Download Gate Stability of GaN-Based HEMTs with P-Type Gate

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Article
Gate Stability of GaN-Based HEMTs with
P-Type Gate
Matteo Meneghini 1, *, Isabella Rossetto 1 , Vanessa Rizzato 1 , Steve Stoffels 2 ,
Marleen Van Hove 2 , Niels Posthuma 2 , Tian-Li Wu 2 , Denis Marcon 2 , Stefaan Decoutere 2 ,
Gaudenzio Meneghesso 1 and Enrico Zanoni 1
1
2
*
Department of Information Engineering, University of Padova, via Gradenigo 6/B, 35131 Padova, Italy;
[email protected] (I.R.); [email protected] (V.R.); [email protected] (G.M.);
[email protected] (E.Z.)
IMEC, Kapeldreef 75, 3001 Heverlee, Belgium; [email protected] (S.S.);
[email protected] (M.V.H.); [email protected] (N.P.); [email protected] (T.L.W.);
[email protected] (D.M.); [email protected] (S.D.)
Correspondence: [email protected]; Tel.: +3904-9827-7664
Academic Editor: Farid Medjdoub
Received: 1 February 2016; Accepted: 15 March 2016; Published: 25 March 2016
Abstract: This paper reports on an extensive investigation of the gate stability of GaN-based High
Electron Mobility Transistors with p-type gate submitted to forward gate stress. Based on combined
electrical and electroluminescence measurements, we demonstrate the following results: (i) the
catastrophic breakdown voltage of the gate diode is higher than 11 V at room temperature; (ii) in
a step-stress experiment, the devices show a stable behavior up to VGS = 10 V, and a catastrophic
failure happened for higher voltages; (iii) failure consists in the creation of shunt paths under the gate,
of which the position can be identified by electroluminescence (EL) measurements; (iv) the EL spectra
emitted by the devices consists of a broad emission band, centered around 500–550 nm, related to the
yellow-luminescence of GaN; and (v) when submitted to a constant voltage stress tests, the p-GaN
gate can show a time-dependent failure, and the time to failure follows a Weibull distribution.
Keywords: gallium nitride; high electron mobility transistor; degradation; step stress
1. Introduction
Gallium nitride transistors have recently been demonstrated to be excellent devices for application
in the power electronics field. Thanks to the high breakdown voltage of GaN (3.3 MV/cm), high
electron mobility transistors (HEMTs) can reach breakdown voltages in excess of 1 kV; in addition,
the high mobility of the electrons in the channel results in a low on-resistance. With regard to this last
aspect, recent on-resistance values reported in the literature are 100 mΩ for a 20 A/650 V transistors [1],
70 mΩ for 600 V AlGaN/GaN devices with a 214 mm gate width [2], and a specific on-resistance of
2.3 mΩ cm2 for normally-off devices with a gate-drain distance of 12 µm [3]. Finally, the wide bandgap
of the semiconductor (3.4 eV) allows for high temperature operation.
The high electron density in the two-dimensional electron gas (2DEG) is obtained thanks to
the spontaneous and piezoelectric polarization of GaN, without the need for any doping; typically,
GaN-based transistors are normally-on devices, with a negative threshold voltage. Several methods
have been recently proposed for the fabrication of normally-off GaN-based transistors: the use of a deep
gate recess, in combination with a metal-insulator-semiconductor (MIS) stack [4]; the implantation of
fluorine ions under the gate [5], that results in a significant depletion of the channel; the use of a p-type
gate material, such as p-AlGaN [6] or p-GaN [7], which shifts the conduction band upwards, thus
resulting in the depletion of the channel for negative gate voltages. As an alternative to these strategies,
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it has been also proposed to develop special E-mode devices, integrating a normally-on GaN HEMT
connected in cascode configuration to a normally-off silicon MOSFET (Metal Oxide Semiconductor
Field Effect Transistor) in the same package [8]. In this last approach, the on/off state of the low-voltage
silicon MOSFET controls the on/off state of the GaN-based high voltage HEMT; the cascoded device
behaves then as an enhancement device, which is compatible with commercial drivers. All of these
approaches have advantages and drawbacks: the use of a gate recess with gate insulator leads to a very
low gate leakage current, but can favor trapping at the interfaces and/or in the insulator, as well as
time-dependent dielectric breakdown; fluorine implantation allows to obtain high (positive) threshold
voltages (>2 V, [9]), but the fluorine ions (and the threshold voltage) can be unstable if the devices are
submitted to long-term stress [10]); the use of a p-type gate requires the optimization and activation of
the p-type dopant (magnesium), i.e., an additional growth step; finally, cascoded HEMTs are rather
complex structures, having two devices mounted on the same package. This can generate reliability
problems, due to the use of extra bonding wires, and to the fact that a silicon-based transistor is used
in proximity of a GaN HEMT that—in principle—can operate at high temperatures.
Several reports on the reliability of MIS-based devices and normally-on HEMTs have already
been published in the literature (see, for instance, [11,12] and references therein). On the other hand,
only little information on the stability of HEMTs with a p-gate is currently available [13,14].
The aim of this paper is to contribute to the understanding of the physical mechanisms responsible
for the failure of GaN-based HEMTs with p-GaN gate submitted to positive bias stress. We present our
recent results on the degradation of transistors with a p-GaN gate submitted to stress with positive
gate voltage. The results of our investigation indicate that the analyzed devices have a (positive)
breakdown voltage higher than 11 V at room temperature, and can show a catastrophic failure when
they are submitted to a step-stress experiment. Information on the nature of the failure mechanism
is provided based on spatially- and spectrally-resolved electroluminescence (EL) measurements and
on optical characterization. Finally, we demonstrate the existence of a time-dependent breakdown
process in positively-biased devices with p-GaN gate.
2. Materials and Methods
The analysis was carried out on HEMTs with p-GaN gate, whose structure is schematically
represented in Figure 1. The devices were grown by metal-organic chemical vapour deposition on
a 200 mm silicon substrate; the epitaxial structure consists of a 200 nm AlN nucleation layer, a 1 µm
AlGaN backbarrier, a 2 µm AlGaN buffer layer, a 300 nm GaN channel layer, a 15 nm Al0.25 Ga0.75 N
barrier, and a 70 nm p-GaN layer. This study is aimed at investigating the stability and degradation of
the p-GaN gate under positive bias conditions. All the measurements were carried out on symmetric
tests structures without field plate, that allow to observe the gate from the top during the execution
of the electroluminescence measurements. The gate width is W G = 100 µm, and the gate length
is LG = 0.8 µm. The electrical measurements were carried out in a probe station equipped with a
semiconductor parameter analyzer (Keysight B1505). The electroluminescence characterization was
carried out by means of a high-sensitivity Si-based camera (Luca Andor, UK), mounted on an optical
microscope with visible-ultraviolet lenses (Mitutoyo, Japan); the synchronization between the electrical
stimulus and the camera was obtained through a customized LabView® software (LabView 2009,
National Instruments, USA).
The electrical characteristics measured on a representative device are plotted in Figure 2; the
threshold voltage is V TH = 1.7 V (at 100 µA/mm, V DS = 1 V), and at higher drain voltages remains
well above 1 V (V TH = 1.32 V at 100 µA/mm, V DS = 10 V).
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Drain
Current
(A/mm)
Drain
Current
(A/mm)
Figure 1. Schematic structure of the samples analyzed within this paper.
Figure 1. Schematic structure of the samples analyzed within this paper.
Figure 1. Schematic
structure of the samples analyzed within this paper.
0
10-1
Drain Voltage
10-2
100-3 from 1V to 10V,
10
step 1V
-1 Drain
Voltage
10-4
10
10-2-5 from 1V to 10V,
10
10-3-6 step 1V
10
10-4-7
10
10-5-8
10
10-6-9
10
-7
10-10
10
-8
10
10-11
-9
10
10-10 0
1
2
10-11
Gate
10
0
1
2
3
4
5
3
4
5
Voltage (V)
Figure 2. Drain current vs gate voltage curves measured on one of the analyzed devices for different
Gate Voltage (V)
drain voltages.
Figure 2. Drain current vs gate voltage curves measured on one of the analyzed devices for different
Figure 2. Drain current vs gate voltage curves measured on one of the analyzed devices for different
3. Results
drain voltages.
drain voltages.
Before starting with the stress experiments, the devices were preliminary submitted to a
3. Results
breakdown
3.
Results stress. The gate voltage was rapidly swept from 0 V to 15 V, and the corresponding gate
Before
with During
the stress
were preliminary
submitted
to a
current
wasstarting
monitored.
the experiments,
measurement,the
thedevices
drain, source
and chuck were
grounded.
Before starting with the stress experiments, the devices were preliminary submitted to
breakdown
stress.
The obtained
gate voltage
was identical
rapidly swept
from
V to 15 V,inand
the 3.
corresponding
gate
Representative
results
on four
samples
are0 reported
Figure
As can be noticed,
a breakdown stress. The gate voltage was rapidly swept from 0 V to 15 V, and the corresponding
current
was
monitored.
During
the
measurement,
the
drain,
source
and
chuck
were
grounded.
the gate current is negligible and below instrument sensitivity (around 100 pA/mm) up to a gate
gate current was monitored. During the measurement, the drain, source and chuck were grounded.
Representative
obtained
four identical
are
in Figure
3. As
can be noticed,
voltage of 8 V results
(the gate
voltageonswing
of these samples
devices is
6 reported
V). For gate
voltages
between
8 V and
Representative results obtained on four identical samples are reported in Figure 3. As can be noticed,
the
gate
current
is
negligible
and
below
instrument
sensitivity
(around
100
pA/mm)
up
to
a gate
11 V, gate current shows an exponential increase, reaching values in the order of 100 nA/mm.
For
the gate current is negligible and below instrument sensitivity (around 100 pA/mm) up to a gate
voltage
of 8 V (the
voltage
swing
of thesegate
devices
is 6 V). For
voltages to
between
V and
higher voltages,
thegate
devices
reach
the forward
breakdown,
thatgate
corresponds
a rapid 8increase
voltage of 8 V (the gate voltage swing of these devices is 6 V). For gate voltages between 8 V and 11 V,
11
gate
currentThis
shows
an exponential
increase,(i.e.,
reaching
values in the
order of 100
nA/mm.have
For
in V,
gate
leakage.
degradation
is permanent
not recoverable),
and—once
the devices
gate current shows an exponential increase, reaching values in the order of 100 nA/mm. For higher
higher
voltages,
the
devices
reach
the
forward
gate
breakdown,
that
corresponds
to
a
rapid
increase
reached the breakdown—the gate current is around 10–100 mA/mm for voltages higher than 12 V.
voltages, the devices reach the forward gate breakdown, that corresponds to a rapid increase in gate
in gate
This degradation
is permanent
(i.e., not
and—once
the devices
have
In leakage.
a dc breakdown
test, the device
fails rapidly,
so recoverable),
it is impossible
to investigate
the physical
leakage. This degradation is permanent (i.e., not recoverable), and—once the devices have reached the
reached
current
is around
10–100
mA/mm
for voltages
higher
than 12 out
V. a
origin ofthe
thebreakdown—the
degradation. To gate
obtain
a better
description
of the
degradation
process,
we carried
breakdown—the gate current is around 10–100 mA/mm for voltages higher than 12 V.
In
a
dc
breakdown
test,
the
device
fails
rapidly,
so
it
is
impossible
to
investigate
the
physical
series of step-stress experiments: the stress voltage applied to the gate was increased by 0.5 V every
In a dc breakdown test, the device fails rapidly, so it is impossible to investigate the physical
origin
thesource,
degradation.
better description
of current
the degradation
process,monitored
we carriedduring
out a
120 s, of
with
drain To
andobtain
chucka grounded.
The gate
was constantly
origin of the degradation. To obtain a better description of the degradation process, we carried out a
series
step-stress
the stress voltage
was increased by 0.5 V every
stress,oftogether
withexperiments:
the electroluminescence
signalapplied
emittedtobythe
thegate
devices.
series of step-stress experiments: the stress voltage applied to the gate was increased by 0.5 V every
120 s, with source, drain and chuck grounded. The gate current was constantly monitored during
120 s, with source, drain and chuck grounded. The gate current was constantly monitored during
stress, together with the electroluminescence signal emitted by the devices.
stress, together with the electroluminescence signal emitted by the devices.
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|Gate Current| (A/mm)
100
10-1
10-2
10-3100
-4
-1
1010
-5 -2
1010
-6 -3
1010
-7 -4
1010
-8 -5
1010
-9 -6
1010
10-7
10-10
10-8
10-11 -9
10
-12
-10
1010
-13
-11
1010
0
-12
4 of 8
Sample 1
Sample 2
Sample 3
Sample 4
|Gate Current| (A/mm)
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10
10-13
Sample 1
Sample 2
Sample 3
Sample 4
VGS=11 V
V =11 V
2
0
2
4 6 8 10 GS
12 14
Gate Voltage (V)
4
6
8 10 12 14
Figure 3. Forward-voltage breakdown
curves
measured
on 4 representative devices.
Gate
Voltage
(V) on
Figure 3. Forward-voltage breakdown
curves
measured
4 representative devices.
3. Forward-voltage
breakdown
curves
measured
on reported
4 representative
devices.4. Gate current
The results Figure
obtained
on one of the
analyzed
samples
are
in Figure
The
results
obtained
on
one
of
the
analyzed
samples
are
reported
in
Figure
4.
Gate current
remains
remains below the instrumentation limit up to a stress voltage of VGS = 7.0 V. During
the subsequent
The
results
obtained
on
one
of
the
analyzed
samples
are
reported
in
Figure
4.
Gate
current
below
the instrumentation
upgate
to a current
stress voltage
of increases
V GS = 7.0during
V. During
thestage
subsequent
steps (for
steps remains
(for
7.5 below
V < VGS
< instrumentation
9.5 limit
V), the
slightly
each
of the step-stress
the
limit upincreases
to a stressduring
voltageeach
of VGS
= 7.0ofV.the
During
the subsequent
7.5
V
<
V
<
9.5
V),
the
gate
current
slightly
stage
step-stress
experiment.
GS
experiment.
The
during
the step
at VGSincreases
= 10 V; after
an each
initial
phase
in which
current
steps (for
7.5failure
V < VGSis<reached
9.5 V), the
gate current
slightly
during
stage
of the
step-stress
The
failureslowly
is reached
during
theleakage
step at V
V; after
an initial
phase
in which
current increases
GS = 10
increases
with
time,
gate
shows
a
rapid
increase
and
reaches
the
compliance
limit.
experiment. The failure is reached during the step at VGS = 10 V; after an initial phase in which current
slowly with time, gate leakage shows a rapid increase and reaches the compliance limit.
increases slowly with time, gate leakage shows a rapid increase and reaches the compliance limit.
4. Results
of a step-stress
experiment
carried
analyzeddevices.
devices.With
Withdrain
drain and
FigureFigure
4. Results
of a step-stress
experiment
carried
outout
on on
oneone
of of
thethe
analyzed
and
source grounded,
the gateexperiment
voltage is increased
by 0.5
V every
120analyzed
s. The corresponding
gatedrain
Figure
4.
Results
of
a
step-stress
carried
out
on
one
of
the
devices.
With
source grounded, the gate voltage is increased by 0.5 V every 120 s. The corresponding gate current
is
current
is
sampled
every
second.
and source
grounded,
sampled
every
second. the gate voltage is increased by 0.5 V every 120 s. The corresponding gate
current is sampled every second.
The spatially-resolved electroluminescence measurements carried out before and during the
step-stress
experiment showed
negligible light emission
up to Vcarried
GS = 9 V out
(Figure
5a); and
this result
is the
The
spatially-resolved
electroluminescence
measurements
before
during
The spatially-resolved electroluminescence measurements carried out before and during the
consistent
with the very
low gate
leakage light
detected
in this voltage
range.
Remarkably,
during
the
step
step-stress
experiment
showed
negligible
emission
up to V
=
9
V
(Figure
5a);
this
result
is
step-stress experiment showed negligible light emission up to VGS
GS = 9 V (Figure 5a); this result is
at
V
GS = 10 V a weak luminescence signal was detected (Figure 5b). Under these conditions light
consistent with the very low gate leakage detected in this voltage range. Remarkably, during the step
consistent withisthe
veryin
low
gate leakage
inregions,
this voltage
range.in
Remarkably,
during
step
proximity
ofsignal
threedetected
localized
and stronger
the area
indicated
bythe
thelight
at V GSemission
= 10 V a focused
weak luminescence
was detected
(Figure
5b). Under
these
conditions
at VGSwhite
= 10arrow
V a weak
luminescence
signal
was
detected
(Figure
5b).
Under
these
conditions
light
in Figure 5b. After failure (and after the corresponding increase in gate leakage), forward
emission is focused in proximity of three localized regions, and stronger in the area indicated by the
emission
is focused
in proximity
of three
localized
regions, and
the areaspot
indicated
by the
current
flows mostly
in a localized
area located
in proximity
of thestronger
dominantinemission
identified
white arrow in Figure 5b. After failure (and after the corresponding increase in gate leakage), forward
whitebefore
arrowfailure
in Figure
5b. After
failure
(compare
Figure
5b,c).(and after the corresponding increase in gate leakage), forward
current flows mostly in a localized area located in proximity of the dominant emission spot identified
before failure (compare Figure 5b,c).
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current flows mostly in a localized area located in proximity of the dominant emission spot identified
before failureElectronics
(compare
Figure 5b,c).
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Figure 5. Spatially-resolved electroluminescence measurements carried out along the gate of the
analyzed devices (a) atelectroluminescence
the beginning of the stress measurements
atmeasurements
VGS = 9.5 V, (b) at carried
the
beginning
ofalong
the
stress
at gate
Figure 5.
5. Spatially-resolved
Spatially-resolved
electroluminescence
carried
out
along
the
gate of
of the
the
Figure
out
the
V and
(c)
after
the catastrophic
failure.
VGS = 10(a)
analyzed
devices
at
the
beginning
of
the
stress
at
V
=
9.5
V,
(b)
at
the
beginning
of
the
stress
at
analyzed devices (a) at the beginning of the stress at VGS
GS= 9.5 V, (b) at the beginning of the stress at
VGS
10VVand
and
(c)after
afterthe
the
catastrophic
failure.
GS==10
(c)
catastrophic
failure.
V
More
detailed
data
on the origin
of the luminescence signal were collected by means of
spectrally-resolved electroluminescence measurements. The EL spectra were measured on the same
sample of Figure 5 (after stress) by applying a constant gate current of 1 mA to the gate of the devices.
More
data
More detailed
detailed
data on
on the
the origin
origin of
of the
the luminescence
luminescence signal
signal were
were collected
collected by
by means
means of
of
The measurements were carried out by means of a high sensitivity cooled CCD (charge-coupled
spectrally-resolved
electroluminescence
measurements.
The
EL
spectra
were
measured
on
the
same
spectrally-resolved
electroluminescence
measurements.
The
EL
spectra
were
measured
on
the
same
device) camera equipped with a monochromator. Figure 6 reports the EL spectra emitted by the same
sample
in Figure
5. Theby
device
emits a broad
luminescence
centered
500–550
nm.
The
sample
55as
(after
stress)
applying
aaconstant
gate
current
of
of
sample of
of Figure
Figure
(after
stress)
by
applying
constant
gatepeak
current
of1around
1mA
mAto
tothe
thegate
gate
ofthe
thedevices.
devices.
origin of luminescence can be explained by considering that—under high forward bias—a high
The
The measurements
measurements were
were carried
carried out
out by
by means
means of
of aa high sensitivity
sensitivity cooled
cooled CCD
CCD (charge-coupled
(charge-coupled
current of energetic electrons flows through the p-GaN/i-AlGaN junction. The flow of highly
device)
equipped
with
a
monochromator.
Figure
6
reports
the
EL
spectra
emitted
device) camera
camera
equipped
with
a
monochromator.
Figure
6
reports
the
EL
spectra
emitted
by the
the same
same
energetic electrons can induce the ionization of the deep levels responsible for the yellow by
ofThe
GaN
(consistently
It is worth noticing
that centered
the gate
voltage
of
the 500–550
sample
Figure
device
emits
awith
broad
luminescence
peakpeak
centered
around
500–550
nm. The
sampleas
asininluminescence
Figure5.5.The
device
emits
a [13,15,16]).
broad
luminescence
around
nm.
devices remains stable during the whole duration of the EL spectral measurements (see Figure 6),
origin
of luminescence
can can
be be
explained
byby
considering
that—under
The origin
of luminescence
explained
considering
that—underhigh
highforward
forwardbias—a
bias—a high
high
demonstrating that the spectral measurement does not induce any further degradation.
current
ofenergetic
energeticelectrons
electrons
flows
through
the p-GaN/i-AlGaN
junction.
The
highly
current of
flows
through
the p-GaN/i-AlGaN
junction.
The flow
of flow
highlyofenergetic
6.0 levels
energetic
electrons
induce the
ionization
of responsible
the deep
for the of
yellow
electrons can
induce can
the ionization
of 6.0m
the
deep levels
for theresponsible
yellow luminescence
GaN
I = 1mA
5.0m
luminescence
of GaN
(consistently
with [13,15,16]).
It is
noticingofthat
gate remains
voltage of
the
(consistently with
[13,15,16]).
It is worth
noticing that
theworth
gate voltage
the the
devices
stable
4.0m
devices
remains
during
the EL
whole
duration
of the EL 5.5
spectral
measurements
(see Figure
6),
during the
wholestable
duration
of the
spectral
measurements
(see Figure
6), demonstrating
that the
3.0m
demonstrating
that thedoes
spectral
does degradation.
not induce any further degradation.
spectral measurement
not measurement
induce any further
Gate Voltage (V)
5.0
2.0m
6.0m1.0m
Intensity (a.u.)
5.0m
0.0
4.5
6.0
IG = 1mA
-1.0m
4.0
4.0m 400 450 500 550 600 650 700
Wavelength (nm)
3.0m
Gate Voltage (V)
Intensity (a.u.)
G
5.5
Figure 6. EL (electroluminescence) spectra evaluated from λ = 400 nm5.0
to λ = 720 nm on the same
device as Figure 5 after 2.0m
the stepstress. The gate voltage measured during the acquisition of each
wavelength is also reported.
1.0m
4.5
0.0
-1.0m
4.0
400 450 500 550 600 650 700
Wavelength (nm)
Figure
(electroluminescence)spectra
spectraevaluated
evaluated
from
= 400
λ =nm
720onnm
the device
same
Figure 6. EL (electroluminescence)
from
λ =λ400
nm nm
to λ to
= 720
theon
same
device
as 5Figure
5 after
the stepstress.
The gate
voltageduring
measured
during theofacquisition
of each
as Figure
after the
stepstress.
The gate voltage
measured
the acquisition
each wavelength
is
wavelength
is also reported.
also reported.
Electronics
Electronics 2016, 5, 14
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The
results collected during the last stage of the stress step experiment in Figure 4 indicate
that
Electronics 2016, 5, 14
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The
results
collected
during
the
last
stage
of
the
stress
step
experiment
in
Figure
4
indicate
that
the catastrophic degradation does not occur immediately after the stress is applied, but after several
the
catastrophic
degradation
does
not
occur
immediately
after
the
stress
is
applied,
but
after
several
results collected
last result
stage ofsuggests
the stress that
step experiment
Figurea4 time-dependent
indicate that
seconds ofThe
operation
at VGS during
= 10 V.theThis
the devicesinshow
seconds
of
operation
at V GS =this
10does
V. This
suggests
the
devices
a time-dependent
failure.
theTo
catastrophic
degradation
notresult
occur
immediately
after
the
stressshow
is applied,
but after
failure.
better
investigate
aspect,
we
carried
out athat
set
of constant
voltage
stress
tests several
at voltages
seconds
of
operation
at
V
GS = we
10
V.
This
result
suggests
that
the
devices
show
a
time-dependent
To
better
investigate
this
aspect,
carried
out
a
set
of
constant
voltage
stress
tests
at
voltages
close
close to (but smaller than) the dc breakdown voltage. Figure 7 reports the results obtained
by
failure.
To better
investigate
this aspect, voltage.
we carriedFigure
out a set7 of
constant
voltage
stress
tests at voltages
to
(but
smaller
than)
the
dc
breakdown
reports
the
results
obtained
by
stressing
stressing identical samples with a gate voltage of 9.75 V, and source, drain, and chuck grounded. As
closesamples
to (but smaller
than) voltage
the dc breakdown
voltage.
Figure
7 reportschuck
the results obtained
identical
withinitial
a gate
of 9.75
V, experiment
and
source,
drain,
As by
can be
can
be noticed,
in the
phase of the
stress
the
gateand
current is grounded.
very low and
stable;
stressing identical samples with a gate voltage of 9.75 V, and source, drain, and chuck grounded. As
noticed,
in
the
initial
phase
of
the
stress
experiment
the
gate
current
is
very
low
and
stable;
this
phase
this phase
is followed by a gradual increase in gate leakage, that—for most of the samples—changes
can be noticed, in the initial phase of the stress experiment the gate current is very low and stable;
is followed
by a gradual
increase
in gateoccurs
leakage, that—for
most
of the samples—changes
of 2–3 orders
of
2–3this
orders
magnitude.
Failure
a sudden
increase
in gate
(reaching
the
phase of
is followed
by a gradual
increase inasgate
leakage, that—for
most
of theleakage
samples—changes
of
magnitude.
Failure
occurs
as
a
sudden
increase
in
gate
leakage
(reaching
the
compliance
value
compliance
mA/mm).Failure occurs as a sudden increase in gate leakage (reaching the of
of 2–3 value
ordersof
of10
magnitude.
10 mA/mm).
compliance value of 10 mA/mm).
100
Gate Current (A/mm)
Gate Current (A/mm)
0
Voltage = 9.75 V
10Gate
10-1 Source,
Gate Voltage
9.75Chuck
V
Drain =and
grounded
-1
10
-2
Source, Drain and Chuck grounded
10 -2
10
10-3
10-3
-4
1010
-4
-5
-5
1010
-6 -6
1010
-7 -7
1010
-8
1010
-8
-9
1010
-9
10-10
10-10 10-1 100
10-1 100
101
102
1
2
10time
10
(s)
time (s)
103 3
10
104
104
Figure 7. Results of constant voltage stress tests carried out on eight identical devices with a gate bias
Figure 7.
7. Results
Results of
of constant
constant voltage
voltage stress
stress tests
tests carried out
out on eight identical devices with a gate bias
Figure
of 9.75
V, source,
drain and substrate
connectedcarried
to ground. on eight identical devices with a gate bias
of 9.75
9.75 V,
V, source,
of
source, drain
drain and
and substrate
substrate connected
connected to
to ground.
ground.
The time-to-failure was found to follow a Weibull distribution (Figure 8), with a shape factor β
of 2.25
(indicating that
thefound
failure to
rate
increases
with time)
and a scale(Figure
parameter
(time
63.2%
The
time-to-failure
was
found
tofollow
follow
Weibull
distribution
(Figure
with
awhich
shape
factor
β
The
was
aaWeibull
distribution
8),8),
with
aatshape
factor
β of
of
samples
failed)
η
of
1454
s.
The
time
to
failure
is
supposed
to
become
shorter
with
increasing
stress
of
2.25
(indicating
that
failure
rate
increases
with
time)
and
a scale
parameter
(time
which
63.2%
2.25
(indicating
that
thethe
failure
rate
increases
with
time)
and
a scale
parameter
(time
at at
which
63.2%
of
voltages.
By analyzing
the
meantime
timeto
tofailure
failure during
stress at
different
voltage
levels,
we
estimated
of
samples
failed)
η
of
1454
s.
The
is
supposed
to
become
shorter
with
increasing
stress
samples failed) η of 1454 s. The time to failure is supposed to become shorter
stress
that the devices have a twenty-years lifetime for a gate voltage of 7.2 V; this value is significantly
voltages. By
By analyzing
analyzing the
the mean
mean time
time to
to failure
failure during
during stress
stress at
at different
different voltage
voltage levels,
levels, we
we estimated
estimated
higher than the typical gate operating voltage (5 V).
that
that the
the devices
devices have
have aa twenty-years
twenty-years lifetime
lifetime for
for aa gate
gate voltage
voltage of
of 7.2
7.2 V;
V; this
this value
value is
is significantly
significantly
higher
than
the
typical
gate
operating
voltage
(5
V).
higher
3
ln(-ln(1-Ft))
32
ln(-ln(1-Ft))
2
1
1
0
-1
0
-1
-2
-3
-2 -4
-3
102
103
104
TTF (s)
Figure 8. Weibull distribution
-4 of time-to-failure for the analyzed devices. β = 2.25, η = 1454 s.
102
103
104
TTF (s)
Figure 8. Weibull distribution of time-to-failure for the analyzed devices. β = 2.25, η = 1454 s.
Figure 8. Weibull distribution of time-to-failure for the analyzed devices. β = 2.25, η = 1454 s.
Electronics
2016, 5,2016,
14 5, 14
Electronics
7 of7 8of 8
The time-dependent failure process described above can be interpreted based on the following
The
time-dependent
failure process
described
above
can
be interpretedfailure
basedhas
on been
the following
considerations.
In reverse-biased
Schottky
junctions,
the
time-dependent
ascribed to
considerations.
In
reverse-biased
Schottky
junctions,
the
time-dependent
failure
has
been
ascribed
to
the degradation of the AlGaN layer, that is subject to a high electric field [15,17]. However,
the devices
the degradation
of thethis
AlGaN
layer,
that is subject
to a highgate
electric
[15,17].
However,
devices
analyzed within
paper
are submitted
to a positive
bias, field
and 2D
simulations
[13]the
demonstrate
analyzed
this paper
a positive
gate bias,
and 2D significantly
simulations during
[13] demonstrate
that within
the absolute
valueare
of submitted
the electrictofield
in the AlGaN
decreases
stress, with
that the
absolute
value
of the electric
field infailure
the AlGaN
decreases
stress, withof
respect
to rest
conditions.
The observed
can therefore
notsignificantly
be ascribed during
to the degradation
respect
rest conditions.
thetoAlGaN
barrier. The observed failure can therefore not be ascribed to the degradation of the
Two other mechanisms can therefore be considered:
AlGaN barrier.
(i) other
at high
(positive) gate
bias, the electric
field in the p-GaN can significantly increase (see the
Two
mechanisms
can therefore
be considered:
simulations in [13]), since the Schottky metal/p-GaN diode is reversely biased and the p-GaN is
(i) at high
(positive)
gate
electric
in the
can significantly
increase
the
partly
depleted.
Thebias,
high the
electric
field field
can favor
thep-GaN
generation
of defects in the
p-GaN,(see
similarly
simulations
in
[13]),
since
the
Schottky
metal/p-GaN
diode
is
reversely
biased
and
the
p-GaN
to what observed in the AlGaN barrier under negative bias [15,18,19]. This may lead the
is partly
depleted.
The high
electric
field
favor thefailure
generation
defects
in theAvalanche
p-GaN,
generation
of leakage
paths
and to
thecan
consequent
of theofgate
junction.
similarly
to
what
observed
in
the
AlGaN
barrier
under
negative
bias
[15,18,19].
This
may
lead
effects (proposed in [13]) can further accelerate the defect generation process.
the
generation
of
leakage
paths
and
to
the
consequent
failure
of
the
gate
junction.
Avalanche
(ii) during positive voltage stress the SiN passivation may be exposed to a high electric field,
effects
(proposed
[13]) can further
the This
defectmay
generation
process.
especially
in inproximity
of the accelerate
gate edge.
lead to
a time-dependent (and
geometry-dependent)
failure
SiN, with consequent
(ii) during
positive voltage dielectric
stress the
SiNofpassivation
may be increase
exposedintogate
a leakage.
high electric
field, especially in proximity of the gate edge. This may lead to a time-dependent (and
4.
Conclusions
geometry-dependent)
dielectric failure of SiN, with consequent increase in gate leakage.
In summary, in this paper we have described an analysis of the degradation mechanisms of
4. Conclusions
GaN-HEMTs with p-type gate submitted to positive bias stress. The results demonstrate that in the
operating
voltage
range
(upwe
to 7have
V) the
devices have
an high robustness
towards stress.
In addition,
In
summary,
in this
paper
described
an analysis
of the degradation
mechanisms
of
based onwith
the results
dc submitted
breakdowntomeasurements,
step-stress
experiment
and constant
voltage
GaN-HEMTs
p-type of
gate
positive bias stress.
The results
demonstrate
that in
the
tests,voltage
we demonstrated
that
thethe
transistors
can show
a time-dependent
failurestress.
whenIn
submitted
operating
range (up to
7 V)
devices have
an high
robustness towards
addition,to
forward
gate
stress
at
higher
voltages
(V
GS > 9 V). The failure corresponds to an increase in gate
based on the results of dc breakdown measurements, step-stress experiment and constant voltage tests,
leakage, thatthat
is the
welltransistors
correlated
the ageneration
of hot-spots,
identified
by means
of EL
we demonstrated
cantoshow
time-dependent
failure when
submitted
to forward
measurements.
Possible
mechanisms
responsible
for
this
failure
have
been
discussed
based
on
the
gate stress at higher voltages (VGS > 9 V). The failure corresponds to an increase in gate leakage, that
experimental
evidence
collected
within
this
paper.
is well correlated to the generation of hot-spots, identified by means of EL measurements. Possible
mechanisms
responsible This
for this
failure
been
discussed
on the experimental
evidence
Acknowledgments:
project
has have
received
funding
frombased
the Electronic
Component Systems
for
collected
withinLeadership
this paper. Joint Undertaking under grant agreement No 662133. This Joint Undertaking
European
receives support
the has
European
Union’s
Horizon
2020
researchComponent
and innovation
programme
and
Acknowledgments:
Thisfrom
project
received
funding
from the
Electronic
Systems
for European
Austria,
Germany,
Italy,agreement
Netherlands,
Norway,
Spain, United
This
Leadership
JointBelgium,
Undertaking
under grant
No 662133.
ThisSlovakia,
Joint Undertaking
receivesKingdom.
support from
the European
Union’sonly
Horizon
2020 research
programme
and Austria,
Belgium,
Germany,
Italy,of
article reflects
the authors’
viewand
andinnovation
the JU is not
responsible
for any use
that may
be made
Netherlands, Norway, Slovakia, Spain, United Kingdom. This article reflects only the authors’ view and the JU is
the information it contains.
not responsible for any use that may be made of the information it contains.
Conflicts
of Interest:
The declare
authorsno
declare
Conflicts
of Interest:
The authors
conflictnoofconflict
interest.of interest
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