Download EE271: Practice Problems 1: Draw schematics for the following logic

EE271: Practice Problems
1: Draw schematics for the following logic equations, without optimizing them:
Y = AB+C
Y = A(B+C)
Y= A+B+C+ ABC
Y = ABC + ABC + ABC
2: Use DeMorgan’s Law to invert these logic expressions:
Y = A + BC
Y = A + ABC + AB
Y = A + BC + ABC
Y = ABC + ABC + AC
3: Simplify these expressions using k-maps:
Y= ABCD+ ABCD+AD+ ABD+ABD
Don’t Care: A B C D
Y = ABC + ABC + ABC
Y = ABCD + ABCD + ABC
4: Write a system verilog module for a full adder.
5: Write a system verilog module that takes the compliment of an 8-bit number (flip all 1 to 0 and all 0
to 1)
6: Convert these numbers to two’s compliment binary:
51
33
-24
199
-17
-9
-1012
7a: Assuming a fixed point unsigned number scheme with the decimal point placed as in:
BBBB.BBBB, convert these numbers to decimal:
10101100
11111111
10010001
10011000
7b: convert these to the fixed point scheme. (You may have to round somewhat.)
12.4
3.14159
11.2
1.125
1.11111
8: Assuming a floating point, two’s compliment scheme with 3 bits of exponent and 5 bits of mantissa,
arranged as MMMMMEEE, find the smallest and largest non-zero numbers that can be represented.
9: Given the scheme from problem 8, convert the following numbers to decimal notation:
10000111
00011010
11111111
00100000
10: Write the logic function for a 4:1 multiplexer.
11: If a D Latch has a logic 1 applied to its D input and a square wave applied to its Latch input, what
will be its output?
12: Design a four state state machine with the following properties: The state variable goes from 0 to 1,
then to 2, then to 3, then back to 1, looping as 1,2,3. If the input A is 0, this behavior continues, but if A
is 1, then the state machine should go to 0 and stay there until A is released, at which point the state
machine returns to 1, and continues looping.