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HCL and ALU
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Overview of Logic Design


Fundamental Hardware Requirements
–
Communication: How to get values from one place to another
–
Computation
–
Storage
Bits are Our Friends
–
Everything expressed in terms of values 0 and 1
–
Communication
•
–
Computation
•
–
Low or high voltage on wire
Compute Boolean functions
Storage
•
Store bits of information
Digital Signals
0
1
0
Voltage
Time
Use voltage thresholds to extract discrete values from
continuous signal
– Simplest version: 1-bit signal
–
•
•
–
Either high range (1) or low range (0)
With guard range between them
Not strongly affected by noise or low quality circuit
elements
•
Can make circuits simple, small, and fast
HCL (hardware control language)
HCL
- Describes the control logic of different processor design.
Logic
Gate Types
- Logic gates are always active
- Input → ... time → output
Rising Delay
Voltage
Falling Delay
a && b
b
a
Time
Combinational Circuits and HCL
Combinational
circuit
- Combination of logic gates
- Output cannot be connected together
- Acyclic
Combinational
circuit to test for bit equality
- The output will equal 1 when both inputs are 0, or both are 1.
HCL code : Bool eq = (a && b) || (!a && !b)
Combinational Circuits and HCL
Multiplexor
- Sets a value depending on a control input signal
- The output will equal a when s is 1, and b when s is 0.
HCL code : Bool out = (s && a) || (!s && b)
Combinational Circuits and HCL
HCL versus C
- Change occurs over time
- There is no real assignment, just assignment to expressions
- Expressions cannot be partially evaluated
Example:
(a && !a) && func(b,c)
Combinational Circuits and HCL
Word--level equality test circuit
Word
HCL code : Bool EQ = ( A == B)
Combinational Circuits and HCL
Word-level multiplexor
WordHCL
(case expression)
- 1 stands for default
Combinational Circuits and HCL
Mux 4
int Out4 = [
!s1 && !s0 : A;
!s1
: B;
s1 && !s0 : C;
1
: D;
];
Min 3
int Min3 = [
A <= B && A <= C : A;
B <= A && B <= C : B;
1
: C;
];
Arithmetic Logic Unit
0
Y
X
A
B
1
A
L
U
Y
A
X+Y
OF
ZF
CF
X
A
L
U
B
2
Y
A
X-Y
OF
ZF
CF
X
B
A
L
U
3
Y
A
X&Y
OF
ZF
CF
X
Combinational logic
Continuously responding to inputs
Control signal selects function computed
Corresponding to 4 arithmetic/logical operations in Y86
Also computes values for condition codes
B
A
L
U
X^Y
OF
ZF
CF
Basic ALU (Combinational Circuit)


The basic ALU provides the basic logical and arithmetic functions:
AND, OR plus addition.
Shift, multiplication and division are usually outside the basic ALU.
Logical operations
a
0
MUX
b
result
1
select (AND or OR)
1 bit logical unit for AND/OR operations
The ALU

ALU includes combinational logic.
–
–

Combinational logic  a change in inputs directly causes a change
in output, after a characteristic delay.
Different from sequential logic which only changes on the clock.
Two major components of combinational logic are –
multiplexors & decoders.
0
0
1
1
0
2
3
c
4
1
2
DECODER
4
5
2
5
3
6
6
7
7
s0
s1
s2
3 X 8 multiplexor
3 X 8 Decoder
1 bit FULL adder (3,2)
Carry out
a
b
a
Carry in
Cout
Cin
Cin
sum
a
b
outputs
sum
Cout
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
sum = (a  b  Cin) + (a  b  Cin) + (a  b  Cin)
Cout
b
inputs
Cin
Adder hardware for Cout
in 2 layers
+ (a b  Cin) = a + b + Cin
Cout =(b  Cin) + (a  Cin) + (a  b)
= ((a + b)  Cin) + (a  b)
Full Adder from Half Adders
Half
adder
a
b
sum
Cout
Full
adder from 2 half adders + or gate
Cin
a
sum
b
Cout
1 Bit Simple ALU
1 bit simple ALU for logical / arithmetic operations
Cin
select
2
a
0
1
b
+
Cout
2
result
1 Bit Enhanced ALU
Enhanced for subtraction
invert
Cin
select
2
a
0
1
b
0
+
2
1
1's complement
Cout
2's complement: use Cin = 1
subtraction: a + b + 1 = a + (b + 1) = a + (-b) = a - b
result
Ripple Carry Type Adder
32 bit ADDER with ripple carry:

To produce a 32 bit result, we
connect 32 single bit units
together.
a0
b0
a1
This type of ALU adder is called a
ripple adder
a2
–
–
–
Carry bits are generated in
sequence.
Bit 31 result and Cout is not correct
until it receives Cin from previous
unit, which is not correct until it
receives Cin from its previous unit,
etc.
Total operation time is proportional
to word size (here 32).
operation = invert
+ select
3
Cin
result 0
ALU0
Cout
Cin
result 1
ALU1
b1

Cin
Cout
Cin
result 2
ALU2
b2
Cout
.
.
.
.
.
.
a31
b31
Cin
ALU31
Cout
Cout
result 31