Download Effects of metal gate-induced strain on the performance of metal

Effects of metal gate-induced strain on the performance of metal-oxidesemiconductor field effect transistors with titanium nitride gate electrode
and hafnium oxide dielectric
Chang Yong Kang, Rino Choi, M. M. Hussain, Jinguo Wang, Young Jun Suh et al.
Citation: Appl. Phys. Lett. 91, 033511 (2007); doi: 10.1063/1.2766667
View online: http://dx.doi.org/10.1063/1.2766667
View Table of Contents: http://apl.aip.org/resource/1/APPLAB/v91/i3
Published by the American Institute of Physics.
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APPLIED PHYSICS LETTERS 91, 033511 共2007兲
Effects of metal gate-induced strain on the performance of metal-oxidesemiconductor field effect transistors with titanium nitride gate
electrode and hafnium oxide dielectric
Chang Yong Kang,a兲 Rino Choi,b兲 and M. M. Hussain
SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741
Jinguo Wang, Young Jun Suh, H. C. Floresca, Moon J. Kim, and Jiyoung Kimc兲
The University of Texas at Dallas, P.O. Box 830688, Richardson, Texas 75083-0688
Byoung Hun Lee and Raj Jammy
SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741
共Received 16 April 2007; accepted 4 July 2007; published online 19 July 2007兲
In this letter, the authors investigate the strain induced by titanium nitride 共TiN兲 electrode and
effective work function 共EWF兲 tuning for metal-oxide-semiconductor field effect transistors
共MOSFETs兲. Scaling of TiN thickness was found to be effective both in increasing tensile stress on
Si substrates and in lowering the EWF of metal gate n-MOSFETs. The device with 3 nm TiN as a
gate electrode showed favorable threshold voltage 共Vth兲 for n-MOSFETs as well as higher channel
electron mobility by 17% compared to the device with 20 nm TiN film. © 2007 American Institute
of Physics. 关DOI: 10.1063/1.2766667兴
Various strain techniques such as strained silicon-oninsulator, silicon-germanium 共SiGe兲 substrate, dual stress
liner 共DSL兲, and stress memorization are being intensively
investigated as a way to enhance device performance.1–5 The
DSL technique is implemented with minimal addition of
complexity and cost to the conventional device fabrication
processes.
As gate dielectrics are scaled down, a metal gate/high-k
gate stack is an inevitable choice for further equivalent oxide
thickness 共EOT兲 and channel length scaling.6–9 Recent reports have addressed dual metal electrode complementary
metal-oxide-semiconductor field effect transistor 共CMOSFET兲 integration with different metal films for separately adjusting threshold voltages for both n-MOSFETs and
p-MOSFETs.10,11 Choi et al. reported that the effective metal
work function could be modulated by changing the thickness
of the metal.12 It is known that a thin metal layer intrinsically
induces a certain amount of stress depending on the deposition method, film thickness, and thermal treatment,13 which
means that a metal layer can also be exploited as a stressor
layer. With a selection of right materials, it would be possible
to use the dual metal gate electrodes to apply the stresses on
the channel. However, few reports have addressed a metalinduced strain engineering approach. In this work, we investigate the effects of metal-induced strain engineering on device characteristics, such as threshold voltage, interface
states, and carrier mobility in conjunction with physical
analysis methods.
To study the effect of titanium nitride 共TiN兲 thickness on
device characteristics, samples with various TiN thicknesses
were prepared. Transistors with a channel length of about
70 nm were fabricated using a standard CMOS process.
30 Å of HfO2 film deposited on a 10 Å SiO2 layer using
atomic layer deposition 共ALD兲 was used as a gate dielectric.
a兲
Electronic mail: [email protected]
Electronic mail: [email protected]
c兲
Electronic mail: [email protected]
b兲
0003-6951/2007/91共3兲/033511/3/$23.00
The ALD TiN thickness ranged from 3 to 20 nm. The
source/drain activation and a postmetallization anneal were
performed at 1000 ° C / 10 s. The EOT of the complete device was 1.3 nm; the channel length 共Lgate兲 was in the
60– 80 nm range.
Electron energy-loss spectroscopy 共EELS兲 analysis was
carried out to profile the composition of TiN and HfO2 layers
after device fabrication 共Fig. 1兲. The top portion of the TiN
was oxidized and became nitrogen deficient. For thinner TiN
layer, this nitrogen-deficient region extended down to the
bottom of the TiN resulting in nitrogen-deficient TiN formation. For a thin TiN sample, therefore, this nitrogen-deficient
TiN resulted in a lower effective work function and lower Vth
as shown in Fig. 2共a兲. Therefore, the 3 nm TiN electrode
FIG. 1. 共Color online兲 Depth profile of atoms in TiN and HfO2 layers using
electron energy-loss spectroscopy 共EELS兲 analysis. After the thermal treatments, the top portion of the TiN was oxidized and became the nitrogen
deficient.
91, 033511-1
© 2007 American Institute of Physics
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033511-2
Kang et al.
Appl. Phys. Lett. 91, 033511 共2007兲
FIG. 2. 共Color online兲 Effects of TiN thickness on Vth and Nit and 共b兲
electron mobility at 1 MV/ cm. The 3 nm TiN devices recovered more
quickly than that of 20 nm TiN. This suggests that the 3 nm TiN led to
higher tensile stress transversely toward the channel than the 20 nm TiN,
which matches the results from the CBED analysis.
yielded a lower n-MOS Vth than that of the thicker TiN
samples. In addition, the interface state density 共Nit兲 was
slightly increased as the TiN became thinner. Thus, it is expected that the carrier mobility of the 3 nm TiN sample
should be lower than that of thicker devices.14 With thinner
TiN, however, the electron mobility calculated at 1 MV/ cm
was increased as shown in Fig. 2共b兲. For the 3 nm TiN
samples, furthermore, electron mobility increased in the
entire electric field regime 关inset of Fig. 2共b兲兴. This contradiction, therefore, should be counted by the additional carrier mobility enhancement due to metal gate-induced strain
engineering.
Metal-induced strain has been measured using a waferbowing test for the various TiN deposition methods as shown
in Fig. 3共a兲. For the film stress measurements, various thicknesses of TiN were deposited on top of 100 nm SiO2 using
chemical vapor deposition 共CVD兲, ALD, and physical vapor
deposition 共PVD兲 methods. High tensile stress induced by
thin TiN film was relieved as TiN film becomes thicker. At
around 20 nm TiN, the film stress for both ALD and CVD
TiN samples was almost neutral. For the PVD TiN film, tensile stress is more significant. Even at 20 nm TiN, the film
stress was compatible to that of the 7 nm ALD and CVD TiN
samples. Lim et al. reported that the PVD TiN film stress
increased with decreasing its thickness due to the change of
preferred orientation.15 For further reducing the TiN thickness below 3 nm, the TiN island structure is formed rather
than a layer, and the TiN-induced strain cannot be measured
FIG. 3. 共Color online兲 TiN film stress as a function of TiN thickness and
deposition method. With decreasing TiN thickness, higher tensile stress was
applied to Si. 共b兲 CBED diffraction pattern for the 3 nm TiN. The strains
were 0.44% for ␴yy and −0.42% for ␧zz. 共c兲 For the 20 nm TiN sample, the
strain from CBED analysis shows that ␴yy and ␴zz were 0.13% and −0.04%,
respectively.
by the wafer-bowing test. For device performance, tensile
stress and compressive stress along the channel direction are
more desirable for designing n-MOSFETs and p-MOSFETs,
respectively. Therefore, thin TiN is expected to be an excellent choice for enhancing the performance of n-MOS gate
electrodes.
Since the stress measured by the wafer-bowing test represents a global stress over the silicon substrate, a convergent
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033511-3
Appl. Phys. Lett. 91, 033511 共2007兲
Kang et al.
devices. From the electrical characterization under the mechanical wafer bending, the amount of Vth shift was much
less than the Vth shift from the TiN phase change 共data not
shown兲.
In summary, TiN-induced strain engineering for metal
gate/high-k dielectric MOSFETs was evaluated. For
n-MOSFETs, thinner TiN was found to increase tensile stress
on Si substrates as well as lower the threshold voltage. The
3 nm TiN device is an excellent choice for the n-MOSFETs
regarding Vth and performance. Electron mobility in
n-MOSFET with 3 nm TiN gate electrode was improved by
17% compared to that with 20 nm TiN electrode.
One of the authors 共J.K.兲 acknowledges partial financial
support through System 2010 by COSAR. Two of the authors 共B.H.L. and R.J.兲 are IBM assignees at SEMATECH.
1
FIG. 4. 共Color online兲 Calculated mobility enhancement based on PR
model. ⌬␮ between the 3 nm TiN and the 20 nm TiN was about 17%, which
is closer to the calculated results from the biaxial stress condition in the
具110典 orientation.
beam electron diffraction 共CBED兲 analysis was carried out
on the 3 and 20 nm ALD TiN on 3 nm HfO2 dielectric MOS
capacitor structures 关Figs. 3共b兲 and 3共c兲兴 in order to quantify
the strain at silicon channel.16 For the 3 nm TiN sample, the
metal-induced Si lattice displacements at 50 nm below the Si
surface were 0.44% and −0.42% for the horizontal direction
共␴yy兲 and the perpendicular direction 共␴zz兲, respectively.
These lattice mismatches decreased in the 20 nm TiN
samples, which were 0.13% for the ␴yy and −0.04% for the
␴zz. The measured lattice strain showed that the 3 nm TiN
film induced a higher tensile stress on Si than the 20 nm TiN
film horizontally and that it qualitatively matched from the
wafer-bowing test. The calculated stress difference was
390 MPa for ␴yy.
It is known that many material properties are changed
including, and most significant to silicon technology, band
gap, effective mass, mobility, Vth, diffusivity of dopants, and
oxidation rates when the band structure of a material is
changed.17 Colman et al., reported that the strain effects on
mobility are anisotropic18 and carrier population effects are
different for bulk silicon and inversion layers. The piezoresistance 共PR兲 effect was widely accepted to explain and calculate the effects of strain on mobility enhancement in silicon substrates.19,20 To explain the metal-induced mobility
improvement in this work, the amount of mobility enhancement was calculated based on the PR model for the both
biaxial and uniaxial stress conditions 共Fig. 4兲. In the PR
model, the mobility enhancement can be expressed as
⌬␮ / ␮ = ␲l␴l + ␲t␴t. The PR coefficient is shown in the inset
of Fig. 4.19,20 ⌬␮ / ␮ is the fractional change in mobility, and
␲l and ␲t are the longitudinal and transverse PR coefficients
expressed in Pa−1, respectively. ␴l is the longitudinal stress,
and ␴t is the transverse stress. As shown previously, the thinner TiN induced higher tensile strain. ⌬␮ between the 3 nm
TiN and the 20 nm TiN was about 17%, which is closer to
the calculated results from the biaxial stress condition in the
具110典 orientation. This finding indicates that the metal electrode mainly induced biaxial stress than uniaxial stress.
Therefore, the metal-induced biaxial stress is the primary
cause of the mobility enhancement in TiN gate electrode
V. Chan, R. Rengarajan, N. Rovedo, J. Wei, T. Hook, P. Nguyen, C. Jia, E.
Nowak, C. Xiang-Dong, D. Lea, A. Chakravarti, V. Ku, S. Yang, A.
Steegen, C. Baiocco, P. Shafer, N. Hung, H. Shih-Fen, and C. Wann, Tech.
Dig. - Int. Electron Devices Meet. 2003, 3.8.1.
2
P. R. Chidambaram, B. A. Smith, L. H. Hall, H. Bu, S. Chakravarthi, Y.
Kim, A. V. Samoilov, A. T. Kim, P. J. Jones, R. B. Irwin, M. J. Kim, A. L.
P. Rotondaro, C. F. Machala, and D. T. Grider, Tech. Dig. VLSI Symp.
2004, 48.
3
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T.
Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A.
Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki,
S. Thompson, and M. Bohr, Tech. Dig. - Int. Electron Devices Meet.
2003, p. 11.6.1.
4
R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P. R. Chidambaram, M.
Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J. P.
Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall,
H. Alshareef, A. Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J.
DeLoach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, and T.
Grider, Tech. Dig. VLSI Symp. 2004, 162.
5
K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T.
Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang,
S. Thompson, and M. Bohr, Tech. Dig. VLSI Symp. 2004, 50.
6
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243
共2001兲.
7
High Dielectric Constant Materials: VLSI MOSFET Applications, edited
by H. R. Huff and D. C. Gilmer 共Springer, New York, 2004兲.
8
High-k Gate Dielectrics, edited by M. Houssa, 共Taylor & Francis, New
York, 2003兲.
9
W. Tsai, L.-A. Ragnarsson, L. Pantisano, P. J. Chen, B. Onsia, T. Schram,
E. Cartier, A. Kerber, E. Young, M. Caymax, S. De Gendt, and M. Heyns,
Tech. Dig. - Int. Electron Devices Meet. 2003, 311.
10
S. C. Song, Z. B. Zhang, M. M. Hussain, C. Huffman, J. Barnett, S. H.
Bae, H. J. Li, P. Majhi, C. S. Park, B. S. Ju, H. K. Park, C. Y. Kang, R.
Choi, P. Zeitzoff, H. H. Tseng, B. H. Lee, and R. Jammy, Tech. Dig. VLSI
Symp. 2006, 16.
11
S. C. Song, M. M. Hussain, B. S. Ju, C. Y. Kang, R. Choi, P. Zeitzoff, B.
H. Lee, and H. H. Tseng, 2006 ALD Conference, POSTECH, Korea 共unpublished兲.
12
K. Choi, H.-C. Wen, H. Alshareef, R. Harris, P. Lysaght, H. Luan, P.
Majhi, and B. H. Lee, Proceedings of the 35th European Solid-State Device Research Conference, 2005 共unpublished兲, p. 101.
13
M. Ohring, The Materials Science of Thin Films, and ed. 共Academic, New
York, 2001兲.
14
Chang Yong Kang, Hag-ju Cho, Rino Choi, Chang Seok Kang, Young Hee
Kim, Se Jong Rhee, Chang Hwan Choi, M. S. Akbar, and Jack C. Lee,
Appl. Phys. Lett. 82, 共2004兲.
15
S. H. N. Lim, D. G. McCulloch, M. M. M. Bilek, and D. R. McKenzie, J.
Appl. Phys. 93, 4283 共2003兲.
16
J. Huang, M. J. Kim, P. R. Chidambaram, R. B. Irwin, P. J. Jones, J. W.
Weijtmans, E. M. Koontz, Y. G. Wang, S. Tang, and R. Wise, Appl. Phys.
Lett. 89, 063114 共2006兲.
17
C. S. Smith, Phys. Rev. 94, 42 共1954兲.
18
D. Colman, R. T. Bate, and J. P. Mize, J. Appl. Phys. 39, 1923 共1968兲.
19
Y. Kanda, IEEE Trans. Electron Devices ED-29, 62 共1982兲.
20
P. R. Chidambaram, Chris Bowen, Srinivasan Chakravarthi, Charles
Machala, and Rick Wise, IEEE Trans. Electron Devices 53, 共2006兲.
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