Download W-band push–push monolithic frequency doubler in 1

Vol. 34, No. 9
Journal of Semiconductors
September 2013
W-band push–push monolithic frequency doubler in 1-m InP DHBT technology
Yao Hongfei(姚鸿飞), Wang Xiantai(王显泰), Wu Danyu(吴旦昱), Su Yongbo(苏永波),
Cao Yuxiong(曹玉雄), Ge Ji(葛霁), Ning Xiaoxi(宁晓曦), and Jin Zhi(金智)Ž
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract: A W-band frequency doubler MMIC is designed and fabricated using 1-m InP DHBT technology. Active balun is employed to transform the single-ended signal into differential output. Push–push configuration loaded
with harmonic resonant network is utilized to acquire the second harmonic frequency. A multi-stage differential
structure improves the conversion gain and suppresses the fundamental frequency. The MMIC occupies an area of
0.55 0.5 mm2 with 18 DHBTs integrated. Measurements show that the output power is above 5.8 dBm with the
suppression of fundamental frequency below –16 dBc and the conversion gain above 4.7 dB over 75–80 GHz.
Key words: frequency doubler; W-band; InP; DHBT; push–push
DOI: 10.1088/1674-4926/34/9/095006
EEACC: 1350F
2. Technology
1. Introduction
Frequency multiplier, and in particular frequency doubler, is widely used in millimeter-wave signal sources and
transceivers. It can be used to extend the frequency range of
microwave signal sources up to millimeter-wave band while
maintaining the performances of the microwave signal sources,
such as high stability and low phase noiseŒ1 . As frequency
increases from microwave to millimeter-wave, the influence
of the parasites in devices and passive structures become dramatically stronger. Therefore, the design of a W-band doubler presents remarkable challenges and specific methodology
should be applied.
A traditional distributed diode multiplier often occupies
large areas and requires high driving powerŒ2; 3 . Nowadays,
the progress of semiconductor technologies based on both specific materials and proper scaling of devices enables us to concentrate on the design using the current-source biased differential pairs in MMIC.
In this paper, the authors present the design, fabrication,
and characterization of a MMIC frequency doubler which theoretically operates from 75 to 110 GHz (due to the upperfrequency limit of the signal source, the doubler was characterized with the frequency only to 80 GHz). To implement
the frequency doubler, an active differential balun is chosen to
convert the single-ended input to differential output. The final
push–push stage performs frequency doubling and suppresses
the fundamental frequency. This differential-pair architecture
allows us to achieve good fundamental signal rejection and
fairly high output power. Multi-stage differential structure improves the conversion gain and diminishes the impact of the
active balun’s unbalance on the circuit performances.
The InP double heterojunction bipolar transistor (DHBT)
technology, used for doubler fabrication, is presented, and the
doubler design is given.
The transistor is grown on 3-inch InP wafer with an
epitaxial profile designed for high frequency application. S parameter measurements of the 1 15 m2 HBT demonstrates
an extrapolated fT (current gain cutoff frequency) of 170 GHz
and an extrapolated maximum oscillation frequency fmax of
253 GHz at the bias of IC D 15.4 mA and VCE D 1.5 VŒ4; 5 .
The large-signal model for InP/InGaAs DHBTs has been implemented as a symbolically defined device (SDD)Œ6 in the
Agilent ADS simulator.
The InP DHBT IC process includes MIM capacitor, thinfilm resistors (50 /), 2-levels of interconnect (M1, M2),
benzocyclobutene (BCB) passivating devices, and the wafer
planarization after device formation, as shown in Fig. 1. A
coplanar waveguide (CPW) is employed for its widely controllable impedance, ease of fabrication, and ability to maintain
signal integrity at very high frequencies within dense mixedsignal ICs.
3. Circuit design
The frequency doubler is based on a push–push cell which
outputs the second harmonic wave and suppresses the funda-
Fig. 1. Progress cross section of InP DHBTs technology.
* Project supported by the National Basic Research Program of China (No. 2010CB327502).
† Corresponding author. Email: [email protected]
Received 6 February 2013, revised manuscript received 26 March 2013
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© 2013 Chinese Institute of Electronics
J. Semicond. 2013, 34(9)
Yao Hongfei et al.
Fig. 2. Electrical scheme of frequency doubler.
mental power. Frequency doubling results in generating harmonics due to nonlinear characteristics of the transistors in the
push–push structureŒ7 and the former common-emitter stage
working under large-signal condition.
3.1. Circuit architecture
A detailed electrical scheme of the proposed doubler IC is
illustrated in Fig. 2.
The chip consists of five building blocks such as current mirror, active balun, differential amplifier, emitter follower and push–push core. The current sources are used to
bias the emitter followers and differential pairs. For differential structure, this presents high common-mode impedance and
improves the common-mode rejection ratio. The single-ended
input is first transformed into differential output by the active
balun and amplified by the following common-emitter stage.
Then, the amplified signals are buffered by the emitter follower
and used to drive the push–push frequency doubling core.
Fig. 3. Frequency doubling core based on push–push configuration.
3.2. Electrical design
Negative bias VEE is employed so that the collectors of
Q3–Q10 can connect to ground instead of DC bias lines. In
this way the influence of the bias network on the RF path is
minimized. Active differential balun instead of passive balun
is used by virtue of its compact size. The balun loses its amplitude and phase balance as frequency increases since the bases
of Q3, Q4 see different impedances when the signal source is
connectedŒ8 . Following the differential balun, the commonemitter differential amplifier and the emitter follower help to
diminish this mismatch. Also the emitter follower stages realize a level shifting and impedance matching to the next stage.
Transmission lines T1, T2 provide an impedance match for fundamental frequency and can also reflect back the harmonic frequencies coming from the doubling stages.
Frequency multiplication occurs in the push-push core, as
shown in Fig. 3. Q9 and Q10 are biased close to class-B (VBE
D 0.82 V), serving as the doubling core. The harmonic component of collector current is a function of conduction angle,
Fig. 4. Collector current modeled as a train of rectified cosine pulses.
which can be controlled by the input driving power and the base
bias pointŒ9 . The collector current can be modeled as a train of
rectified cosine pulses as shown in Fig. 4 and using the Fourier
series expansion, it can be represented asŒ10
095006-2
Ic .t/ D I0 C I1 cos .!1 t/ C I2 cos .2!t / C C In cos .n!t / C ;
(1)
4t0
;
T
(2)
I0 D Imax
In D 0; for odd n;
(3)
J. Semicond. 2013, 34(9)
Yao Hongfei et al.
Fig. 6. Total collector current of the two transistors Q9, Q10 ( Ic1 C
Ic2 /.
Fig. 5. The collector currents of Q9, Q10.
8t0
In D Imax
T
"
n t0
1
cos
T
2nt0
T
2 #
1
; for even n:
(4)
Imax is the maximum current, t0 is the length of the pulse,
and T is the period corresponding to the fundamental frequency. To maximize the amplitude of the second harmonic,
the conduction duty cycle for each transistor should be chosen such as t0 /T D 32%Œ9 . However, this would sacrifice the
valuable gain at W-band. As a compromise, Q9, Q10 were each
biased with t0 /T about 50%. Simulation of the push–push core
is shown in Fig. 2 and we show the collector currents IC1 , IC2
in Fig. 5. Q9 and Q10 turn on alternately and at the output node
the circuit delivers the even-order harmonic current or voltage,
as shown in Fig. 6. The fundamental leakage is due to the nonideal differential characteristics of the signals at the two bases
of Q9 Q10. This comes from the imbalance of the active balun.
Current mirrors act as stable current sources. The parallel
short-ended stub T3 with electrical length of 24ı @ 2f0 (f0
D 90 GHz) at the common collector node implement the simple impedance match for the doubling frequency. T3 can also
ground the fundamental frequency f0 thus improving the fundamental suppression.
All transistors have a size of 1 15 m2 , which is a good
compromise between fT and RF power. Q1, Q2 are biased at
5 mA and 7 mA respectively with R1 D 300 , R2 D 120 ,
R3 D 500  which stabilize the current source in case of environment variation. Q2 helps to reduce the base current influence and improve the output current precision. The individual
source for the differential structure is biased at about 14 mA to
make full use of the DHBT’s gain and power ability.
Due to circuit complexity and wide frequency band of
DHBT, circuit stability is an important design issue. When frequency increases toward W-band, the current source loses its
high-impedance characteristics and even presents some immittance. Also the parasitic inductances or capacitances of the devices and the interconnecting lines have an even greater impact
on the RF performance. Hence, wires connecting the current
sources to the differential pairs are modeled as transmission
lines in the schematic diagram. Also the stabilizing resistors
Rc1 , Rc2 are included to eliminate the oscillations. These are
shown in Fig. 7.
All the passive components, including capacitances, resistors and transmission lines, are simulated by momentum
electro–magnetic (EM) simulator, and then co-simulated with
the nonlinear HBT models in Agilent’s advanced design system (ADS) EDA environment to predict the time-domain and
frequency-domain output. Figure 8 shows the simulated frequency spectrum and wave form of the output signal when the
driving signal is of 40 GHz and 0 dBm.
3.3. Layout design
The whole circuit is divided into two parts: RF core and
DC bias. The RF core contains four pairs of HBTs Q3–Q10,
matching transmission lines T1–T3, and RF input and output
ports. The DC part is composed of current mirrors which are
used to bias the RF differential pairs.
The signal line is fed via the matched 50  CPW line. Similarly, the output signal is connected to the output pad with
a 50  CPW line. The layout is compacted to shorten highfrequency signal paths. The RF core is optimized for minimum
wire length and maximum symmetry. VEE feeds the RF transistors through the current mirror sources which isolates the RF
core from DC bias lines. The microphotograph is presented in
Fig. 9 with a size of 0.55 0.5 mm2 .
4. Test and measurements
The doubler was measured using on-wafer probing and
biasing at room temperature, as shown in Fig. 10. The input
signal was generated by a signal generator (E8257D) and delivered to the MMIC through coaxial cables. The output signal was delivered to the 18th harmonic mixer through a GGB
WR-10 waveguide and down-converted to Ka-band. The output signal was monitored by spectrum analyzer (E4447A) with
the frequency value displayed at W-band. The bias voltage VEE
for all stages is –3.6 V and the total current IEE is 113 mA. So
the power consumption is 407 mW.
Figure 11 gives the output spectrum when the input frequency is 80 GHz. From the displayed noise level and the resolution bandwidth (BW), it can be estimated that the phase noise
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J. Semicond. 2013, 34(9)
Yao Hongfei et al.
Fig. 7. The stabilizing resistors and modeled inter-connecting lines between current sources and differential pairs.
Fig. 8. Simulated (a) frequency spectrum and (b) wave form of the output signal.
Fig. 10. Test setup for on-wafer measurement of the W-band doubler.
which is very close to the theoretical value of the 18th multiplied E8257D signal:
146 .dBc=Hz/ C 20 lg 18 D
Fig. 9. Microphotograph of the MMIC frequency doubler (0.55 0.5
mm2 /.
is about
Noise .dBm/
Pout .dBm/
10 lg.BW.Hz//
120 dBc=Hz @ 1 MHz;
(5)
121 .dBc=Hz/:
(6)
From Eqs. (5) and (6), it is certain that the additive phase
noise of the frequency doubler is trivial and will not aggravate
the quality of the input signal.
The output spectrum was also inspected from 10 MHz to
42 GHz to determine the fundamental frequency suppression.
When the input power is 0 dBm @ 40 GHz, form Fig. 12, it can
be seen that the displayed power of the fundamental frequency
is 21:4 dBm. With the 9.5 dB coaxial cable loss taken into account, the actual power of the fundamental frequency is 10:9
dBm.
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J. Semicond. 2013, 34(9)
Reference
Technology
Output frequency (GHz)
Conversion gain (dB)
Pout (dBm)
Area (mm2 /
Published year
Yao Hongfei et al.
Table 1. Performance summary and comparison.
Ref. [11]
Ref. [1]
Ref. [12]
GaAs PHEMT
InP DHBT
SiGe HBT
76
75
60
16
1
1.3
4
10
1:6
2.63
2.24
0.22
2000
2005
2010
Ref. [3]
Module
92
14:7
5.2
—
2011
This work
InP DHBT
80*
4.7
5.8
0.28
2013
*The measured frequency is limited by the measurement system.
Fig. 11. Output spectrums of the frequency doubler when the input
frequency is 40 GHz.
Fig. 13. Measured output power, conversion gain and suppression of
f0 versus input power at 80 GHz.
Fig. 14. Measured output power and conversion gain over 75–80 GHz.
Fig. 12. Output spectrums of the frequency doubler over 10 MHz–42
GHz when the input frequency is 40 GHz.
Figure 13 shows the measured output power and conversion gain for various input power at 80 GHz. It can be seen that
at the vicinity of 7 dBm for input power, the output power
began increasing rapidly and the fundamental wave came into
compression. This indicates that the doubler was driven effectively and nonlinearity was strengthened. Hence the second
harmonic frequency was triggered out. When the input signal
reached 2 dBm, conversion gain exceeded 0 dB. With the
input power increased further, the output power saturated at
about 6 dBm, with the corresponding gain of 5 dB.
The output power and conversion gain are also measured
as a function of the input frequency, as shown in Fig. 14. As
can be seen, from 75 to 80 GHz, the conversion gain is more
than 4.7 dB and output power is higher than 5.8 dBm with gainripple less than 0.6 dBpp. The output spectrum with the input
frequency swept from 37.5 to 40 GHz was also inspected. The
final results are also shown in Fig. 14. As can be seen, suppression of the fundamental frequency is below –16 dBc, which is
close to the predicted –19 dBc in Fig. 8. The small-signal S22
is below –6 dB over the whole W band.
A comparison of several representative reported W-band
frequency doublers is presented in Table 1. Contributing to the
low-parasite design of the multi-stage differential structure and
high frequency performance of the InP DHBT, the proposed
doubler demonstrates the highest conversion gain.
095006-5
J. Semicond. 2013, 34(9)
Yao Hongfei et al.
5. Conclusion
A compact W-band frequency doubler using push–push
shaping circuit is proposed. Differential structure improves the
common-mode rejection ratio and suppresses fundamental frequency. The multi-stage driving circuit increases the conversion gain and delivers enough power to the push–push core.
Low-parasite layouts ensure the desirable RF performance.
Due to the frequency limit of the test system, measurements
were performed from 75 to 80 GHz and show the output power
is higher than 5.8 dBm with conversion gain above 4.7 dB.
[5]
[6]
[7]
[8]
[9]
References
[10]
[1] Puyal V, Konczykowska A, Nouet P. DC–100-GHz frequency
doublers in InP DHBT technology. IEEE Trans Microw Theory
Tech, 2005, 53(4): 1338
[2] An D W, Yu W H, Lv X. Design and analysis of a 2 mm-band
tripler based on quartz. J Infrared Millim Wave, 2011, 30(4): 377
[3] Yang T, Xiang X J, Wu W. Broad-band tripler of W-band. J Infrared Millim Wave, 2007, 26(3): 161
[4] Jin Z, Su Y B, Cheng W. High current multi-finger InGaAs/InP
[11]
[12]
095006-6
double heterojunction bipolar transistor with the maximum oscillation frequency 253 GHz. Chin Phys Lett, 2008, 25(8): 3075
Cheng W, Jin Z, Yu J Y. Design of InGaAsP composite collector
for InP DHBT. Chinese Journal of Semiconductors, 2007, 28(6):
131
Cao Y X, Jin Z, Ge J. A symbolically defined InP double heterojunction bipolar transistor large-signal model. Journal of Semiconductors, 2009, 30(12): 37
Kobayashi K W, OKI A K, Tran L T. A 108-GHz InP-HBT
monolithic push–push VCO with low phase noise and wide tuning bandwidth. IEEE J Solid-State Circuits, 1999, 34(9): 1225
Li Q, Wang Z G, Li W. Design of 20–44 GHz broadband doubler
MMIC. Journal of Semiconductors, 2010, 31(4): 045012
Maas S A. Nonlinear microwave and RF circuits. Norwood, MA:
Artech House, 2003
Hung J J, Hancock T M, Rebeiz G M. High-power highefficiency SiGe Ku- and Ka-band balanced frequency doublers.
IEEE Trans Microw Theory Tech, 2005, 53(2): 754
Campos-Roca Y, Verweyen L, Fernández-Barciela M. 38/76
GHz PHEMT MMIC balanced frequency doublers in coplanar
technology. IEEE Microw Wireless Compon Lett, 2000, 10(11):
484
Liu G, Ulusoy A C, Trasser A. 60–80 GHz frequency doubler
operating close to fmax . APMC, 2010: 770