Download Presentation

Dist / Guidelines page 1 Rev 3.3
Signal Distribution and Layout
Guidelines for Analog and Digital Circuits.
All labs
S.C. Petersen
I. Power Distribution
Ideal Case
Routing power to devices on a circuit board requires that we account for non-ideal behaviors of both the
power source and the wiring. Standard engineering practice routinely calls for judicious use of bypass
capacitors to stabilize voltage as well as observing routing rules for interconnecting the power lines. The
best way to understand the practical issues involved begins by looking at a simple design with an ideal
power source connected to circuit devices with ideal wiring, and then complicating it. This ideal example is
shown in Fig. 1 for a circuit having two digital devices needing power from a voltage source. Obviously,
these devices, integrated circuits or “chips” are powered by wiring their power pins, typically located on
opposite corners of each chip, to the source of power. Such wiring could be traces on a finished printed
circuit board, hand-wired prototype or “wire-wraps”, or even pre-wired connections available within a
digital plug-board.
Fig. 1. Ideal power supply wired to two integrated circuit “chips” U1 and U2.
Most digital logic devices require power from a constant voltage source. Thus, in Fig. 1 the power source
VS is constant and supplies total varying load current iT (t )  i1 (t )  i2 (t ) . Currents i1 (t ) and i2 (t ) feed chips
U1 and U2 respectively, modeled as time-varying resistances R1 (t ) and R2 (t ) .
Recall that an ideal voltage source will always supply whatever current is needed (positive, negative or
zero) to always maintain its terminal voltage constant. Since VS is ideal, iT (t )  i1 (t )  i2 (t ) will have no
effects whatever on otherwise constant VS . Similarly, wires w1 , w2 … are also ideal. This means they have
no resistance and exhibit no reactive effects (due to inductance or capacitance). It follows that
v12  v34  VS regardless of load variations due to i1 or i2 . For simplicity, unless explicitly stated, lower-case
quantities are assumed to be functions of time, while upper-case quantities are not.
Practical Case
The real situation of course is quite different. Non-ideal wires will have both resistance and inductance.
Both depend on wire size and geometry. Generally, the thinner the wire, the greater both quantities become
for a given length. Similarly, the voltage source will have some internal resistance, modeled by constant
Thevenin resistance RT . It will also have finite limitations on its DC and AC current capabilities. For
example, the 7805 three-terminal +5 [V] regulator is capable of sourcing up to about 1[A] of current. The
Dist / Guidelines page 2 Rev 3.3
ability of the 7805 to follow fast AC current demands is also limited, even though the DC value may lie
within its normal operating range between 0 and 1[A]. Noting these facts, we can draw a more accurate
practical circuit shown in Fig 2.
Fig. 2. Practical circuit from Fig. 1 accounting for internal resistance of the power source and finite
resistance and inductance of wiring.
Beginning at node x, we can sum voltage rises and drops around loop-1 by applying Kirchoff’s Voltage
Law (KVL) to obtain an expression for the supply voltage available to chip-1, v12 .
VS  vRT  vRW 1  vLW 1  v12  vRW 2  vLW 2  0
[1]
Solving for the voltage across the supply pins of chip-1, we obtain
v12  VS  vRT  (vRW 1  vLW 1 )  (vRW 2  vLW 2 )
[2]
It follows from basic circuit theory that voltage variations across wire-1 will be given by
vRW 1  iT RW 1 ,
vLW 1  LW 1
diT
,
dt
or the “DC” voltage drop due to wire-1’s resistance, and
[3a]
or the “AC” voltage drop due to wire-1’s inductance.
[3b]
The same holds for any of the four wire segments shown. Now, clearly, if the supply current iT is not
changing then the inductances in the first loop will have no effect since vLW 1  vLW 2  0 . For clarity let
i2  0 so iT  i1 , and the supply current depends only on whatever current chip-1 happens to be drawing due
to its equivalent load resistance R1 (t ) . Therefore,
i1 
v12
di
1
v12 .
and 1 
dt  dR1 (t ) 
R1 (t )
 dt 


For wires with relatively low currents, wire inductance will dominate the changes we see in v12 and we can
neglect the effect of wire resistances; i.e.
v12
 VS  vLW 1  vLW 2
di
di
di 

 VS   LW 1 1  LW 2 1  = VS   LW 1  LW 2  1 .
dt
dt
dt


[4]
The derivative terms in [4] represent the dynamic (AC) voltage drop due to current transients caused by fast
changing power demands from U1. This will occur during digital state changes (remember, CMOS logic
Dist / Guidelines page 3 Rev 3.3
only draws significant current during state changes). Similarly, additional transients can also be caused by
U2 when we add back in the effect of the second loop. For this case, when iT  i1  i2 , [4] becomes
v12  VS   LW 1  LW 2 
d (i1  i2 )
.
dt
[5]
Practical Solutions.
1. Alter the wiring scheme:
Equation [5] shows how U2 can potentially affect the behavior of U1 through induced power supply
variations. Although we are not accustomed to thinking this way, U1’s power pins actually become an input
from U2 through the power bus! The classic description of this phenomenon is called “power supply
coupling”, and can be minimized or eliminated by modifying how each chip receives its power for the main
supply. By removing i2 from flowing in wires 1 and 2 that also feed U1, we can decouple the two chips
and avoid U2 affecting U1. An obvious way is to just route wire-3 to the “+” power supply point directly
instead of connecting to U1’s “+” pin; similarly, wire-4 is routed directly back to the “-” power supply
point. Fig. 3. shows how this can be done by wiring chips U1 and U2 directly to nodes A (“+”) and B(“-”).
This scheme is known as the common-point or “star” distribution technique, and is the opposite of serial or
“daisy-chaining” where devices are connected sequentially in parallel. Assuming that VAB stays truly
constant, we see that v12 and v34 are completely independent of each other, since i1 only flows in wires 1 and
2, while i2 flows only in wires 3 and 4. Node B is usually called the common node and given the “ground”
symbol; accordingly currents flowing to this node are called ground return currents (wires 2 and 4).
Fig. 3. Low impedance common-point or “star” power distribution scheme to decouple chip interactions
through power wiring. Filter capacitor C guarantees that Z AB is kept low.
To ensure that VAB stays nice and constant, we usually make sure that common points (nodes) A and B are
physically close to the power source, and they present a very low source impedance to power wiring
connected between them by placing a large filter capacitor directly across nodes A and B (shunt
connection). This capacitor can respond to fast dynamic current demands the supply may not be otherwise
be able to respond to as well as filter voltage variations due to lead inductance between the common point
and the actual power source.
2. Add filter capacitors:
Even after decoupling chips by using a star distribution scheme, voltage variations or noise will still exist at
U1 and U2 due to associated wiring inductances. This noise can be further minimized or eliminated by
connecting filter capacitors directly across each chip’s power pins. We usually apply this kind of filter
using capacitor values determined by experience and rule-of-thumb; digital devices typically have 0.1  F .
Although we could develop precise analytic expressions describing how supply noise is reduced by filter
Dist / Guidelines page 4 Rev 3.3
capacitors, a description based on direct observation is much more intuitively understandable. To see how
this works, fig. 4 shows U1 drawn with its’ two non-ideal supply wires, w1 and w2 along with filter
capacitor C.
Fig. 4. Circuit showing how a filter capacitor works. It moderates and stabilizes a chip’s supply voltage by
acting as a transient current source to offset dynamic AC voltage drops in the power supply paths feeding the
positive and negative pins.
The fundamental idea behind filter capacitors is simple: When the voltage changes across a capacitor, it will
always produce a current that opposes that change in voltage by trying to keep it constant. This is known as
Lenz’s Law. Thus, when i1 changes, v12 will also change due to the drops across the two wires. There are
two cases of interest:
dv
If i1  then v12  and it follows that ic  C 12  0 (flows from C towards node 1), so ic acts as a transient
dt
source of current for i1 and will stabilize (or filter) v12 .
dv12
 0 , (flows into C away from node 1), so ic acts as a
dt
transient sink for current for i1 and will stabilize (or filter) v12 .
If i1  then v12  and it follows that ic  C
Dist / Guidelines page 5 Rev 3.3
II. Signal Distribution
The Ground Return Problem.
Another problem closely related to the power and ground buses discussed above, is based on the
observation that all signals (not just power) require closed-loop return paths back to their respective
sources. This means that any output from a powered chip must have a return current path back to that chip’s
actual ground pin, since the output voltage is generated between two nodes, the actual output pin and the
chip’s common node. Think about this for a moment and you should readily grasp how these returning
signal currents will necessarily always follow an electrical path offering the least impedance; this is not
necessarily the physically shortest path or the path with the least resistance. Usually this is via the zero-volt
common-node. Because this node is often simply denoted graphically using one of the many zero-volt
common-node reference symbols (like “earth” or “ground”), the actual physical path taken by return
currents can be difficult to see. Voltages will always develop across these non-zero impedance paths giving
rise to unwanted coupling between circuits due to dynamic signal voltage drops in the ground path only.
This condition, known as a ground-loop should be avoided where possible. Usually, fully isolating a chip’s
ground pin by starring it to the common-point ground at the power supply also has the unwanted
consequence of increasing signal return impedances between two chips. Fig. 5 shows the basic idea behind
this problem.
Fig. 5
Fig. 6 Analog example. How the does the bi-polar (dual-supply) op-amp’s output load current
return?
Dist / Guidelines page 6 Rev 3.3
General Power and Signal Distribution Guidelines
All Circuits:
1.
Always establish a low impedance “common” power distribution point that is well filtered. This is
shown in Fig. 3 with a polarized capacitor, like an aluminum electrolytic type. Size depends on
peak transient current demand, 1 to 100  F is common. Remember that larger gauge wiring may
be called for to wire the regulator circuitry to the common nodes to minimize inductance and keep
resistance low. On PCB design, insure both the power and ground busses are implemented with
wide low-impedance / resistance traces. Use of copper planes is recommended for this.
Digital Circuits:
2.
Digital CMOS devices need more filtering than TTL due to current transients during switching. A
single 100[nF] capacitor connected directly across a chip is usually sufficient.
3.
Combination layouts employing star and daisy-chains are common. Daisy-chaining several TTL
chips with one or more bypass capacitors is O.K. CMOS chips connected this way should each
have their own bypass capacitors.
4.
Keep signal return impedances low by employing ground “meshes” where necessary. These are
connections made directly between the ground pins of chips having their outputs driving inputs
between them.
Analog Circuits:
5.
Filtering for analog devices, like op-amps, should be bypassed with a minimum of 100 nF to
minimize inter-chip coupling through the positive supply bus. Additional filtering may be needed
to control device stability, noise and add immunity to low-frequency inter-chip coupling.
6.
Low noise circuits should employ the common-point star technique. A series of stages having high
loop gain should be laid out to avoid parasitic feedback via the power or ground busses.
Mixed Signal Circuits:
7.
Always separate power and ground distributions for analog and digital circuits. If fed from the
same supply rail, a low-impedance common-point scheme should be used. Many single chips
having analog and digital circuits internally, like cpu’s with A/D blocks, will usually have separate
power and ground pins. Internally, these are routed via a star configuration to control coupling.
Datasheets should be consulted and their recommendations carefully followed.
8.
When laying out a PCB, separate digital from analog circuits in separate blocks if possible.
Carefully consider paths of least impedance for analog ground currents and avoid having digital
currents share these same paths.
III. Layout Guidelines
1.
Place components to minimize inter-wiring / trace lengths.
2.
In digital systems, don’t use the star distribution technique for signal buses, like the address and data
buses.
3.
Take advantage of pin symmetry between chips when deciding where to place them.
Dist / Guidelines page 7 Rev 3.3
4.
When prototyping, leave enough space around the periphery of a circuit board to accommodate adding
components if necessary. This is typical when working with digital circuits.