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Physics 120 - Prof. David Kleinfeld - 2017 Notes on n-channel JFETs in the Active region 1. Review of basics 1. IG = 0 2. ID = IS In active region, device characteristics are defined by1: 3. VGS(off) ≤ VGS ≤ 0 4. VDS > VGS - VGS(off); recall that both VGS and VGS(off) are negative 5. ID is function of VGS, with ID = IDSS 2 VGS ( ) ⎡ V − VGS off ⎤ ⎦ off ⎣ GS ( ) 2 This implies ID = IDSS for VGS = 0. 6. ID is independent of VDS (ideal current source) 1 The turn-off gate-to-source voltage VGS(off) has a number of aliases, such as threshold voltage or pinch-off voltage, denoted VGS(off) = VT = VTH = VP = VPO = VP0 The active region is also called the "saturation region" or "pentode region", while the Ohmic region is also called the "linear region" or the "triode region". Sigh. For small changes in gate voltage, we can calculate the changes in source or drain current. The constant of proportionality is referred to as the transconductance, denoted gm, where gm = dIS 2I dID = = 2 DSS ⎡⎣ VGS − VGS off ⎤⎦ dVGS dVGS VGS off ( ) ( ) so that ΔIS = gm ΔVGS. We will see later that the transconductance plays a role analogous to β with bipolar junction transistors, but is not a constant, i.e., it depends of VDS! 2. Fixed current source Let's now consider the worlds simplest current source. Here VGS = 0, so the current is forced to be IDS = IDSS. This is maintained so long as the load line can maintain a value of VDS in the active region, i.e., VDS > - VGS(off). The load line is given by writing Kirchoff's rule for voltage drops and ignoring the transconductance 1/gm: 0 = -VDD +IDS RLoad + VDS to yield the load line IDS = VDD − VDS RLoad . This must intercept IDS = IDSS in the active region. Here, we slide along the (flat) line of ID = IDSS so long as VDS > - VGS(off). To find the maximum load resistance that keeps us in the active zone, we first rewrite the load line as an expression for VDS, i.e., VDS = VDD - IDSS RLoad Noting that VDS > - VGS(off), this implies -VGS(off) > VDD - IDSS RLoad or RLoad < ( ) VDD + VGS off IDSS This simple device suffers only from having a value of ID that is not adjustable! Yet for example, the (2N5485), has IDSS = 8 mA, enough to drive a typical LED with the effective resistance of RL ~ 100 Ω. 3. Improved current source A more sophisticated source uses a resistor between the source and ground to determine IDS. Here we have VG = 0 but VGS < 0, since the gate is grounded. The loop equation encompassing the gate and source satisfies (ignoring the transconductance term 1/gm): 0 = -VG + VGS + IDS RS or, with VG = 0, IDS = − VGS . RS We need to choose a value of Rs to fix ID. The second equation that relates IDS and VGS is the constitutive equation IDS = IDSS ⎡ V − VGS 2 VGS off ⎣ GS ( ) ⎛ VGS ⎞ off ⎤⎦ = IDSS ⎜ 1− ⎟ ⎝ VGS off ⎠ ( ) 2 2 ( ) We are free to pick a desired quiescent current, denoted IDSQ, with IDSQ < IDSS. Then the required value of RS is found by substituting VGS = -IDSQRS into the constitutive equation, i.e., 2 IDSQ = IDSS ( ) ⎛ −VGS off ⎛ IDQ ⎞ IDSQ RS ⎞ 1− 1+ . Thus R = S ⎜ ⎟ ⎜ ⎟ IDQ IDSS ⎠ VGS off ⎠ ⎝ ⎝ . ( ) The load line is given by writing Kirchoff's rule for voltage drops in the outer loop and ignoring the transconductance 1/gm: 0 = -VDD + IDSQ RLoad + VDS + IDSQ RS. We first consider the bounds of RLoad. The load-line is rearranged to VDS = VDD - IDSQ RLoad - IDSQ RS. The requirement that VDS > VGS - VGS(off) in the active region leads to VGS - VGS(off) < VDD - IDSQ RLoad - IDS RS. But VGS = - IDSQ RS from our analysis of the inner loop. Thus - VGS(off) < VDD - IDSQ RLoad or RLoad < ( ) VDD + VGS off IDSQ . We return to the load line equation, which is reordered as The load line for ID versus VDS is found by computing the voltage drops along the loop, i.e., IDS = VDD − VDS RLoad + RS . The value of VDSQ varies for IDSQ fixed as RLoad varies. The FET current sources are independent of fluctuations in the power supply voltage and largely independent of gm. As an example relevant to the laboratory exercise with a 2N5485, the choice IDSQ = 0.4 mA with IDSS = 8 mA and VGS(off) = - 3 V, we find RS = 5.8 kΩ. We use the closest value 5 % resistor at 5.6 kΩ. 4. Source follower The analysis is over two loops, one to define Rs and the other to define the load line. We consider the bottom loop to relate Vin and ID: 0 = - Vin +VGS + RS IS so ID = Vin − VGS RS . We consider the top loop to relate Vout and ID: 0 = - VDD +VDS + RS ID so ID = VDD − VDS V = Out RS RS and we get Vout = ID RS = Vin - VGS. We see that the output follows the input with the addition of a term VGS. Recall that VGS < 0 so the offset is positive. The value of VGS is found from the intersection of the load line ID = Vin − VGS RS and the constitutive equation ID = IDSS 2 ⎡ VGS − VGS off ⎤ ⎢ ⎥ 2 VGS off ⎢⎣ ⎥⎦ . ( ) ( ) The critical issue is that VGS is not constant but depends on Vin! This leads to a nonlinearity, yet is minimal for the choice Vin << VGS(off), as seen by solving for VGS, i.e., ⎡ ⎤ 2 ⎡ VGS off ⎤ ⎢ VGS off Vin − VGS off ⎥ VGS = VGS off ⎢1 − + ⎢ ⎥ + ⎥ 2 RSIDSS RSIDSS ⎢⎣ 2 RSIDSS ⎥⎦ ⎢ ⎥ ⎢⎣ ⎥⎦ ( ) ( ) ( ) ( ) We'll next see how to cancel the VGS term, but before then we consider the inclusion of a nonzero value of 1/gm as a resistance from the gate to the source. The loop equation is: 0 = - Vin +VGS + (1/gm) IS + RS IS so ID = Vin − VGS RS + 1 gm and Vout = ID RS = gmRS V − VGS 1+ gmRS in ( ) . The key is to maintain Rsgm >> 1 or Rs << 1/gm. This is critical, as gm is also a function of VGS. 4. Improved voltage follower An improved follower may be built in which the offset voltage VGS is minimized. We use a current source to define the current through Rs, as show below. Here we may write an expression for the equilibrium current (ignoring gm): 0 = - Vin + VGS (Q1) + IDQ R1 + Vout But we previously solved for the self limiting current source corresponding to the lower JFET, V Q or IDQ = − GS 2 . R2 ( ) Then 0 = - Vin + VGS (Q1) − ( ) R1 + Vout VGS Q2 R2 For R1 = R2 and matched JFETs, i.e., VGS (Q1) = VGS (Q2), the output voltage is exactly the input voltage and we have a perfect follower with a very large input impedance. "Matched" means that IDSS and VGS(off) are the same for each of the two FETs, so that VGS (Q1) = VGS (Q2) since the same current IDS flows through each FET. In fact, one can purchase FETs that are manufactured as pairs, on a common substrate, for this purpose.