Download Sustainable Electronics for Nano-Spacecraft in Deep Space

Sustainable Electronics for Nano-Spacecraft in Deep Space Missions
D.-I. Moon1, J.-Y. Park2, J.-W. Han1, G.-J. Jeon2, J.-Y. Kim2, J.-B. Moon2, M.-L. Seol1,
C. K. Kim2, H. C. Lee2, M. Meyyappan1, and Y.-K. Choi2
1
Center for Nanotechnology, NASA Ames Research Center, Moffett Field, CA, USA, email: [email protected]
2
School of Electrical Engineering, KAIST, Daejeon, Korea, email: [email protected]
Abstract— An on-the-fly self-healing device is experimentally
demonstrated for sustainability of space electronics. A high
temperature generated by Joule heating in a gate electrode
provides on-chip annealing of damages induced by ionizing
radiation, hot carrier, and tunneling stress. With the healing
process, a highly scaled silicon nanowire gate-all-around
device shows improved long-term reliability in logic, floating
body DRAM, and charge-trap Flash. A thermally isolated gate
structure is proposed to enhance the self-healing effect.
a promising candidate for the next generation space electronics
due to its inherent radiation hardness. Accordingly, the SiNW
GAA FET based floating body DRAM and SONOS Flash
memory are evaluated here in a monolithic integration approach.
tunneling stress and the respective recoveries are demonstrated
in a silicon nanowire (SiNW) gate-all-around (GAA) FET. As
shown in Fig. 3, dual contact pads of the gate allow current flow
creating heat for on-chip annealing. The effect of the proposed
concept is examined for practical applications such as logic
transistor, high-speed DRAM, and non-volatile Flash memory.
The novel structure is suggested to control the uniform heat
distribution.
In contrast with TID, SEE momentarily alters the logic and
memory states but these events can be resolved by reset and
correct operations. As shown in Fig. 10, when a high energy
particle is incident on the body, electron-hole pairs are
generated. As the number of gate electrodes increases, i.e., from
a single gate to a GAA, the leakage current from the radiation
is significantly suppressed at a fixed dimension due to the
enhanced electrostatic control from the gate. SEE effects on
device scaling are shown in Fig. 11. A narrowed DNW reduces
photocurrent (Iphoto) by smaller radiation sensitive volume, but
a shortened LG adversely increases Iphoto since it is amplified by
lateral bipolar (n-p-n) effects. At LG = 30 nm and DNW = 15 nm,
a bipolar action starts to be observed over the linear energy
transfer (LET) of 1 MeV-cm2/mg. As generated holes
As illustrated in Fig. 6, a small body volume along with the
surrounding gate structure of GAA offers inherent radiation
immunity compared with SOI-based FETs and FinFET [6], [7].
Fig. 7 shows electro-thermal simulation results performed using
the fabricated device parameters. The self-healing process can
be understood as the thermal annealing of the gate dielectric and
I. INTRODUCTION
isolation dielectric by the gate as nano-heater. The temperature
Nano-spacecraft consisting of a set of integrated circuits (IC) of the gate can surpass 900 °C within 10 ns, which is sufficient
has been introduced recently to solve challenges such as to remove the interface traps and trapped charges in the gate
propulsion cost and launch weight [1]. As shown in Fig. 1, the dielectric [8]. The evidence of such high temperature in a
conventional spaceship takes 18,000 years from Earth to a polysilicon line was previously reported in elsewhere [9]. Thus,
nearest star, i.e. Alpha Centauri, but the ChipSat dramatically temperature-controlled Joule heating system can be used to
reduces the travel time to 20 years due to its light weight and recover radiation, stress and aging induced performance
great energy efficiency [2]. However, as summarized in Fig. 2,
degradations for high reliability applications.
high risks of radiation induced damages and mission period
over 20 years (longer than usual lifetime of IC) are considered
III. LOGIC TRANSISTOR
as technology barriers. Three passive strategies to avoid
Major failures of semiconductor electronics in space
radiation impacts are used: limit flight path minimizing
environment
are due to TID and SEE. Unexpected high energy
radiation exposure, use of shielding, and radiation aware circuit
particles
from
the cosmic-ray, solar flare and trapped particles
design. The specially planned flight trajectory leads to delays
should
be
considered
for long term missions because these
and constraint of the exploration area. Also, it is intrinsically
effects
can
cause
soft
error
or even catastrophic failure [10].
impossible to avoid unexpected radiation exposure. The
Experimental
results
of
TID
are summarized in Fig. 8. The
shielding metal adds significant weight, which nullifies the
fundamental advantage of the nano-spacecraft. The radiation threshold voltage (VT) and subthreshold swing (SS) become
aware design often limits the performance benefit of the state- worse by shortened LG and increased radiation dose due to the
of-the-art technology as it usually relaxes the worst-case accumulated charges and traps from the gate oxide and spacers.
The self-healing results for TID are shown in Fig. 9. Positive
tolerance margin.
fixed charges around the device are successfully removed by
In this respect, an on-chip self-healing process has been
the Joule heating. The drive current is even further enhanced
discussed to defend against the susceptibility on-the-fly [3]-[5].
In the present work, aging and failure mechanisms such as total from the pre-stressed device, which would be from the removal
ionizing dose (TID), single event effect (SEE), hot carrier and of pre-existing interface states.
II.
SELF-HEALING PROCESS
The process flow and fabricated devices are shown in Figs.
4 and 5. Dual gate contacts were designed. A single voltage was
applied to both contacts for normal operation while a current
was injected to generate Joule heat during annealing. Among
various device structures, the GAA FET has been considered as
accumulate, additional electrons from the source to drain flow
at the off-state [11]. Accordingly, digital states can be
accidently flipped due to parasitic bipolar action, namely single
transistor latch (STL). In order to evaluate STL, the ionizing
radiation was emulated by impact ionization to trigger the
parasitic bipolar transistor as impact ionization and radiation
ionization result in intrinsically identical outcome, electronhole pair generation. As shown in Fig. 12, the drain current (ID)
increases abruptly by impact ionization. In the STL process,
undesired interface traps are generated and negative charges are
injected into the gate dielectric. Accordingly, ID-VG
characteristics such as drive current and the gate induced drain
leakage become worse as the stress increases. After subsequent
annealing of interface traps, the device is clearly recovered. To
support the physical recovery of the interface states, noise
measurements were carried out in fresh, stress, and recovery
states. As shown in Fig. 13, the normalized power spectrum
density (PSD) shows that the interface states were recovered to
a fresh state by the self-healing process.
IV. MEMORY
The lifetime of memories is mainly limited by the
operational stress on the gate dielectric. The floating body
DRAM is written by majority carrier generation through impact
ionization or band-to-band tunneling. But, both charge
generation processes cause gate oxide degradation. Therefore,
the cycling endurance becomes a critical issue. A timing
diagram and bias conditions of the floating body DRAM
operation [12] are displayed in Fig. 14. The writing process is
performed with a pulse width of 5 ns. The binary memory states
are clearly distinguished. The sensing current (ΔIS) between a
state ‘1’ and ‘0’ is 14 μA. The results of cycling operations are
summarized in Fig. 15(a). The memory begins to degrade after
1011 cycles and fails after 1012 cycles. The failing mechanism is
associated with the gate oxide breakdown. To extend the
endurance limit, the self-healing process is inserted at every
1011 cycles. Thus, the reliable operations are experimentally
verified for more than 1012 cycles. Moreover, the hold retention
time is also recovered by the self-healing process, as shown in
Fig. 15(b). The generated interface states increase the band-toband current, reducing the state ‘0’ retention time due to
unwanted hole leakages.
Flash memory uses Fowler-Nordheim (FN) tunneling for a
program and erase (P/E) operations. The tunnel oxide is
inevitably susceptible against FN mechanism. As shown in Fig.
16, ID-VG characteristics of the SONOS Flash memory are
significantly degraded due to repeated P/E operations. However,
the device performance can be maintained by application of the
self-healing process. The self-healing pulse is embedded within
the erase operation. As summarized in Fig. 17(a), no
degradation in terms of VT, SS, and ION is visible after 10K P/E
operations. Furthermore, the capability to retain charges is also
maintained after 1K P/E stress due to the damage curing of the
tunneling oxide, as shown in Fig. 17(b). Referring to previous
work [4], ultra-high endurance Flash memory (> 100M cycles)
with excellent retention can be realized for long term stable
space electronics.
One challenging issue with regard to the self-healing
process is how temperature uniformity along a word-line (WL)
for the array can be controlled. The simulation data indicates
that the temperature distribution is not uniform along WL as
shown in Fig. 18. Therefore, the memory cell at both edges of
the WL is not equally cured compared to that at the center. The
uniform temperature distribution can be attained by improved
WL design. When both edges of the WL (heat source) are
electrically tied but thermally decoupled from a contact pad
(heat sink), the temperature loss at WL edge can be
compensated. Hence, a thermal island at the edge of WL is
proposed and verified as shown in Fig. 19. A sacrificial pattern
reserved for an airgap as the thermal island is prepared. After
the WL patterning, the airgap can be made underneath the edge
of the WL by removing the sacrificial pattern. As the length of
the airgap (Lair) increases, the difference in the temperature
between the center and edge of the WL is sharply decreased.
Therefore, the uniform temperature distribution is obtained
regardless of length of WL if Lair becomes 215 nm. The flow
chart of the self-healing process is shown in Fig. 20. As all parts
of the logic and memories are not always used at the same time,
the region in idle state goes to the recovery process when
necessary. During the self-healing process, the data under selfhealing is copied to and subsequently recovered from the
redundancy because the logic and memories states are
initialized by the thermal process.
V.
CONCLUSIONS
Highly reliable logic transistor, high-speed floating body
DRAM and non-volatile charge trap Flash memory were
demonstrated in silicon nanowire gate-all-around FETs. The
high temperature arising from Joule heating in the gate was
applied for on-the-fly annealing. The on-chip annealing
capability recovers interface states and bulk traps in the gate
dielectric induced by hot-carrier injection and ionizing radiation.
Therefore, the lifetime of devices can be extended, which opens
an opportunity for nano-spacecraft sustainable for more than 20
years of deep space exploration.
ACKNOWLEDGMENT
REFERENCES
[1] N. Jones, Nature, vol. 534, p. 15, 2016.
[2] D. Clery, Science, May 23, 2016 [Online]. Available: DOI: 10.1126/
science.aag0558
[3] A. Kelleher and W. Lane, IEEE Trans. Nucl. Sci., vol. 43, p. 997, 1996.
[4] H.-T. Lue et al., IEDM Tech Dig., p. 199, 2012.
[5] G. Pobegen et al., IEEE Electron Device Lett., vol. 34, p. 939, 2013.
[6] E. S. Comfort et al., IEEE Trans. Nucl. Sci., vol. 60, p. 4483, 2013.
[7] P. Roche et al., IEDM Tech Dig., p. 766, 2013.
[8] J. C. King and C. Hu, IEEE Electron Device Lett., vol. 15, p. 475, 1994.
[9] J.-Y. Park et al., Scientific Reports, vol. 6, p. 19314, 2016.
[10] A. Paccagnella et al., IEDM Tech Dig., p. 473, 2004.
[11] J. R. Schwank et al., IEEE Trans. Nucl. Sci., vol. 522, p. 522, 2003.
[12] S. Okhonin et al., IEDM Tech Dig., p. 925, 2007.
Lifetime of COTS chips ~ 10 years
 Deep space mission > 20 years
Radiation hardening strategy
Flight path Radiation
Chip
control
shielding
design
Voyager
O
O
O
ChipSat
X
X
O
Fig. 2. International standard for a lifetime of terrestrial commercial
off-the-shelf (COTS) chips is set to target for 10 years, whereas many
deep space missions require longer than that period. Furthermore, the
intermittent radiation exposure alters the designed function of the chip,
leading irrecoverable aging and even catastrophic failure.
Fig. 1. A nano-spacecraft such as ChipSat, which consists of solar cells and
functional blocks in a printed circuit board, would face a high risk of damage
from radiation and aging issues on a flight into deep space. Especially, most
of functional blocks such as microcontroller, memories, sensors, and
communication system are semiconductor-based chips.
Sustainable space
Radiation
VG
p
LG
S
Gate
S
n+
DNW
D
S
D S
D
Self-healing process
+V
Damaged
Joule-heating
D
Leakage
Current
Thermal annealing
Damage
curing
Gate
Gate-all-around FET
Gate
S
S
Fresh state
TID
Gate
Gate
SEE
D
Aging
Hot carrier
Gate
VD
Tunneling
D
“HOT” Gate
S
-V
Spacer
D
Recovery
STI
Fig. 3. Schematics to show the self-healing effect in the lifetime limited factors of space applications: radiation, hot carrier, and tunneling stress.
High energy particles generate fixed charges and interface traps. Also, device and memory operational point of view, hot carrier and tunneling
stress cause reliability issues. These aging mechanisms lead failure of semiconductor-based electronics. By applying voltage to the gate electrode,
the gate dielectric and isolation dielectric are annealed by the high temperature generated by Joule heat, and the damaged device can be recovered
to a fresh state. With the iterative self-healing process, the lifetime of space electronics can be extended to satisfy long term deep space mission.
(a)
(b)
Contact
50 nm
x-x’
Bosch process
Si bulk wafer
Bulk doping
S
SiNW patterning
G
Poly-Si
D
Gate
SiNW
y
C4F8
Oxide
SiNW
FinFET
GAA
Fig. 6. Impact of radiation-induced
charges on the different device
structures. As the gate screens the
accumulation charges, GAA has
inherent structural advantages.
LG
Nitride (6 nm)
50 nm
Bulk-Si
20 nm
for the self-healing process. (b) Cross-sectional TEM image after Bosch process. (c) TEM image along the
x-x’ direction. The gate is entirely surrounding the SiNW channel. The thickness of the poly-Si gate is 300
nm. Close-up view of fabricated devices for (d)-(e) the logic transistor, floating body DRAM, and (f)-(g)
charge trap Flash memory. The diameter of SiNW (DNW) is 15 nm and the length of the gate (LG) is 30 nm.
(a)
(b)
1600
Measurement
Simulation
SiNW
1400
0.9
+V Top view
Gate
0.6
0.3
0.0
Healing
0 1 2 3 4 5 6 7
Voltage, V (V)
600
400
200
0
Gate
SiNW
850 °C
1000
800
Cross-section
950 °C
1200
Heat sink
(22 °C)
o
Planar
(g)
O/N/O
Oxide (8 nm)
Temperature ( C)
STI
(f)
SF6
Passivation
polymer
10 nm
Oxide (5 nm)
PR
Breakdown
+++-+
-+
-+
+++-+
-+
-+
+++-+
-+
-+
DNW
10 nm
Oxide (3 nm)
Contact
Bulk-Si
`
Fig. 5. (a) In-line CD SEM image before the gate sidewall spacer formation. Dual gate pads were formed
Current, I (mA)
Gate
200 nm
20 nm
Gate
y-y’
LG
STI oxide
Bosch process
x’
y’
Fig. 4. Process flow of the GAA
SiNW FET. For the suspended
SiNW on a bulk substrate, the
deep reactive ion etching, i.e.,
Bosh process, was performed.
Poly-Si
GAA structure
(e)
Gate
Oxide
SiNW Channel
Bulk-Si
x
Gate patterning
S/D doping
(d)
x-x’
Separation
D
S
STI formation
Gate stack
SiNW
(c)
Heat sink
(22 °C)
Thermal conductivity
Poly-Si: 31.2 W/m·K
Bulk Si: 149 W/m·K
SiO2: 1.04 (20 °C) ~
2.51 (1600 °C) W/m·K
STI oxide
250 °C
-V
Temp. (oC)
SiNW
900
700
500
300
100
Bulk-Si (heat sink)
Gate
Oxide
10 ns
Heat sink
-10
10
-9
10
Time (sec)
-8
10
Fig. 7. (a) I-V characteristic of the gate electrode. As the current is increased, the temperature of the gate
electrode increases rapidly by Joule heating. But, the current is abruptly decreased at a high voltage due to the
mechanical deformation of the poly-Si gate resulting from the high temperature. (b) Temperature contour and
transient response simulations. Each end of gate contact pads and a bulk Si substrate were set to a heat sink.
The heat is localized to the center of the gate, and it is effectively transferred to the isolation and gate dielectric.
-40
-7
ID (A)
Fig. 8. (a) VT and SS degradation trend according to LG. TID effects
are severe in the short LG. (b) VT and SS versus total dose. VT at low
dose is shifted to negative direction due to the positive oxide charges,
but it turns to opposite direction due to the generated interface traps.
Accordingly, SS is continually worsened as total dose increases.
(a)10
SiNW
High
D
e- current density
Gate
Gate
1.2
0.8
LET = 30 MeV-cm2/mg
LG = 1μm, DNW = 15 nm
1
Write ‘1’
Read
‘0’
10
-8
10
-9
0.5 V
-1.5 V
-2 V
2.5 V
0V
-2.5 V
Write ‘1’
0
10
-2
10
-4
Off-state
DNW = 15 nm
10 1000
100
LG (nm)
Photocurrent
LET = 100
(MeV-cm2/mg)
Peak intensity
at 10 ps
LET = 0.1
Bipolar effect
LG = 30nm
DNW = 15 nm
10
Transient time (ps)
Read ‘0’
∆IS
Write ‘0’
0.4
0.6
Fig. 11. (a) SEE trend by scaling
down of SiNW GAA FETs. (b)
Transient simulation with SEE.
Parasitic bipolar effect is observed
in the highly scaled SiNW GAA.
5
1 2 3 4 5 6 7 8 9 10
Cycles (x10 )
5
State '1'
Fresh (1 cycle)
Recovery (1012 cycles)
Stress (1011 cycles) State '0'
0 -4
10
10
-3
10
-2
10
-1
Oxide
WL (Heat source)
Pad
Pad
Oxide
Bulk-Si
Edge
200 °C
300 °C
100 °C
22 °C
500 °C
400 °C
Pad
Center SiNW
Fig. 18. The difference in the
temperature between the center
and the edge position degrades
the effect of the self-healing
process in the memory array.
Thermally non-uniform
Thermally
isolated WL
Thermal isolation
Lair
900 °C
Cross-section
Pad
Heat sink
0 μm
1.15
LG = 30 nm
DNW = 15 nm
-5
LG = 30 nm
DNW = 15 nm
Fresh
Stress
Recovery
-10
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
Thermally uniform
-6
10
-7
10
Fresh
Stress
Recovery
-8
10
-7
0.5
(a) 5
4
3
2
1
0
-1
Without the self-healing
With the self-healing
0
1
4
3
2
1
0
-1
Healing temperature
900
Lair = 0 nm
Lair = 100 nm
Lair = 215 nm
Lair = 250 nm
800
700
600
500
Non-uniform temperature
2 μm (Conventional WL)
400
300
0.23 μm (Proposed design)
0
1
2
Position in WL, x (m)
Fig. 19. Comparison of the conventional and the proposed design for a
long WL. The temperature within the WL is gradually decreased from
the center to the edge position in the conventional design. But, the
proposed WL design shows a highly uniform temperature distribution
with Lair of 0.215 μm due to the thermal isolation effect.
2
3
4
10
10
10
P/E endurance (#)
(b) 5
1000
10
Fig. 13. Results of the noise
measurement. The normalized PSD
value, which means the amount of
the oxide traps, is changed by
stress and the self-healing process.
10
-2 -1 0 1 2 3 4 5 6
VG (V)
-6
10
Drain current, ID (A)
Without the self-healing
With the self-healing
P/E: 14 V, 100 s/-14 V, 100 ms
200
x
1.20
Fresh Radiation Recovery
Fig. 16. The non-volatile memory
characteristics after 10K P/E
operations. The gate pulse of ±2.2
V with 100 ms is applied with the
erase for the self-healing process.
Fig. 15. (a) Endurance comparison
with/without the self-healing process.
(b) Hold Retention time is seriously
degraded after cycling; however, it
recovers to a fresh state by healing.
Conventional
VG = 1 V
VD = 0.05 V
1.25
10
Retention time (sec)
Pad
Thermal distribution along the WL (1 μm)
10
0.4
Fig. 12. STL curves of fresh,
stress, and recovery states. A selfhealing bias of 4.5 V (±2.25 V
for each gate contact) is applied
across the gate for 100 ms.
Without the self-healing
(b) 15
0.0 0.2
VG (V)
0.0
VG (V)
With the self-healing
10
Fresh
Radiation
Recovery
-2.0 -1.5 -1.0 -0.5 0.0
(a) 15
0.8
Time (sec)
Fig. 14. The high-speed memory
characteristics with a writing
time of 5 ns. ΔIS between state ‘1’
and state ‘0’ is 14 μA after a
hold time of 100 ms.
10
100
11
Read ‘1’
0.2
DNW (nm)
1
Read
Hold
VD
(BL)
-IS (A)
-7
100
2
3
4
Number of gate (#)
Hold
25
20
15
10
5
0
0.0
10
LG = 1 m
10-6
Fig. 10. Heavy ion strike
simulations with various device
structures. The radiation induced
photocurrent is suppressed as the
number of gates increases.
VG
(WL)
10
-6
0
IS (A)
0.0
10
ID (a.u.)
35 %
0.4
5
-5
LET = 30 MeV-cm2/mg
Healing:
4 V, 100 ms
Fig. 9. (a) Transfer characteristics of the fresh, radiation damaged, and
recovered states. For the self-healing process, ±2 V is applied to each
gate contact for 200 ms. (b) Summary of TID and recovery effect.
Damaged VT is recovered to fresh state by the self-healing. But, ID is
further enhanced after the recovery due to the thermal annealing effects.
-4
(b)10
Gate
10-12
-0.4 -0.2
10
-IS (A)
Iphoto (a.u.)
Low
Gate
Gate
0.5
10-11
ID (A)
Gate
Iphoto (a.u.)
Ion strike
S
Total dose:
5 Mrad
1.30
10-10
-1
90
1.0
-0.20
2
50
70
LG (nm)
Heal
-0.25
-80
-100
-120
-140
PSD, SID/ID (Hz )
30
1.5
VT (V)
0
(b) -60
VT (V)
2
10 LG = 30 nm
8
6
4
2
0
0
2
4
6
8 10
Total dose (Mrad)
Rad
10-9
10-9
ID (A)
4
10
10-8
-80
o
Total dose = 5 Mrad
6
-60
-8
ID (A)
-20
Temperature ( C)
-40
10
2.0
VD = 0.05 V
VT (mV)
-60
ID (A)
10-6
(a)
SS (mV/dec) VT (mV)
(b) -20
SS (mV/dec) VT (mV)
(a) -80
10
20 years
Post cycling (1K)
10 years
Without the self-healing
With the self-healing
0
1
2
3
4
5
6
7
8
10 10 10 10 10 10 10 10 10
Retention time (sec)
Fig. 17. (a) Endurance test. VT
increases by P/E cycling due to
interface traps, but it removed by
thermal annealing. (b) Post 1K
cycling retention characteristics.
Idle Run
Run
R
R: redundancy
Periodic
checking
No
Aging
monitor
No Yes
Data recovery
Idle Run
Run
R
Idle Run
Run Copy
Data copy
Temperature
sensor
Self-healing
process
Heal Run
Run Copy
Fig. 20. Operational concept for the
self-healing process. A sustainable
electronic system is composed of
the built-in gate heater, aging
monitor, and temperature sensor.