Download SPICE Device Model SUP/SUB75N08-10 N-Channel

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SPICE Device Model SUP/SUB75N08-10
N-Channel Enhancement-Mode Transistors
Characteristics
• N-channel Vertical DMOS
• Macro-Model (Subcircuit)
• Level 3 MOS
• Applicable for Both Linear and Switch Mode
• Applicable Over a -55 to 125°C Temperature Range
• Models Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
Description
capacitance network is used to model gate charge
characteristics while avoiding convergence problems of
switched Cgd model. Model parameter values are
optimized to provide a best fit to measured electrical
data and are not intended as an exact physical
description of a device.
The attached SPICE Model describes typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model was extracted and optimized over a
25°C to 125°C temperature range under pulse
conditions for 0 to 10 volt gate drives. Saturated output
impedance model accuracy has been maximized for gate
biases near threshold. A novel gate-to-drain feedback
D
Model Subcircuit
4
R1
M2
M1
G
CGS
3
DBD
1
2
S
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to
the appropriate data sheet of the same number for guaranteed specification limits.
Siliconix
9/14/98
Document: 70936
1
SPICE Device Model SUP/SUB75N08-10
Model Evaluation
N-Channel Device (TJ=25°C Unless Otherwise Noted)
Parameter
Static
Gate Threshold Voltage
On-State Drain Currentb
Drain-Source On-State Resistanceb
Symbol
Test Conditions
Typ
Unit
VGS(th)
ID(on)
rDS(on)
VDS = VGS, ID = 250µA
VDS = 5V, VGS = 10V
VGS = 10V, ID = 30A
VGS = 10V, ID = 30A,
TJ = 125°C
3.12
416
0.011
0.018
V
A
VGS = 10V, ID = 30A,
TJ = 175°C
VDS = 15V, ID = 30A
IF = 75A, VGS = 0V
0.022
Forward Transconductanceb
Forward Voltageb
Dynamica
Input Capacitance
Output Capacitance
gfs
VSD
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Charge c
Crss
Qg
Qgs
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
Turn-Off Delay Timec
Qgd
td(on)
tr
td(off)
Fall Timec
Reverse Recovery Time
Ciss
Coss
tf
trr
VGS = 0V, VDS = 25V,
f = 1MHz
VDS = 30V, VGS = 10V,
ID = 75A
VDD = 30V, RL = 0.47Ω
ID ≅ 75A, VGEN = 10V,
RG = 2.5Ω
IF = 75A, di/dt =100A/µs
Ω
60
0.92
S
V
4890
963
pF
221
83
31
nC
24
57
31
62
ns
20
100
ns
Notes:
a) Guaranteed by design, not subject to production testing
b) Pulse test: pulse width ≤ 300 µsec, duty cycle ≤ 2%
c) Independent of operating temperature
Siliconix
9/14/98
Document: 70936
2
SPICE Device Model SUP/SUB75N08-10
Comparison of Model with Measured Data
(TJ=25°C Unless Otherwise Noted)
250
200
150C
200
Vgs=7V
ID - Drain Current (A)
150
Vgs=6V
100
50
-55C
150
100
50
25C
Vgs=5V
0
0
0
2
4
6
8
VDS - Drain-to-Source Voltage (V)
0.08
6
0.06
4
0.04
0.02
rDS(on)
0
2
4
6
8
rDS(on) - On-Resistance (Ohm)
Sqrt (IDsat) (A)
Sqrt( IDsat)
8
0
4
8
10
0.016
Vgs = 10V
0.012
Vgs = 20V
0.008
0.004
0
10
0
0
20
VGS - Gate-to-Source Voltage (V)
40
60
80
100
ID - Drain Current (A)
7000
30
20
Vds
6000
Vgs
Ciss
5000
4000
Vds (V)
Capacitance (pF)
6
0.02
0.1
2
2
VGS - Gate-to-Source (V)
rDS(on) - On-Resistance (Ohm)
10
0
10
3000
24
16
18
12
12
8
6
4
2000
Coss
1000
Crss
0
0
10
20
30
40
50
VDS - Drain-to-Source Voltage ( V )
60
0
0
25
50
75
100
125
150
Qg (nC)
Siliconix
9/14/98
Document: 70936
3
0
175
Vgs (V)
ID - Drain Current (A)
Vgs= 10, 9, 8V
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Document Number: 91000
Revision: 18-Jul-08
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