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MPSoC Clock and Power
Olivier Franza, Intel
• Increased uncertainty with process scaling
– Process, voltage, temperature variations, noise, coupling
• Affects design margin over design, power &
performance loss
– Increased power constraints
– Increasing leakage, power (density, delivery) limitations
• More transistors mean:
– Larger clock distribution networks
– Higher capacitance (more load and parasitics)
• With each new technology:
– Gate delay decreases ~25%
– Wire delay increases ~100%
– Cross-chip communication increases
– Clock needs multiple cycles to cover die
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테크놀로지 스케일링에 따른 저항성분은
증가하고 정전용량은 줄어들지 않는다.
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온칩 버스에서 소모하는 에너지는 전체
에너지의 1/4
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Interconnect Delays & Density
Hannu Tenhunen & Dr. Li-Rong Zheng, Royal Institute of Technology
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Multiple Clocks due to Interconnect limitation
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At reduced performance,
larger resource size
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Multiple clock domains
• Low skew and jitter ALWAYS a must
• Clock modeling requires more accuracy
• Within-die variations, inductance, crosstalk,
electromigration, self-heat, …
• Floor plan modularity
• Think adding/removing cores seamlessly!
• Hierarchical clock partitioning
• Reduce global clock and possibly relax its
requirements
• Generate “locally”-used clock “locally”
• Implement clock domain deskewing techniques
• Bound clock problem into simple, reliable, efficient
domains
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DEC/Compaq Alpha
more complex core to improve performance, more
complex clocks (?), Source: DEC/Compaq – Gronoski & al., JSSC 1998 – Xanthopoulos &
al., ISSCC 2001 – Barroso & al., ISCA 2000
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Clock and Power Convergence
Intel® Itanium® Montecito
• Each core split into 3 clock
domains on variable power
supply
• Each domain controlled by
Digital Frequency Divider (DFD)
generating low-skew variablefrequency clocks; fed by central
PLL and aligned through phase
detectors
• Regional Voltage Detector
(RVD): supply voltage monitor
• Second level clock buffer (SLCB):
digitally controlled delay buffer
for active deskewing
• Regional Active Deskew (RAD):
phase comparators monitoring
and adjusting delay difference
between SLCBs
• Clock Vernier Device (CVD):
digitally controlled delay buffer
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On-Chip Interconnects:
Circuits and Signaling,
Wayne Burleson
• Using Vdd programmability
• High Vdd to devices on critical path
• Low Vdd to devices on non-critical
paths
• VddOff for inactive paths
A – Baseline Fabric
B – Fabric with Vdd Configurable
Interconnect
This work builds on a similar idea for FPGAs described in:
Fei Li, Yan Lin and Lei He. Vdd Programmability to Reduce FPGA Interconnect Power, IEEE/ACM
International
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2006년
Conference on Computer-Aided Design, Nov. 2004
가을
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From Spaghetti wires to Noc
Marcello Coppola, STMicroelectronics
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Benchmarks,
EE Times,7/2005
• Xpipes, Bologna and Stanford : compared w/
Amba AHB multilayer bus, 21% faster, but
worse latency
• When, Univ. of Kaiserslautern: LPDC decoder:
500Mhz vs 64 Mhz (fixed bus), but 30W vs.
700mW, twice the die size.
• Arteris: better die size, comparable power
consumption, 740Mhz (250Mhz)
• SonicsMX: power-efficient mobile-handset w/
power management
• STNoC, Spidergon: topology w/ degree 2-3
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NoC Applications
http://www.eit.uni-kl.de/wehn
• Turbo-Decoder UMTS compliant, 100Mbit: large
flexibilty w/ 14 parallel units, area = 16.84 mm2
(14mm2 PUs, 2.8mm2 NoC)
• LDPC Decoding,
T. Theocharides, G. Link, N. Chip, T.
Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, Int.
Conference on VLSI Design 2005
– 1024 Bit block size, 1.2Gb/s, R=0.75
– NoC: 5x5 2D mesh, dimension-order routing,
large flexibility
– 160nm CMOS Technology, 1.8V, 500 MHz, 110
mm2, ~30 Watt
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Reliable design,
G. De Micheli
1. Manufacturing imperfections: More likely to
happen as lithography scales down
2. Approximations during design: Uncertainty
about details of design
3. Aging: Oxide breakdown,electromigration
4. Environment-induced Soft-errors (Data
corruption due external radiation exposure),
electro-magnetic interference
5. Operating-mode induced: Extremely-low
voltage supply
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Dealing with variability
• Most variability problems that induce timing
errors
1.
2.
3.
4.
Power supply variation
Wire length estimation
Crosstalk
Soft errors
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Adaptive low-power
transmission scheme
Frédéric Worm, Patrick Thiran, Giovanni De Micheli, and Paolo Ienne.
Self-calibrating Networks-on-Chip.In Proceedings of the IEEE International
Symposium on Circuits and Systems, Kobe, Japan, May 2005.
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Reduced Energy Consumption
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Low-Power Network-on-Chip
for High-Performance SoC Design
Lee, K.; Lee, S.-J.; Yoo, H.-J.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 14, Issue 2, Feb. 2006 Page(s):148 - 160
Digital Object Identifier 10.1109/TVLSI.2005.863753
Se-Joong Lee; Kangmin Lee; Seong-Jun Song; Hoi-Jun Yoo
Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II:
Analog and Digital Signal Processing, IEEE Transactions on]
Volume 52, Issue 6, June 2005 Page(s):308 - 312
Digital Object Identifier 10.1109/TCSII.2005.848972
성균관대학교 정보통신공학부
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Contents
• Introduction
• NoC Architecture
– Overall Architecture
– Packet Routing Scheme
– Chip-to-Chip Connectivity
– Topology Selection
– Physical Transfer Unit Size
– Hierarchical Circuit/Packet Switching
– Synchronization
– NoC Protocol
• Low-Power Techniques
– Low-Swing Signal
– Mux-Tree Based Round-Robin Scheduler
– Crossbar Partial Activation Technique
– Low-Energy Coding On-Chip Serial Link
• Implementation and Measurement Result
• Conclusion
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Introduction
• System-on-Chip (SoC)
– More than a billion transistors are integrated on a single chip.[1.
1]
– Wire delays have become more critical[1. 2]
– The synchronization problem Heterogeneous NoC architecture
• The clock frequencies increase
• The feature sizes decrease
• NoC Solution
– How to interconnect efficiently
• Focus
– Performance and Scalability
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NoC Architecture
• Overall Architecture
– Essential Part of NoC
•
•
•
•
•
•
•
Network0 Interface (NI)
Up-Sampler (UPS)
Link Wires
FIFO Synchronizer with a queuing buffer (SYNC)
Switch
Overall architecture of the On Chip Network
Down-Sampler (DNS)
Off-chip Gateway (OGW)
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NoC Architecture
• Packet Routing Scheme
– Routing Process
• A packet is transferred to a destination according to route information in the
packet header.
Switch port index, Header Format, Header modification
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NoC Architecture
• Chip-to-Chip Connectivity
– Off-chip Gateway(OGW)
• OGWs provide chip-to-chip packet transaction
Chip-to-Chip connection using OGWs
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NoC Architecture
• Topology Selection
– The first step for NoC architecture design
– There are basic topologies
• Mesh Topology
– Mesh topology widely used and studied for parallel computing architecture.
• Star Topology
– Star topology has not been popularly used because it has a limitation of scalability
– Optimal to SoC design( PUs may be placed irregularly to minimize chip area)
Mesh area  (5 N  4 N ) ASYNC
 (25N  36 N ) A1SW  4( N  N ) ALNK
Star area  NASYNC  N 2 A1SW  N N ART
the number of PUs = N
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NoC Architecture
• Topology Selection
Energy consumption according to a number of PUs
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NoC Architecture
• Topology Selection
Network area according to a number of PUs
– The network area cost
including the
area of…
•
•
•
•
Switches
Multiplexers
Demultiplexers
links
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NoC Architecture
• Physical Transfer Unit(PHIT) Size
– A packet is divided and transmitted through the core network.
Serialization ratio (SERR) = packet size / phit size
Energy and Area of OCN according to SERR
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NoC Architecture
• Hierarchical Circuit and Packet Switching
– Local Intracluster Network
→ Circuit Switching
• The Circuit switching does not need packet buffers
• Area and Power consumption can be reduced
– Global Intercluster Network
→ Packet Switching
• The global intercluster traffic shares the bandwidth of the
switch-to-switch
link
• The throughput of the shared and limited link is more important
rather than
the latency
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NoC Architecture
• Synchronization
– Heterogeneous Multiprocessing System(multi timing reference)
Synchronization structure in the NoC
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NoC Architecture
• NoC Protocol
Packet Format, Burst READ/WRITE Transactions
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Low-Power Techniques
• Low-Swing Signaling
– The global link consumes higher power than local
link does
Low-swing signaling and its transceiver circuits
– Low-signaling
can alleviate its energy
consumption significantly[2. 13]
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Low-Power Techniques
• Low-Swing Signaling
(a)Energy consumption (b)Energy and delay product
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Low-Power Techniques
• Mux-Tree Based Round-Robin Scheduler
Mux-tree-based round-robin scheduler
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Low-Power Techniques
• Crossbar Partial Activation Techniques
(CPAT)[2.
10]
Schematic Diagram of Crossbar
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Low-Power Techniques
• Low-Energy Coding on On-Chip Serial Link
transitions in parallel with serial communications
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Low-Power Techniques
• Low-Energy Coding on On-Chip Serial Link
– Serialized low-energy transmission (SILENT)
technique[2. 18]
• To minimize the transmission energy on the serial wire
t)
B (by
[i ] using
 b (t ) [i ]  b (t 1)the
[i ], data
for i correlation
0  (n  1) properties
– The
is expressed
as follows:
B (t ) [n encoding
 1: 0] : n  bit algorithm
original data word
at time t
b (t ) [n  1: 0] : n  bit encoded data word at time t
Encoder/Decoder
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Low-Power Techniques
• Low-Energy Coding on On-Chip Serial Link
– Serialized low-energy transmission (SILENT)
Average power consumption on18]
serial communications
technique[2.
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Implementation and
Measurement Results
• Implemented multimedia SoC
– proposed NoC architecture, protocol and lowBlock
diagram of atechniques
prototype SoC
power
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Implementation and
Measurement Results
• Implemented multimedia SoC
– proposed NoC architecture, protocol and lowpower techniques
Measured packet signals
On-chip network power consumption
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Conclusion
• A low-power NoC is designed and
implemented for high-performance SoC
application
• Heterogeneous IPs are interconnected in a
hierarchical star topology
• Various power-efficient techniques were
suggested and implemented
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