Download Memory Devices - Chapter 3

Memory Devices - Chapter 3
• Major advantage of digital systems is the
ability to store large amounts of digital data
• For long and short periods of time based on
requirements
• A flip-flop is a storage mechanism
• Other systems can be used as well
• Advances in semiconductor technology have
enabled smaller and more efficient memory
storage systems and methods
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
1
Semiconductor Memories
•
Semiconductor memories are
used as the internal memory of
a computer
• Speed is important
•
•
•
This memory is in constant
communication with the central
processing unit (CPU)
It contains the program code
and the working data of the
operations taking place
Computers also have auxiliary
memory or mass storage
• Hard disks, CDROM, tape
• Much slower
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
2
Semiconductor Memories
•
Memory Cell
• A device used to store a single bit
•
Memory Word
• A group of bits that represent some type of information
•
Byte
• A group of 8 bits
•
Nibble
• A group of 4 bits or half a byte
•
Capacity
• A specification of the number of bits that can be stored in a memory device
• 4096 x 20 = 81920 bits or 4K x 20 (1K = 1024)
• Should use KiB, MiB, GiB when referring to 2x multipliers
•
Density
• Similar to capacity; often used to compare memories
•
Address
• Describes the location of a word in memory
• Should never exceed the maximum address of the device
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
3
Semiconductor Memories
• READ Operation
• Operation where a binary word
stored in a specific address is
sensed and relayed to an
“output”
• WRITE Operation
• Operation where a new word is
placed at a particular address
• Access Time
• Time for data to become
available when reading (tACC)
• A measure of the device’s
operating speed
• Cycle Time
• Time to complete a read/write
operation before becoming
available for another
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
4
Semiconductor Memories
•
Volatile Memory
• A type of memory that requires electrical power in order to store information
•
Random Access Memory (RAM)
• A type of memory where the access time is constant
•
Sequential Access Memory (SAM)
• A type of memory where the access time varies based on the address of the
information
•
Read/Write Memory (RWM)
• Memory that can be read and written easily
•
Read-Only Memory (ROM)
• A type of memory that can only be read
•
Static Memory Devices
• Semiconductor memory where the data is stored as long as power is applied
•
Dynamic Memory Devices
• Semiconductor memory where the data is not permanently stored even
though power is applied unless it is periodically written to
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
5
General Memory Operation
•
•
•
1.
2.
3.
4.
5.
•
Memories have different internal
circuits
Generally, we connect to memory
through a common system
Most memories support these
functions:
Set the address for READ/WRITE
Set READ/WRITE operation
Supply data for WRITE operation
Hold the output data for READ
operation
Enable/Disable memory so it will
not respond to commands
Be aware that some functions are
active on LOW signals (signified
by a bar above the signal name)
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
6
Read Only Memories
•
•
•
•
Memory designed to
hold data that is
permanent or does
not frequently change
Data may be stored
during manufacturing
process or electrically
Useful for computers
during startup as the
ROM contains the
necessary code
Many electronics use
ROMs to store
important information
needed for the proper
operation of the
system
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
7
ROM Architecture
•
ROM ICs are very
complex
• Only examine a
simplified version
• 16x8 ROM
Register Array
• Made up of an array
of 8-bit registers
• Registers’ outputs
are connected to a
common output bus
• Each register has two
enable pins, both
need to be 1 so that
an output is placed
on the bus
© 2003-2017 Roberto Muscedere
2-to-4
decoder
2-to-4
decoder
Images and Text Portions © 2003 Prentice Hall
8
ROM Architecture
Address Decoders
• The address code
(A3A2A1A0)
determines which
register of the array
is enabled
• Part of this code
(A1A0) is fed to a
decoder, which
activates one row’s
select line
• The other part of the
code (A3A2) goes to
another decoder,
which activates one
column’s select line
• Only one register will
have both enables
set to 1
© 2003-2017 Roberto Muscedere
2-to-4
decoder
2-to-4
decoder
Images and Text Portions © 2003 Prentice Hall
9
ROM Architecture
Output Buffers
• The register that is
enabled will place its
data on the shared bus
• This bus is fed into the
output buffers, which
pass data to the
external data output
only if CS is low
• If CS is high, the output
will be high-z
• This is just an example
•
•
•
Generally, the
physical chip is made
to be as square as
possible
1024x8 ROM may be
organized as 64x16
registers internally
2-to-4
decoder
2-to-4
decoder
Capacities range from
32 to 1M bytes
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
10
ROM Timing
•
There is a
propagation delay
between the
application of inputs
to the ROM and the
point where valid
outputs appear
• This is called the
access time
•
•
•
Typically, the CS is
held high and is set
to 0 once the address
has been set
After some time, tOE,
the outputs will
appear on the output
bus
To begin the process
again, CS may need
to be set high again
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
11
Types of ROMs
• Mask-Programmed ROM
• Device is made with contents
of the memory hardwired by
placing and removing
transistors
• Very expensive to create as
they are essentially an
Application Specific IC
(ASIC)
• Programmable ROMs
(PROMs)
• Contain a fusible-link that can
be programmed just one-time
using a higher system
voltage
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
12
Types of ROMs
• Erasable PROMs (EPROMs)
• Similar to a PROM, but it can also
be erased
• Uses a floating gate, which can be
“reset” by applying a UV light
source
• Electrically Erasable PROMs
(EEPROMs)
• Floating gate can be reset by an
external voltage instead of a UV
light source
• Flash Memory
• Modern devices (smaller, faster)
• Uses bulk erase to purge large
portions of memory to improve
performance
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
13
ROM Applications
•
Firmware
• Operational code for embedded microprocessors in “firmly stored” ROMs
•
Bootstrap
• Initial firmware to enable a CPU to load the next phase of code from an
auxiliary storage system
•
Data Tables
• Used to store data, which is not easily generated by other circuits
• Can be used in conjunction with a data converter to produce any function
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
14
Semiconductor RAMs
• Although RAM refers to memory where the access
time is constant, it is often common practice to use
the term RAM to refer to read/write memory (RWM)
• We will always use the term RAM to describe
semiconductor RWM
• RAMs are used for temporary storage
• When power is removed, the contents are lost
• Very fast compared to other storage systems
• Can use “standby” modes to preserve contents
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
15
RAM Architecture
•
RAM ICs are more
complex than ROMs
• Only examine a
simplified version
•
•
•
•
Basically an array of
registers to which we
can read/write
information
64 x 4 RAM
Sometimes /WE is
used instead of R/W
Often the number of
pins is minimized
and, therefore,
multiplexing is used
to interface with
RAMs
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
16
RAM Architecture
READ Operation
• Set Address
• Set R/W to 1
• Set /CS to 0
• Wait for output
WRITE Operation
• Set Address
• Set R/W to 0
• Set /CS to 0
• Set Data
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
17
Static RAM
• RAM operation up to now
has been in regards to
static RAM (SRAM)
• Essentially flip-flops, but
actually two inverters backto-back
• Built in a variety of
technologies (Bipolar,
NMOS, CMOS)
• CMOS is becoming more
popular as the power and
area are significantly reduced
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
18
Static RAM Timing
•
SRAMs are usually
interfaced directly to
CPU controllers in
order to maximize
efficiency
READ Operation
• Many variations in
timing information
(depends on vendor)
• Parameters:
tRC = Read Cycle Time
tACC = Access Time
tCO = Time for outputs
to become active
tOD = Time outputs
remain active
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
19
Static RAM Timing
WRITE Operation
• Parameters:
tWC = Write Cycle
Time
tAS = Address Setup
Time
tAH = Address Hold
Time
tW = Write Time
tDS = Data Setup
Time
tDH = Data Hold
Time
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
20
Dynamic RAM
• Usually fabricated with MOS technologies to increase
capacity, speed and lower power requirements
• Stores information on charges in small capacitors
(transistors)
• Very high capacity (4x), lower cost than SRAM (1/5)
• Charge is lost over time and bits must be “refreshed” to
retain information (every 8 ms for example)
• Some DRAMs have built in refresh and some require
external circuitry
• Larger address space requires a larger number of pins;
multiplexing inputs
• Generally not used in applications where speed and simple
interfacing are required
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
21
Dynamic RAM
• Architecturally,
DRAMs are an
array of registers
• For example:
• 1 bit register
• 14 bit input
• Two decoders
• Row (7 bit)
• Column (7 bit)
• Row is applied
first, then the
column
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
22
Dynamic RAM
•
•
•
Symbolic representation of a 1 bit cell
During a write, S1 and S2 are closed
During a read, S2, S3 and S4 are closed
• Feedback enables write-after-read and refresh
•
•
Switches are actually MOSFETs, which are controlled by internal
circuitry
Voltage on capacitor is converted to a “0” or “1” by using the Sense
Amplifer
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
23
Dynamic RAM
Address Multiplexing
•
Example:
• 16384x1 DRAM
•
Generalized
connection (like
SRAM) requires:
•
•
•
•
•
14 address (Ax)
2 control (R/W, CS)
2 data (DI,DO)
18 total
Using multiplexing:
• 7 address (Ax)
• 3 control
(CAS,RAS,R/W)
• 2 data (DI,DO)
• 12 total
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
24
Dynamic RAM
Address Multiplexing
•
Two address strobes
are used:
•
•
•
Two steps are required
to select address
•
•
•
/RAS = row address
strobe
/CAS = column
address strobe
Place low order
address on bus first,
assert /RAS
Place high order
address on bus
second, assert /CAS
/CS is replaced by
/RAS and /CAS (must
both be low for the
DRAM to output)
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
25
Dynamic RAM Interfacing
Address Multiplexing
• Interfacing SRAMs
to other devices is
simple
• Additional logic
may be required to
control R/W and
/CS
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
26
Dynamic RAM Interfacing
Address Multiplexing
•
•
•
•
•
Interfacing DRAMs to other
devices is more complicated as
the address multiplexing needs
to be considered
In this case, a MUX is needed to
direct the address at the right
time
Additional logic is required to
control MUX, /RAS, /CAS and
refresh
Fewer DRAM pins, but more
components required for
connection
Some systems have this
addressing circuit built-in
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
27
Dynamic RAM Read Timing
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
28
Dynamic RAM Write Timing
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
29
Dynamic RAM Refreshing
•
•
•
•
•
•
•
A DRAM cell is refreshed after each READ is performed
It also needs to refresh every 4-8 ms
This is impossible with very large DRAMS
Manufacturers design DRAMs to refresh each ROW after a READ
When RAM is idle, each row is refreshed in sequence or in a distributed
order
Manual method: /RAS-only refresh; /CAS and R/W remain high while
address is cycled
Newer devices have automatic refresh; controlling system has to enable
it
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
30
Expanding Word Size
• Sometimes we are unable
to find the memory chips
required for a design
• Can combine more than
one chip to achieve the
desired result
• Expanding word size
• Use multiple RAMs in
parallel to increase output
bus
• Example: 2 16x4 RAMs
create a single 16x8 RAM
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
31
Expanding Word Size
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
32
Expanding Word Size
• DRAMs
usually
have few
I/O bits
• Combine
them to
create
larger
data
busses
© 2003-2017 Roberto Muscedere
[11]
Images and Text Portions © 2003 Prentice Hall
33
Expanding Capacity
• Expanding capacity
• Use multiple RAMs
in “series” to
increase address
space
• Higher order
address line is used
to control which
RAM is enabled
• One handles the
high
• One handles the low
• Example: 2 16x4
RAMs create a
single 32x4 RAM
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
34
Expanding Capacity
• More
than two
devices
to
increase
address
space
• Use
decoder
to
generate
/CS
signals
© 2003-2017 Roberto Muscedere
Images and Text Portions © 2003 Prentice Hall
35