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Power Consumption in CMOS CONCORDIA VLSI DESIGN LAB 1 Power Dissipation in CMOS Two Components contribute to the power dissipation: » Static Power Dissipation – Leakage current – Sub-threshold current » Dynamic Power Dissipation – Short circuit power dissipation – Charging and discharging power dissipation CONCORDIA VLSI DESIGN LAB 2 Static Power Consumption CONCORDIA VLSI DESIGN LAB 3 Static Power Dissipation VDD Leakage Current: • P-N junction reverse biased current: iL= A. is(eqV/kT-1) • Typical value 1pA to 5A /µm2@room temp. • Total Power dissipation: PsL= iL.VDD Sub-threshold Current • Relatively high in low threshold devices CONCORDIA VLSI DESIGN LAB S G MP B D Vin Vo D G B MN S GND 4 Subthreshold Current Vgs <≈Vt Vss CONCORDIA VLSI DESIGN LAB Vdd 5 Subthreshold Current CONCORDIA VLSI DESIGN LAB 6 Analysis of CMOS circuit power dissipation The power dissipation in a CMOS logic gate can be expressed as P = Pstatic + Pdynamic = (VDD · Ileakage) + (VDD . Isubthreshold) + (VDD · Ilshort circuit) + (α · f · Edynamic) Where α is the switching probability or activity factor at the output node (i.e. the average number of output switching events per clock cycle). The dynamic energy consumed per output switching event is defined as Edynamic = CONCORDIA VLSI DESIGN LAB i VDDdt DD 1 _ switching_ event 7 Charging and discharging currents Discharging Inverter CONCORDIA VLSI DESIGN LAB Charging Inverter 8 Currents due to Charging and Discharging CONCORDIA VLSI DESIGN LAB 9 Power Dissipation: Dynamic tp Vin VDD VDD 0 S G t1 VDD MP D Vo Vin Vout D ic ip ip ip G in CL MN S in GND CONCORDIA VLSI DESIGN LAB 10 Power Dissipation: Dynamic During charging 1 t1 Pdp = ----- ip t VDD – Vo dt tp 0 ip t = C dVo ----------L dt S G VDD MP D Vo D C VDD Pdp = ------LVDD – Vo dVo tp 0 CL Pdp = -------- VDD 2 2tp CONCORDIA VLSI DESIGN LAB ip G CL MN S GND 11 Power Dissipation: Dynamic During Discharging 1 tp Pdn = ----- in t Vod t tp t1 in t = – C dVo ----------L dt C 0 LPdn = -----–Vo dVo tp VDD C L VDD2 = ------- ---------------tp 2 CONCORDIA VLSI DESIGN LAB S G VDD MP D Vo D G in CL MN S GND 12 Power Dissipation: Dynamic Total Power dissipation Pdp+ Pdn = (CL/tp) (VDD)2 = CL. f. (VDD)2 Taking node activity factor α into consideration: The power dissipation= α CL. f. (VDD)2 CONCORDIA VLSI DESIGN LAB 13 The MOSFET parasitic capacitances • distributed, • voltage-dependent, and • nonlinear. So their exact modeling is quite complex and accurate power modeling and calculation is very difficult, inaccurate and time consuming. CONCORDIA VLSI DESIGN LAB 14 Schematic of the Inverter CONCORDIA VLSI DESIGN LAB 15 CONCORDIA VLSI DESIGN LAB 16 CMOS Inverter VTC /short Circuit Current V out VDD 5 S MN off MP lin MN sat MP lin 4 G D Vout D MN lin MP sat 1 G ISC MN sat MP sat 3 Vin 2 MP MN lin MP off MN VGSN S 1 VTN GND CONCORDIA VLSI DESIGN LAB 2 3 4 5 VDD- |VTP| VDD V in ISC 17 Analysis of short-circuit current The short-circuit energy dissipation ESC is due to the railto-rail current when both the PMOS and NMOS devices are simultaneously on. ESC = ESC_C + ESC_n Where and CONCORDIA VLSI DESIGN LAB ESC _ c VDD ESC _ d VDD i dt i dt n v0 0 VDD p v0 VDD 0 18 Power Dissipation: short circuit current Short Circuit: S tr Vin G tf VDD-|VTP| MP VTN tp Isc D Vin Vo Isc D G For tr=tf = trf VTN=|VTP| The short circuit power dissipation: 3 t rf Kn P sc = ------- ( V DD – 2VT ) ----12 tp CONCORDIA VLSI DESIGN LAB MN S GND 19 Current flows with load A: Input B: VTC C: Current flow D: Current flow when load is increased CONCORDIA VLSI DESIGN LAB 20 Factors that affect the short-circuit current For a long-channel device, assuming that the inverter is symmetrical (n = p = and VTn = -VTp = VT) and with zero load capacitance, and input signal has equal rise and fall times (r = f = ), the average short-circuit current [Veendrick, 1994] is I mean 1 3 (VDD 2VT ) 12 VDD T From the above equation, some fundamental factors that affect short-circuit current are: W ( ) t L , VDD, VT, r,f and T. ox CONCORDIA VLSI DESIGN LAB 21 Parameters affecting short cct current For a short-channel device, and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). CL also affects short-circuit current. Imean is a function of the following parameters (tox is processdependent): CL, , T (or /T), VDD, Wn,p, Ln,p (or Wn,p/ Ln,p ), tox, … The above argument is validated by the means of simulation in the case of discharging inverter, CONCORDIA VLSI DESIGN LAB 22 The effect of CL on Short CCt Current CONCORDIA VLSI DESIGN LAB 23 Effect of tr on short cct Current CONCORDIA VLSI DESIGN LAB 24 Effect of Wp on Short cct Current CONCORDIA VLSI DESIGN LAB 25 Effect of time step setting on simulation results Tr (ps) 0 100 200 CONCORDIA VLSI DESIGN LAB Timestep (ps) 2 4 5 6 8 10 2 4 5 6 8 10 2 5 5 8 8 10 MaxStep (ps) 10 10 10 10 10 20 10 10 10 10 10 20 10 10 20 10 20 20 iMax (uA) 802.6 413.8 336.4 284.9 221 183 73.09 64.4 58.69 65.64 76.13 63.1 50.96 49.78 50.46 50.72 52.08 51.25 iaverage_inT/2 (uA) 1.258 1.264 1.24 1.234 1.245 1.231 1.202 1.213 1.21 1.208 1.207 1.217 1.311 1.295 1.313 1.311 1.311 1.311 26 Reducing Power Consumption It can be done in several ways: Circuit Design Architecture design Activity reduction Changing Vt Etc. CONCORDIA VLSI DESIGN LAB 27 Datapath to be optimised for power consumption CONCORDIA VLSI DESIGN LAB 28 Pipelining the circuit CONCORDIA VLSI DESIGN LAB 29 Parallelism CONCORDIA VLSI DESIGN LAB 30 Parallelism and pipelining CONCORDIA VLSI DESIGN LAB 31 Activity reduction . CONCORDIA VLSI DESIGN LAB 32 Power Distribution CONCORDIA VLSI DESIGN LAB 33 Thank you ! CONCORDIA VLSI DESIGN LAB 34 Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application CONCORDIA VLSI DESIGN LAB 35 Interconnect/Via CONCORDIA VLSI DESIGN LAB 36 Large Vias An example of replacing one large contact cut with several smaller cuts to avoid current crowding CONCORDIA VLSI DESIGN LAB 37 Electromigration Electromigration is the forced movement of metal ions due to an electric field Ftotal = Fdirect + Fwind Direct action of electric field on metal ions Anode + Force on metal ions resulting from momentum transfer from the conduction electrons << Al Al Al + Al Al Al - Al Al E Cathode - Al- Note: For simplicity, the term “electron wind force” often refers to the net effect of these two electrical forces CONCORDIA VLSI DESIGN LAB 38 Electromigration => Metal atoms (ions) travel toward the positive end of the conductor while vacancies move toward the negative end Effects of electromigration in metal Voids interconnects: • Depletion of atoms (Voids): Slow reduction of connectivity Interconnect failure Short cuts (Deposition • of atoms) CONCORDIA VLSI DESIGN LAB Hillocks 39 CONCORDIA VLSI DESIGN LAB 41 http://ap.polyu.edu.hk/apavclo/public/gallery.htm CONCORDIA VLSI DESIGN LAB 42 http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html CONCORDIA VLSI DESIGN LAB 43 http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html e CONCORDIA VLSI DESIGN LAB e www.lamel.bo.cnr.it/research/ elettronica/em/rel_res.htm e 44 Incubation period CONCORDIA VLSI DESIGN LAB 45 Mean Time To Failure CONCORDIA VLSI DESIGN LAB 46 Mean Time To Failure DC interconnect, the MTTF is defined as: MTTFDC AJm 2 exp E kT A is the area, Jm is the current density, E is 0.5eV, K is the Boltzsman constant, and T is the absolute temperature. For Ac interconnect the MTTF is defined as E kT 2 AC Jm Jm k Jm DC A exp MTTFDC Jm Jm AC DC CONCORDIA VLSI DESIGN LAB is the average current density, is the average absolute current density and is a constant. 47 Layout of a controller http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vcc-on-an-ic CONCORDIA VLSI DESIGN LAB Reasons for having multiple supply lines. • Current has to be distributed, it is impractical that any pad can take the total current. The resistance drop is prohibiting • Power coming in from any one pin will probably have to snake it's away around a lot of stuff to get to every part of the device. Multiple power lines gives the device multiple avenues to pull power from, which keeps the voltage from dipping as much during high current events. • Need for a clean supply voltage at certain areas. • Analog devices require special attention and probably different voltage supply. • Heat distrubution, and removal CONCORDIA VLSI DESIGN LAB Xilinx Virtex I/O distribution The figure represents all of the power and ground pins on a Virtex 4 FPGA in a BGA package with 1513 pins. The FPGA can draw up to 30 or 40 amps at 1.2 volts Every I/O pin is adjacent to at least one power or ground pin, minimizing the inductance and therefore the generated crosstalk. http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vccon-an-ic CONCORDIA VLSI DESIGN LAB Example Assume a chip of 0.5cm by 0.5cm fed by one Vdd pad. The chip consumes 1A at 3.3Volts. Determine the voltages on points marked X, Y and Z. Are these values Acceptable? What can you do about it? (assume Jm = 1mA/um2 and a 1µm thick aluminum) CONCORDIA VLSI DESIGN LAB 51 Thank you ! CONCORDIA VLSI DESIGN LAB 52