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Models for Hand Analysis
NMOS Transistor
2

1
IDS N = KN  VGSN – VTN VDSN – ---VDSN 
2
2
1
IDSN = ---KN VGSN – VTN  1 +  VDSN 
2
VDSN  VGSN-VTN
VDSN VGSN-VTN
KN=(W/L)K’N
PMOS Transistor
2

1
I D SP = –K P  VGS P – V TPV D SP – --- VD SP 
2
VDSP VGSP -VTP
2
1
ID SP = – -- Kp VGS P – VTP    1 – VDS P
2
VDSP VGSP-VTP
KP=(W/L)K’P
CONCORDIA
VLSI DESIGN LAB
1
pMOS Current model
2

1
I D SP = –K P  VGS P – V TPV D SP – --- VD SP 
2
2
1
IDSP = –-- Kp VGS P – VTP    1 – VDS P
2
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VLSI DESIGN LAB
VDSP>VGSP -VTP
VDSP <VGSP-VTP
2
Channel Resistance
R=
CONCORDIA
VLSI DESIGN LAB
1
Bn (V gs  Vt )
R=
2
 n [Vgs  Vt ]2 
3
Variation of resistance with Vgs
CONCORDIA
VLSI DESIGN LAB
4
Linear Scaling
CONCORDIA
VLSI DESIGN LAB
LENGTH
L
S
L/S
WIDTH
W
S
W/S
THIN OXIDE
tox
S
tox/S
DIFFUSION DOPING
ND
1/S
ND . S
SUBSTRATE DOPING
NA
1/S
NA . S
SUPPLY VOLTAGE
VDD
1/S
VDD/S
5
Scalling Effects
CONCORDIA
VLSI DESIGN LAB
6
Velocity Saturation and mobility Degradation
CONCORDIA
VLSI DESIGN LAB
7
TOH’s Model for Short Channel
2
W
V
I D  nCox [Vgs  ds ]
L
2
for
I D  kVsat CoxW (Vgs  Vt )
for
Vdsat  (1  k )(Vgs  Vt )
E sat 
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VLSI DESIGN LAB
2Vsat
K
Vds  Vdsat
Vds  Vdsat
1
1

E
L
1  sat 1  Esat
E
(Vgs  Vt )
n
8
Secondary Effects

Subthreshold current:
is the small current that flows from drain
at Vgs < Vt

Punch through:
If a large voltage is applied to Vds, then the
depletion region of the drain can extend to the source, a punch through
occurs and under these condition a large current can flow from the drain to
source.

Hot carrier: As a results of scaling, device dimensions are
reduced while, doping concentrations are increased, while voltages
are not reduced to the same proportion, as a consequence there is
an increase in electric field in the channel region while, the thickness
of the gate insulating layer is thinner. Due to the acceleration of
electrons by the Vds, electrons and holes gaining high speed can
penetrate the gate insulator and change its characteristics.

Channel hot electrons: If the Vds is increased, then
the
lateral electric field is increased and the electric field accelerates the
electrons near the drain with high kinetic energy they are injected
into the oxide near the drain.
CONCORDIA
VLSI DESIGN LAB
9
Semiconductor Resistors
Resistance
R=  (l /A)
= (/t). (l /w)
= Rsh. (l /w)
current
1
 = ----------------------------------------------  n  q +   p  qn
p
Rsh = sheet resistance Ω/
For 0.5u process:
N+ diffusion : 70 Ω/
P+ diffusion : 140 Ω/
Polysilicon : 12 Ω/
Polycide:2-3 Ω/
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VLSI DESIGN LAB
l
t
w
(A)
M1: 0.06 Ω/
M2: 0.06 Ω/
M3: 0.03 Ω/
P-well: 2.5K Ω/
N-well: 1K Ω/
10
Semiconductor Resistors
Diffusion
n+
polysilicon
Al
Field oxide
Polysilicon Resistor
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VLSI DESIGN LAB
Al
SiO2
n+
Diffusion Resistor
11
Variations in Width and Length
1. Width
Oxide encroachment
Weff = Wdrawn- 2WD
polysilicon
Weff
Wdrawn
WD
WD
polysilicon
2. Length
Lateral diffusion
LD = 0.7Xj
Leff = Ldrawn- 2LD
CONCORDIA
VLSI DESIGN LAB
Ldrawn
LD Leff
LD
12
Semiconductor Capacitors
1. Poly Capacitor:
a. Poly to substrate
b. Poly1 to Poly2
2. Diffusion Capacitor
sidewall
capacitances
depletion region
n+ (ND)
substrate (NA)
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VLSI DESIGN LAB
bottomwall
capacitance
13
Transistor Resistance
Two Components:
Drain/ Sources Resistance:
(G)
: (S)
n+
RD(S) = Rsh x no. of squares+
contact resistance.
L
(D)
n+
W
Channel Resistance:
Depends on the region of operation:
RCH = -------------------------------1
--------------------------------- '
W
K'  -----    VGS – VT   –V DS 
L
RC H = -------------------------2
--------------------------2W
K'  -----     V
– VT
L
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VLSI DESIGN LAB
RS
Rch
RD
Linear
Saturation
GS
14
Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
CONCORDIA
VLSI DESIGN LAB
15
Prentice Hall/Rabaey
The Gate Capacitance
CONCORDIA
VLSI DESIGN LAB
16
Prentice Hall/Rabaey
Average Gate Capacitance
Different distributions of gate capacitance for varying
operating conditions
Most important regions in digital design: saturation and cut-off
CONCORDIA
VLSI DESIGN LAB
17
Prentice Hall/Rabaey
Diffusion Capacitance
CONCORDIA
VLSI DESIGN LAB
18
Prentice Hall/Rabaey
Diffusion Capacitance
CD  C J * L *W  C JSW * (2 L  2W )
AD
PD
CD  CJ
 C JSW
VBD MJ
VBD MJSW
[1 
]
[1 
]
PB
PB
CONCORDIA
VLSI DESIGN LAB
19
SPICE TRANSISTOR MODEL
CONCORDIA
VLSI DESIGN LAB
20
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
CONCORDIA
VLSI DESIGN LAB
21
MAIN MOS SPICE PARAMETERS
CONCORDIA
VLSI DESIGN LAB
22
Prentice Hall/Rabaey
SPICE Parameters for Parasitics
CONCORDIA
VLSI DESIGN LAB
23
Prentice Hall/Rabaey
SPICE Transistors Parameters
CONCORDIA
VLSI DESIGN LAB
24
Prentice Hall/Rabaey
Example
CONCORDIA
VLSI DESIGN LAB
25