Download ECGR 2255 Lab Write-Ups

2210 Experiment 13 – CMOS Logic
ELEC 2210 EXPERIMENT 13
CMOS Logic
Objectives:
The experiments in this laboratory exercise will provide an introduction to CMOS logic
circuits. You will use the Bit Bucket breadboarding system to build and test several CMOS
circuits. The objectives of this experiment include the following:
 Reinforce basic principles of CMOS logic from ELEC 2210 lecture.
 Continue to develop professional lab skills and written communication skills.
Introduction
A thorough treatment of CMOS logic can be found in Chapter 7 of the ELEC 2210
textbook, Microelectronics Circuit Design by R.C. Jaeger.
The acronym CMOS stands for Complementary Metal Oxide Semiconductor. CMOS
logic circuits use one NMOS and one PMOS transistor per input. These are interconnected
in such a way that there is never a DC path from the power supply to ground, resulting in
zero static power dissipation. A CMOS logic inverter circuit is shown in Fig. 1.
Figure 1. CMOS logic inverter. When MP is on, MN is off, and vice-versa.
More complex CMOS circuits can be designed by extending the basic architecture of the
inverter. Two-input CMOS NOR and NAND gates are shown in Fig. 2.
T. Roppel Nov. 2009
1
2210 Experiment 13 – CMOS Logic
Figure 2. CMOS gates. (a) NOR: Y = (A+B)* and (b) NAND: Y = (AB)*.
In order to simplify the drawings in Fig. 2, bubbles are used. Bubbles with the same name
are connected in the actual circuit. Logic variable names are used at the input and output
terminals. For CMOS, the logic levels are “rail-to-rail,” so that logic HIGH = VDD and
logic LOW = ground.
The CMOS Transmission Gate is a special-purpose gate that acts as a bi-directional switch.
The switch can be turned on or off by applying complementary logic signals to the
transistor gates. This is shown in Fig. 3.
(a)
Figure 3. CMOS Transmission Gate. (a) Standard symbol. (b) Gate ON, vout
connected to vin (c) Gate OFF, no connection between vout and vin.
In this experiment, we will be using a matched complementary pair, the AOP605. This is
an 8-pin chip that contains one NMOS and one PMOS transistor. The pinout is shown in
Fig. 4. You will use several of these for this experiment.
T. Roppel Nov. 2009
2
2210 Experiment 13 – CMOS Logic
Figure 4. Pinout of the AOP605 chip. For building CMOS logic, one chip is required
for each input variable.
Pre-Lab:
(1) Obtain the data sheet for the AOP605 from the class web site, or from
http://www.aosmd.com/pdfs/datasheet/AOP605.pdf
(2) Use the package pinout to carefully draw a wiring diagram for the logic function Y =
(A+BC)* . You will need to use three AOP605 chips. Draw the outline of each chip with
all pins numbered and labeled, and show all interconnections, including power supply and
ground. Bring one copy of this to submit, and one to use in lab.
(3) Construct the truth table for the logic function in (2). Bring an extra copy to use in lab,
with two additional output columns labeled Output Voltage and Output Logic Level left
blank to fill in during the experiment.
Lab Exercise:
There are 3 parts. Have your GTA sign off on each part as you proceed.
(1) Voltage Transfer Characteristic for CMOS Inverter.


Construct a CMOS logic inverter using one AOP605 chip. Use the Bit Bucket 5 V
DC supply for VDD.
Measure the output voltage and the power supply current as a function of the input
voltage over the range of 0 to +5 V. Use the Bit-Bucket variable DC source to
provide the input voltage. Do not exceed 5 V. Use the Bit-Bucket DVM to
measure the input voltage, the oscilloscope to measure the output voltage, and a
DMM to measure current. Make sure the ‘scope is set to measure DC (not AC).
T. Roppel Nov. 2009
3
2210 Experiment 13 – CMOS Logic
Questions: (a) At what voltage (range) does your inverter switch logic levels? (b) What
are the output logic level voltages? (c) What is the power dissipation (VDD x ID) for each
logic level?
(2) CMOS Logic Design
Connect a CMOS logic circuit that implements Y = (A+BC)*. Use the wiring diagram you
prepared in your pre-lab.
Use the leftmost three data switches on the Bit Bucket to provide inputs A, B, and C. Use
one of the LED’s to display the output Y. Verify the truth table.
(3) CMOS Transmission Gate





Construct a CMOS transmission gate as shown in Fig. 3, and connect a 1 kΩ
resistor from the output to ground to serve as a pull-down.
Use the left-most data switch (#7) for input A and the next one (#6) for input A*.
With the gate OFF (A = 0, A* = 1), use the variable DC source to provide input
voltage over the range from 0 to 5 V in 1 V steps, and measure the output voltage.
With the gate ON (A = 1, A* = 0), use the variable DC source to provide input
voltage over the range from 0 to 5 V in 1 V steps, and measure the output voltage.
Apply a sine wave signal from the Bit Bucket to the T-gate input, and observe the
output on the oscilloscope. Discuss your observations as you adjust the amplitude
of the sine wave, and as you turn the T-gate on and off.
Questions: (a) Does the T-gate operate as expected? (b) Did you observe any limitations
on performance, such as a limit on the range of input voltage for which it functions as
expected?
T. Roppel Nov. 2009
4