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UNIT I
Power Supplies
Biasing BJT and MOSFET
Outline
• Rectifier
• BJT Biasing
• FET Biasing
Block diagram of Power Supply Unit
RECTIFIER
• Transformer: To Step down AC voltage amplitude
to the desired DC voltage (by selecting an
appropriate turn ratio N1/N 2 for the transformer)
Isolate equipment from power-line .
• Rectifier: Converts an ac input to a unipolar output
Filter.
Filter
• Convert the pulsating input to a nearly constant dc
output Regulator.
•
Reduce the ripple of the dc voltage.
Half wave Rectifier
Half wave Rectifier- contd…
Half wave Rectifier -contd…
• The input is an alternating current. This input
voltage is stepped down using a transformer. The
reduced voltage is fed to the diode ‘D’ and load
resistance RL.
• During the positive half cycles of the input
wave, the diode ‘D’ will be forward biased.
Half wave Rectifier-contd…
• During the negative half cycles of input wave, the
diode ‘D’ will be reverse biased. We take the
output across load resistor RL.
Half wave Rectifier-contd…
• The diode passes current only during one half
cycle of the input wave.
• The output is positive and significant during the
positive half cycles of input wave.
Half wave Rectifier-contd…
• At the same time output is zero or insignificant
during negative half cycles of input wave. This is
called half wave rectification.
• Dc current given by
Half wave Rectifier-contd…
• The ratio of dc power output to the applied input
a.c power is known as rectifier efficiency, denoted
by η.
Half wave rectifier with filter
Half wave rectifier with filter-contd…
Half wave rectifier with filter-contd…
• Output of half wave rectifier is not a constant DC
voltage. It is a pulsating dc voltage with ac
ripples.
• In real life applications, we need a power supply
with smooth wave forms. we desire a DC power
supply with constant output voltage.
Half wave rectifier with filter-contd…
• We can make the output of half wave rectifier
smooth by using a filter (a capacitor filter or an
inductor filter) across the diode.
• We can also use an resistor-capacitor coupled
filter (RC).
Full wave rectifier
Full wave rectifier-contd…
• In a Full Wave Rectifier circuit two diodes are
used, one for each half of the cycle.
• A multiple winding transformer is used whose
secondary winding is split equally into two halves
with a common centre tapped connection, (C).
Full wave rectifier-contd…
• When point A of the transformer is positive with
respect to point C, diode D1 conducts in the
forward direction as indicated by the arrows.
• When point B is positive (in the negative half of
the cycle) with respect to point C,
diode D2 conducts in the forward direction.
• The current flowing through resistor R is in the
same direction for both half-cycles.
Full wave rectifier-contd…
• This configuration results in each diode
conducting in turn its anode terminal is positive
with respect to the transformer centre
point C producing an output during both halfcycles, twice that for the half wave rectifier so it is
100% efficient.
Full wave rectifier-contd…
Unidirectional current given by
Bridge Rectifier
Bridge Rectifier-contd…
• This type of single phase rectifier uses four
individual rectifying diodes connected in a closed
loop “bridge” configuration to produce the desired
output.
• The main advantage of this bridge circuit is that it
does not require a special centre tapped
transformer, thereby reducing its size and cost.
Bridge Rectifier-contd…
• The single secondary winding is connected to one
side of the diode bridge network and the load to
the other side as shown below.
• The four diodes labelled D1 to D4 are arranged in
“series pairs” with only two diodes conducting
current during each half cycle.
Bridge Rectifier-contd…
During positive
cycle of the input
Bridge Rectifier-contd…
• During the positive half cycle of the supply,
diodes D1 and D2 conduct in series
• Diodes D3 and D4 are reverse biased and the
current flows through the load as shown below.
Bridge Rectifier-contd…
During
Negative
cycle of the
input
Bridge Rectifier-contd…
• During the negative half cycle of the supply,
diodes D3 and D4 conduct in series.
• Diodes D1 and D2switch “OFF” as they are now
reverse biased.
• The current flowing through the load is the same
direction as before.
Bridge Rectifier-contd…
• The current flowing through the load is
unidirectional, so the voltage developed across the
load is also unidirectional the same as for the
previous two diode full-wave rectifier.
• The average DC voltage across the load
is 0.637Vmax.
Bridge Rectifier-contd…
The smoothing capacitor converts the full-wave rippled
output of the rectifier into a smooth DC output voltage.
Bipolar Junction Transistor(BJT)
• Bell Labs (1947): Bardeen, Brattain, and Shockley
• Originally made of germanium
• Current transistors made of doped silicon
Bipolar Junction Transistor(BJT)
• The basic of electronic system nowadays is
semiconductor device.
• The famous and commonly use of this device is
BJTs (Bipolar Junction Transistors).
• It can be used as amplifier and logic switches
Point-Contact Transistor –
first transistor ever made
Bipolar Junction Transistor(BJT)
• BJT consists of three terminal:
 collector : C
 base : B
emitter : E
• Two types of BJT : pnp and npn
• 3 layer semiconductor device consisting:
– 2 n- and 1 p-type layers of material  npn transistor
– 2 p- and 1 n-type layers of material pnp transistor
• The term bipolar reflects the fact that holes and electrons
participate in the injection process into the oppositely
polarized material
Basic models of BJT
npn transistor
Diode
Diode
pnp transistor
Diode
Diode
Transistor currents
-The arrow is always
drawn
on the emitter
-The arrow always point
toward the n-type
IC=the collector current
IB= the base current
IE= the emitter current
-The arrow indicates the
direction of the emitter
current:
pnp:E B
npn: B E
Understanding BJT working
force – voltage/current
water flow – current
- amplification
Transistor working PNP
Transistor working PNP
• Both biasing potentials have been applied to a pnp
transistor and resulting majority and minority carrier flows
indicated.
• Majority carriers (+) will diffuse across the forward-biased
p-n junction into the n-type material.
• A very small number of carriers (+) will through n-type
material to the base terminal. Resulting IB is typically in
order of microamperes.
• The large number of majority carriers will diffuse across
the reverse-biased junction into the p-type material
connected to the collector terminal.
Transistor working PNP
• Majority carriers can cross the reverse-biased junction
because the injected majority carriers will appear as
minority carriers in the n-type material.
• Applying KCL to the transistor :
IE = I C + IB
• The comprises of two components – the majority and
minority carriers
IC = ICmajority + ICOminority
• ICO – IC current with emitter terminal open and is called
leakage current.
Operation region summary
Operation
Region
Cutoff
IB or VCE
Char.
IB = Very
small
Saturation VCE = Small
Active
Linear
VCE =
Moderate
Breakdown
VCE =
Large
BC and BE
Junctions
Reverse &
Reverse
Forward &
Forward
Reverse &
Forward
Beyond
Limits
Mode
Open
Switch
Closed
Switch
Linear
Amplifier
Overload
Transistor Bias Circuits
Objectives
 Discuss the concept of dc biasing of a transistor for
linear operation
 Analyze voltage-divider bias, base bias, and collectorfeedback bias circuits.
 Basic troubleshooting for transistor bias circuits
Introduction
For the transistor to properly operate it must be biased.
Several methods to establish the DC operating point.
We will discuss some of the methods used for biasing
transistors as well as troubleshooting methods used for
transistor bias circuits.
Common Emitter Configuration
Ie
Vcc
Ic
Output
E
C
Rb1
B
Rc
_
+
Ib
_
+
Output
Vee
Input
Rb2
Input Vcc
•The circuit has been re-configured with
input at Base & output at Collector
Re
• The Emitter is common to input & output
•This is called Common Emitter
configuration
Input Characteristics
Output Characteristics
Beta () or amplification factor
• The ratio of dc collector current (IC) to the dc base
current (IB) is dc beta (dc ) which is dc current
gain.
• where IC and IB are determined at a particular
operating point, Q-point (quiescent point).
Common Base Configuration
Ie
E
Ic
-- ----- -- ----
-- -- --------------- - -- --
C
B
Input
_
+
Vbe
_
Ib
+
Output
Vcb
•Here the input is applied at the Emitter & the output taken
from the Collector
•In this arrangement Base is common to the input & output
•This is called Common Base configuration
Common Base
Common Base Configuration
• In the dc mode the level of IC and IE due to the majority
carriers are related by a quantity called alpha
=
IC
IE
IC = IE + ICBO
  IC
IE
• It can then be summarize to IC = IE (ignore ICBO due to small value)
Common Base Configuration
• Alpha a common base current gain factor that shows
the efficiency by calculating the current percent
from current flow from emitter to collector.
• The value of  is typical from 0.9 ~ 0.998.
Common – Collector Configuration
• Also called emitter-follower (EF).
• It is called common-emitter configuration since
both the signal source and the load share the
collector terminal as a common connection point.
Common – Collector Configuration
• The output voltage is obtained at emitter terminal.
• The input characteristic of common-collector
configuration is similar with common-emitter.
configuration.
Common Collector characteristics
Output characteristics of CC
configuration
Operating Regions
E–B
junction
Reverse
Biased
C–B
junction
Reverse
Biased
Active
Forward
Biased
Reverse
Biased
Saturation
Forward
Biased
Forward
Biased
Region of
operation
Cut off
Ic
Saturation
Region
Active Region
Ib = 60μA
Ic = 10mA
Ib = 50μA
Ic = 8mA
Ib = 40μA
Ic = 6mA
Ib = 30μA
Ic = 4mA
Ib = 20μA
Ic = 2mA
Cut-off Region
0V
24 V
Vce
Transistor as an amplifier
Simulation of transistor as an amplifier
The DC Operating Point
The goal of amplification in most cases is to
increase the amplitude of an ac signal without
altering it.
The DC Operating Point
• For a transistor circuit to amplify it must be
properly biased with dc voltages.
• The dc operating point between saturation and
cutoff is called the Q-point.
• The goal is to set the Q-point such that that it does
not go into saturation or cutoff when an a ac signal
is applied.
Q-Point (Static Operation Point)
• When a transistor does not have an ac input, it
will have specific dc values of IC and VCE.
• These values correspond to a specific point on the
dc load line. This point is called the Q-point.
• The letter Q corresponds to the word (Latent)
quiescent, meaning at rest.
• A quiescent amplifier is one that has no ac signal
applied and therefore has constant dc values of IC
and VCE.
DC Biasing Circuits
•
The ac operation of an
amplifier depends on the initial
dc values of IB, IC, and VCE.
•
By varying IB around an initial
dc value, IC and VCE are made
to vary around their initial dc
values.
•
DC biasing is a static operation
since it deals with setting av in
fixed (steady) level of current
(through the device) with a
desired fixed voltage drop
across the device.
+VCC
RC
RB
v out
ib
vce
ic
The DC Operating Point
The goal is to set the Q-point such that that it does not
go into saturation or cutoff when an a ac signal is
applied.
Collector characteristic curves
The collector
characteristic curves
graphically show the
relationship of collector
current and VCE for
different base currents.
The DC Operating Point
With the dc load line superimposed across the collector curves
for this particular transistor we see that 30 mA of collector
current is best for maximum amplification, giving equal amount
above and below the Q-point.
VCC
1
Ic  (
)VCE 
Rc
RC
The DC Operating Point-contd…
Effect of a superimposed ac voltage has on the circuit.
The collector current swings do not exceed the limits of operation(saturation
and cutoff).
Applying too much ac voltage to the base would result in driving the collector
current into saturation or cutoff resulting in a distorted or clipped waveform.
Voltage swing
• Both AC and DC load lines are shown as drawn
on the collector characteristics of an NPN
transistor.
• Note that both of the lines have to pass through
the operating point, Q.
Voltage swing-contd…
• AC load line defines the range the collector
current and voltage swings that can take place
around the operating point.
• The range limited on by the saturation region of
the transistor characteristics and on the right by its
cut-off point.
Voltage swing-contd…
• If the swings ten exceed these limits, the
waveform is clipped, creating severe distortion in
the amplified signal. The undisto (unclipped)
voltage swing is restricted to ∆vMAX+ and
∆vMAX+ around the operating point
Voltage swing-contd…
Voltage-Divider Bias
Voltage-divider bias is the most
widely used type of bias circuit.
voltage-divider bias is more stable(
independent) than other bias types.
Voltage-Divider Bias-contd…
R1 and R2 are used to provide
the needed voltage to point
A(base).
The voltage at point A of
the circuit in two ways,
with or without the input
resistance(point
A
to
ground) considered.
Voltage-Divider Bias-contd…
Voltage-Divider Bias-contd…
•The voltage across R2(VB) by
the proportional method.
VB = (R2/R1 + R2)VCC
 R 2 ||  DC RE 
VCC
VB  
 R1  ( R2 ||  DC RE ) 
Voltage-Divider Bias-contd…
Base voltage and subtract VBE to find out
what is dropped across RE ,determine the
current in the collector-emitter side of the
circuit.
The current in the base-emitter circuit is
much smaller, IE≈ IC
Base Bias
This type of circuit is very unstable since its  changes with
temperature and collector current. Base biasing circuits are
mainly limited to switching applications.
VCC  VBE
IC  (
)  DC
RB
Collector-Feedback Bias
Collector-feedback bias is kept
stable with
negative feedback,
although it is not as stable as
voltage-divider or emitter.
With increases of IC, less voltage is
applied to the base.
With less IB ,IC comes down as well..
•IB = (VC - VBE)/RB
•IC = (VCC - VBE)/(RC + RB/DC)
Vcc
Base Bias
Vc = Vcc – (Ic + Ib) x Rc
Also, Vc = (Ib x Rb) + Vbe
Rc
Equating the two equations
Vcc – (Ic + Ib)Rc
= (Ib Rb) + Vbe
Or, Ib(Rc + Rb) = Vcc – IcRc - Vbe
As Ic = Ib
Ib
Vcc – IcRc - Vbe
.
. .
Ic+Ib
Ib =
Rc + Rb
( Vcc – IcRc – Vbe)
Ic =
Rc + Rb
Rb
Ic
Vce
Disadvantages of fixed bias circuit
• Ic increases with temperature & there is no control
over it
• Hence there is poor thermal stability Ic =  Ib
• Hence Ic depends on 
•  may change from transistor to transistor
• This will shift the operating point
• Hence stabilization is very poor in fixed bias
circuit
Advantages of fixed bias circuit
• Simple circuit with minimum components
• Operating point can be fixed conveniently in the
active region, by selecting appropriate value for
Rb
• Hence fixed bias circuit provides flexibility in the
design
Emitter Bias
•This type of circuit is independent
of  making it as stable as the
voltage-divider
type.
The
drawback is that it requires two
power supplies.
•IB ≈ IE/
•IC ≈ IE ≈( -VEE-VBE)/(RE + RB/DC)
Summary
 The purpose of biasing is to establish a stable
operating point (Q-point).
 The Q-point is the best point for operation of a
transistor for a given collector current.
 The dc load line helps to establish the Q-point
for a given collector current.
 The linear region of a transistor is the region of
operation within saturation and cutoff.
Stability Factor
Stability
• Temperature & Current gain variation may change
the Q point
• Stability refers to the design that prevents any
change in the Q point
• Temperature effect
• When the temperature increases it results in the
production of more charge carriers
• This increases the forward bias of the transistor
and Ib increases
Temperature effect
• When the temperature increases it results in the production
of more charge carriers
• This increases the minority charge carrier and hence the
leakage current as
Iceo = (+1) Icbo
• Icbo doubles for every 100 C
As Ic =  Ib + Icbo
• The increase in the temperature increases Ic
• This in turn increases the power dissipation and again
more heat is produced
Stability Factor
• It indicates the degree of change in the operating
point due to variation in temperature
• There are 3 stability factors corresponding to the 3
variables – Ico, Vbe & 
S =
S’ =
S’’ =
Ic
Ico
Vbe,  constant
Ic
Vbe
Ico,  constant
Ic

Ico, Vbe constant
The stability factor should
be as minimum as possible
Techniques
• Stabilization technique
• Resistive biasing circuits change Ib suitably and
keep Ic constant
• Compensation technique
• Temperature sensitive devices such as diodes,
thermistors & transistors are used to provide
suitable compensation and retain the operating
point without shifting
Stability Factor S
For Fixed Bias Circuit
Ic
S = Ico
Vbe,  constant
(I+)
=
Ib
1- 
Ic
For the fixed Bias Circuit Ib = Vcc / Rb
.
. .
Ib
=0
Ic
(I+)
.
. .
S=
1 - (0)
.
. .
S=1+
Stability Factor S’
For Fixed Bias Circuit
Ic =  Ib + Iceo
S’ =
=  Ib + ( + 1) Icbo
Vcc - Vbe
= 
+ ( + 1) Icbo
Rb
 Vcc
 Vbe
+ ( + 1) Icbo
=
Rb
Rb
.
. .
.
. .
Ib
Vbe
= 0 _

+ 0
Rb
S = -  / Rb
Ic
Vbe Ico,  constant
Stability Factor S’’
For Fixed Bias Circuit
Ic = Ib + Iceo
S’’ =
= Ib + (+1)Icbo
Ic

Vcc - Vbe
= 
+ ( + 1) Icbo
Rb
 Vcc
 Vbe
+ ( + 1) Icbo
=
Rb
Rb
.
. .
Ic

Vcc
=
Rb
Vbe
Rb
= Ib + Icbo
= Ib (approx)
= Ic / 
.
. .
S’’ = Ic / 
+ Icbo
Ico, Vbe constant
Stability Factor S’
For Collector-Base Bias
Vcc – IcRc - Vbe
Ic
Vbe Ico,  constant
S’ =
Ib =
Rc + Rb
Vcc – IcRc - Vbe
Ic

Ic
Rb + ( + 1) Rc
Rc + Rb
Ic

Ic =
=
IcRc
+
Vcc - Vbe
=
Rc + Rb
Rc + Rb + Rc
 (Rc + Rb)
(Vcc – Vbe)
Rc + Rb
Vcc - Vbe
=
Rc + Rb
S’ =
=
Ic
Vbe
-
Rb + ( + 1) Rc
Stability Factor S’’
For Collector-Base Bias
S’’ =
Ic

Ico, Vbe constant
Vcc = (Ib + Ic)Rc + IbRb + Vbe
Vcc –Vbe = (Ib + Ic)Rc + IbRb
= Ib [(1 + )Rc +Rb]
Vcc – Vbe
.
. .
Ib =
( Vcc – Vbe)
.
. .
(1 + ) Rc + Rb
Ic =
(1 + ) Rc + Rb
[(1 + )Rc +Rb](Vcc –Vbe) - (Vcc –Vbe) Rc
Ic
.
. .

=
[(1 + ) Rc + Rb]2
(Vcc –Vbe)[(1 + )Rc +Rb] - Rc
=
[(1 + ) Rc + Rb]2
(Vcc –Vbe)(Rc +Rb)
=
[(1 + ) Rc + Rb]2
Vcc – Vbe
=
(1 + ) Rc + Rb
Rc + Rb
x
(1 + ) Rc + Rb
Ib(Rc + Rb)
=
.
. .
S’’ =
(1 + ) Rc + Rb
Ic(Rc + Rb)
[(1 + ) Rc + Rb]
S’’ =
Ic(Rc + Rb)
[(1 + ) Rc + Rb]
Ic 1+ 
=
=
=
(Rc + Rb)

1+ 
(1 + ) Rc + Rb
Ic
1
(1+ ) (Rc + Rb)

1+ 
(1 + ) Rc + Rb
Ic
S

1+ 
If S is small, S’’ will also be small
Hence if we provide stability against Ico variations, it will take care
of  variation as well
Stability Factor S
For Voltage Divider Bias
S =
Vb = IbRb +Vbe + IeRe
= IbRb +Vbe + (Ib + Ic)Re
Ic
Ico Vbe,  constant
where Rb = Rb1 ll Rb2
Differentiating,
0 = IbRb + 0 + IbRe + IcRe
i.e. Ib(Rb + Re) = - IcRe
.
. .
Ib
Ic
=
-Re
Rb + Re
(I + )
(I + )
S=
Ib
1-
Ic
=
1+
Re
Re + Rb
(I + )
S=
1+
Re
Re + Rb
• In the above equation, if Rb << Re, then S
becomes 1
Rb = Rb1 ll Rb2
• Hence either Rb1 or Rb2 must be << Re
• Since Vb << Vcc, Rb2 is kept small wrt Rb1
(I + )
S=
1+
Re
Re + Rb
(I + )
S=
1+
1
S = (I + )
1 + Rb/Re
• Re cannot be increased beyond a limit, as it will
affect Ic and hence the Q point
• If Rb-Re ratio is fixed, and if Rb >> Re, S increases
with 
• Thus stability decreases with increasing 
(I + )
S=
1+
Re
Re + Rb
(I + )
S=
1+
1
S= I
1 + Rb/Re
• If Rb << Re, then S becomes independent of 
• Stability factor S for Voltage Divider circuit is less
compared to other circuits
• Hence it is preferred over other circuits
Stability Factor S’
For Voltage Divider Bias
Vb = IbRb +Vbe + IeRe
= IbRb + Vbe + (Ib + Ic)Re
S’ =
Ic
Vbe Ico,  constant
= Ib(Rb + Re) + Vbe + IcRe
= Ic /  (Rb +Re) + Vbe + IcRe
Or, Vb = Ic(Rb +Re) +  Vbe +  IcRe
= Ic[Rb +( + 1)Re] +  Vbe
0 = Ic[Rb +( + 1)Re] + Vbe
Or, Vbe = - Ic [Rb +( + 1)Re]
Ic
S’ =
=
Vbe
-
Rb + ( + 1) Re
Differentiating,
Stability Factor S’’
For Voltage Divider Bias
Vb = IbRb +Vbe + IeRe
S’’ =
= Ib(Rb + Re) + Vbe + IcRe
Ic

Ico, Vbe constant
= Ic /  (Rb +Re) + Vbe + IcRe
Or, Vb = Ic(Rb +Re) +  Vbe +  IcRe
Or, (Vb – Vbe) = Ic(Rb +Re) +  IcRe
Differentiating,
(Vb – Vbe) = Ic(Rb +Re) + IcRe + Ic Re
(Vb – Vbe – IcRe) = Ic[Rb + Re+ Re]
.
. . S’’ =
Ic

=
Vb – Vbe - IcRe
Rb + Re(1+ )
S’’ =
Ic

=
=
=
=
Vb – Vbe - IcRe
Rb + Re(1+ )
Vb – Vbe - IeRe
Rb + Re(1+ )
As Ie = Ic
Ib Rb
Rb + Re(1+ )
Ib
1 +(Re/Rb)(1+ )
Hence Rb / Re must be small to make S’’ smaller
Bias Compensation
• The biasing circuits seen so far provide stability of
operating point for any change in Ico, Vbe or 
• The collector- base bias & emitter bias circuits
provide negative feedback & make the circuit
stable, but the gain falls down
• In such cases it is necessary to use compensation
techniques
• Diode Compensation
Technique
Vcc
Here diode D has been connected
as shown
It is given forward bias through
Vdd
Rb
Rc
270 K
5.6 K
The diode D is identical to the BE
junction of the transistor
The charge carriers will increase
in the BE jn. due to temperature or
other variations
Rd
-
Vdd
+
Re
D
Vcc
Since diode D has similar
properties, its charge carrier also
increases, for any change in the
parameters
Rb
Rc
270 K
5.6 K
Thus the increase in current in
the BE junction is compensated
by the current flow through the
diode in the reverse direction.
Rd
-
Vdd
+
Re
D
Vcc
Another technique
Here the diode D has been
connected in the bleeder path
When there is increase in
current in the BE junction due to
parameter changes, current
through D also increases by the
same amount
Ib1
Rb1
270 K
Ib2
Rc
5.6 K
D
Rb2
Re
Vcc
This increases Ib1, produces more
drop across Rb1& reduces Vb
As Vb decreases, Ib falls down
Rb1
Rc
270 K
5.6 K
Thus the transistor currents are
arrested and not allowed to increase
Thus diode D provides suitable
compensation
D
Rb2
Re
Thermistor Compensation
Here a Negative Temperature
Coefficient Resistor has been used
Vcc
Ib1
Rb1
Rc
270 K
5.6 K
As temperature increases, its
resistance decreases
This increases Ib1 & voltage drop
across Rb1
This decreases Vb and hence Ib &
Ic, thus keeping the circuit stable.
Ib
Ib2
NTC
Re
Vcc
Constant Current circuit
Rb1
Rc

Re provides self bias

Vb is fixed depending on
the ratio of Rb1 & Rb2 &
the value of Vcc

Ve = Vb - Vbe

Vbe is fixed for a transistor

Hence Ve is fixed &

Ie = Ve / Re is also fixed

Hence it acts as a constant
current circuit
5.6 K
Rb2
Re
Problem
 For the given Si transistor
find the constant current I
Rb1
I
270 K
5.6 K
Answer
 I = 4.22 mA
Rb2
4K7
Re
2K2
-20 V
FET Biasing
Introduction
• For the JFET, the relationship between input and
output quantities is nonlinear due to the squared term
in Shockley’s equation.
• Nonlinear functions results in curves as obtained for
transfer characteristic of a JFET.
• Graphical approach will be used to examine the dc
analysis for FET because it is most popularly used
rather than mathematical approach
• The input of BJT and FET controlling variables are
the current and the voltage levels respectively
Introduction -contd…
JFETs differ from BJTs:
• Nonlinear relationship between input (VGS) and
output (ID)
• JFETs are voltage controlled devices, whereas
BJTs are current controlled
FET Biasing
Common FET Biasing Circuits
• JFET
– Fixed – Bias
– Self-Bias
– Voltage-Divider Bias
• Depletion-Type MOSFET
– Self-Bias
– Voltage-Divider Bias
• Enhancement-Type MOSFET
– Feedback Configuration
– Voltage-Divider Bias
General Relationships
• For all FETs:
IG  0A
ID  IS
• For JFETs and Depletion-Type MOSFETs:
ID  IDSS(1
VGS 2
)
VP
• For Enhancement-Type MOSFETs:
I D  k (VGS VT ) 2
Fixed-Bias Configuration
• The configuration includes the ac levels Vi and Vo and the
coupling capacitors.
• The resistor is present to ensure that Vi appears at the input to
the FET amplifier for the AC analysis.
Fixed-Bias Configuration-contd…
Investigating the input loop
• IG=0A, therefore
VRG=IGRG=0V
• Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
• It is called fixed-bias configuration due to VGG is a
fixed power supply so VGS is fixed
• The resulting current, ID  IDSS(1 VGS )2
VP
Fixed-Bias Configuration(Graphical approach)
• Investigating the graphical approach.
• Using below tables, we can draw the graph
Self Bias Configuration
• The self-bias configuration eliminates the need for two dc
supplies.
• The controlling VGS is now determined by the voltage across
the resistor RS
Self Bias Configuration-contd…
• For the indicated input loop:
VGS   I D RS
• Mathematical approach:
ID
ID

VGS
 I DSS 1 
VP





I R
 I DSS 1  D S
VP

2



2
Graphical approach
– Draw the device transfer characteristic
– Draw the network load line
• First point, VGS   I D RS
• Second point, any point from ID = 0 to ID = IDSS. Choose
I D  0, VGS  0
I DSS
then
2
I R
  DSS S
2
ID 
VGS
– the quiescent point obtained at the intersection of the
straight line plot and the device characteristic curve.
– The quiescent value for ID and VGS can then be determined
and used to find the other quantities of interest.
Graphical approach
Self Bias
• For output loop
– Apply KVL of output loop
– Use ID = IS
VDS  VDD  I D ( RS  RD )
VS  I D RS
VD  VDS VS  VDD VRD
Voltage-Divider Bias
• The arrangement is the same as BJT but the DC
analysis is different
• In BJT, IB provide link to input and output circuit, in
FET VGS does the same
Voltage-Divider Bias
• The source VDD was separated into two equivalent sources to
permit a further separation of the input and output regions of the
network.
• IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the
series equivalent circuit appearing to the left of the figure can be
used to find the level of VG.
Voltage-Divider Bias
• VG can be found using the voltage divider rule :
R2VDD
VG 
R1  R 2
• Using Kirchoff’s Law on the input loop:
• Rearranging and using ID =IS:
VG VGS VRS  0
VGS  VG  I D RS
• Again the Q point needs to be established by plotting a
line that intersects the transfer curve.
Procedures for plotting
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0,
ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the
circuit.
Voltage Divider Bias
• Once the quiescent values of IDQ and VGSQ are
determined, the remaining network analysis can be
found.
I R1  I R 2
• Output loop:
VDD

R1  R2
VDS  VDD  I D ( RD  I D RS )
VD  VDD  I D RD
VS  I D RS
Effect of increasing values of RS
Depletion-Type MOSFETs
•Depletion-type MOSFET bias circuits are similar to JFETs. The
only difference is that the depletion-Type MOSFETs can operate
with positive values of VGS and with ID values that exceed IDSS.
•Analyzing the MOSFET circuit for DC
analysis
How to analyze dc analysis for
the shown network?





It is a Type network
Find VG or VGS
Draw the linear characteristics
Draw the transfer
characteristics
Obtain VGSQ and IDQ from the
graph intersection
Depletion type MOSFET
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values
of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the
voltage-divider bias circuit. These are the same calculations as used
by a JFET circuit.
Q-Point- Enhancement MOSFET
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values
of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the
voltage-divider bias circuit. These are the same calculations as used
by a JFET circuit.
Enhancement-Type MOSFET
•The transfer characteristic for the enhancement-type MOSFET is
very different from that of a simple JFET or the depletion-type
MOSFET.
Enhancement MOSFET
• Transfer characteristic for E-MOSFET
I D  k (VGS  VGS (Th ) )
k
I D ( on)
(VGS ( on)  VGS (Th ) ) 2
2
Feedback Biasing Arrangement
• IG =0A, therefore VRG = 0V
•Therefore:
•Which makes
VDS = VGS
VGS  VDD  I D RD
Feedback Biasing Q-Point
1. Plot the line using VGS = VDD, ID = 0 and ID = VDD / RD and VGS
=0
2. Plot the transfer curve using VGSTh , ID = 0 and VGS(on), ID(on); all
given in the specification sheet.
3. Where the line and the transfer curve intersect is the Q-Point.
4. Using the value of ID at the Q-point, solve for the other variables
in the bias circuit.
DC analysis step for Feedback Biasing
Enhancement type MOSFET





Find k using the datasheet or specification given;
ex: VGS(ON),VGS(TH)
Plot transfer characteristics using the formula
ID=k(VGS – VT)2. Three point already defined that is
ID(ON), VGS(ON) and VGS(TH)
Plot a point that is slightly greater than VGS
Plot the linear characteristics (network bias line)
The intersection defines the Q-point
Voltage-Divider Biasing
Again plot the line and the transfer curve to find the Q-point.
Using the following equations: VG  R2VDD
R1  R2
Input loop : VGS VG  I D RS
Output loop: VDS VDD  I D ( RS  RD )
Voltage-Divider Bias Q-Point
1. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID
= VG/RS and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS(on), ID(on); all
given in the specification sheet.
4. Where the line and the transfer curve intersect is the Q-Point.
5. Using the value of ID at the Q-point, solve for the other variables
in the bias circuit.
Troubleshooting
N-channel VGSQ will be 0V or negative if
properly checked
 Level of VDS is ranging from 25%~75% of VDD.
If 0V indicated, there’s problem
 Check with the calculation between each terminal
and ground. There must be a reading, RG will be
excluded

P-Channel FETs
For p-channel FETs the same calculations and graphs are used,
except that the voltage polarities and current directions are the
opposite. The graphs will be mirrors of the n-channel graphs.
Practical Applications
• Voltage-Controlled Resistor
• JFET Voltmeter
• Timer Network
• Fiber Optic Circuitry
• MOSFET Relay Driver