Download 2 The TTL Inverter

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2.1
The TTL Inverter
Circuit Structure
The circuit diagram of the Transistor Transistor Logic inverter is shown
in Fig. 2.1. This circuit overcomes the limitations of the single
transistor inverter circuit. Some of the notable features of the circuit
structure of the TTL Logic family are as follows:
(i) An input transistor, T1, which performs a current steering function,
can be thought of as a back-to-back diode arrangement.
VCC

RB
RB
T1
Fig. 2.2
Equivalent of Input Current-Steering Transistor
The transistor can operate in either forward or reverse mode to
steer current to or from T2 . Since it has a forward current gain, it
provides a higher discharge current to discharge the base of T2
when turning it off.
(ii) The output transistor pair, T3 and T4 shown in Fig. 2.3 and referred
to as a totem-pole output, can actively source or sink current to or
from capacitive loads and allows the output voltage to be defined
independently of the load connected to the gate. Resistor, R 3 ,
serves to limit current. Under steady-state conditions, only one
transistor is ON at a time.
T4 OFF
RL
T4 ON
T3 OFF
T3 ON
RL
Fig. 2.3 Output Current Driving Transistors
1
R3
130
R1
1.6k
RB
4k
T4
Input
T2
T1
Output
T3
Vi
VO
A
T1 SAT
T2 OFF
T3 OFF
T4 ON
B
4
3
VOH MIN
VO
R2
1k
C
(2.86V)
T1 SAT
T2 ON
T3 OFF
T4 ON
T1 SAT
T2 ON
T3 ON
T4 ONOFF
2
1
T1 SATREV ON
T2 SAT
T3 SAT
T4 OFF
D
VOL MAX
E
(0.2V)
0
0.5V
1
2
VIL MAX
VIH MIN
(1.2V)
(1.4V)
3
4
Vi
5
Fig. 2.1 Circuit Diagram & Transfer Characteristic of a TTL Inverter
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(iii) The diode, D, serves to increase the effective VBE of T4 which
allows T4 to be turned OFF before T3 turns ON fully. This prevents
large surge currents from flowing when both transistors conduct
during transitions between logic states. The disadvantage is that
the high logic voltage is reduced by an amount of the diode drop
as shown in Fig. 2.4.
T4
D
T3
Fig. 2.4
VO
Use of Diode in Totem-Pole Output
(iii) Finally, T2 is a “phase splitter” driving transistor to drive the
output stage. It allows the logic condition to be phase-splitted
in opposite directions so that the output transistors can be
driven in anti-phase. This allows T3 to be ON when T4 is OFF
and vice versa as shown in Fig. 2.5.
RC
Vi  LO T2 OFF VO1  HI VO 2  LO
VO1
T2
Vi  HI T2 ON
VO1  LO VO 2  HI
VO2
RE
Figure 2.5 The Phase Splitting Stage
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2.2
Logical Operation
The logical functioning of the circuit can be established by determining
the state of conduction of each transistor in turn from input to output
for all possible combinations of input states. Transistors can be taken
as either ON or OFF. Note that the input transistor, T1, may conduct in
either forward or reverse mode. Drawing up a table of conduction
states accordingly with reference to Fig. 2.1 gives:
INPUT
T1
T2
T3
T4
D
OUPUT
LO
ONFOR
OFF
OFF
ONCUT-IN
ONCUT-IN
HI
HI
ONREV
ON
ON
OFF
OFF
LO
LO in action
2.3
HI out
and
HI in
-
LO out
 This is logic inverter
Transfer Characteristic
The transfer characteristic can be deduced by applying a slowly
increasing input voltage and determining the sequence of events
which takes place with regard to changes in the states of conduction of
each transistor and the critical points at which the onset of these
changes occur. Consider the circuit and transfer characteristic of Fig.
2.1.
Point A
With the input LO and the base current supplied to T1, this transistor
can conduct in the forward mode. Since the only source of collector
current is the leakage of T2 then T1 is driven into saturation. This
ensures that T2 is OFF which, in turn, means that T3 is OFF. While there
is no load present, there are leakage currents flowing in the output
stage which allow the transistor T4 and the diode D to be barely
conducting at the point of cut-in.
VO  VCC  VBE 4 CUTIN  VD CUTIN
VO  5  0.6  0.4  4V
Point A : Vi  0V, VO  4V
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Point B
As the input voltage is slowly increased, the above condition prevails
until, with T1 ON in saturation, the voltage at the base of T2 rises to
reach the point of conduction. Then:
Vi  VBE 2 CUTIN  VCE 1 SAT  0.6  0.1  0.5V
Point B : Vi  0.5V
VO  4V
Point C
As the input voltage is further increased, T2 becomes more conducting,
turning fully ON. Base current to T2 is supplied by the forward biased
base-collector junction of T1 which is still in saturation (i.e both
junctions of T1 are forward biased). Eventually, T3 reaches the point of
conduction. This happens when:
Vi  VBE 2 ON  VBE 3 CUTIN  VCE 1 SAT
Vi  0.7  0.6  0.1  1.2V
Note that with transistor T3 at cut-in, VBE 3 = 0.6V which means that
the current through R2 is 0.6V/1k = 0.6mA. With operation in the
linear active region, the collector current in T2 is F IE2  0.97  0.6 =
0.58mA. The voltage drop across R1 is then VR1 = 0.58mA  1.6 k =
0.94V. Under this condition the voltage drop across T2 is:
VCE 2  VCC  VR1  VR2
VCE 2  5  0.94  0.6  3.46V
This confirms that T2 is still operating in the forward active mode.
With T3 beginning to conduct there is a conduction path for current
through T4 and the diode, D, which then turns fully ON. In this case:
VO  VCC  VR1  VBE 4 ON  VD ON
VO  5  0.94  0.7  0.5  2.86V
Point C :
Vi  1.2V
5
VO  2.86V
Point D
As the input voltage is further increased, T2 conducts more heavily,
eventually saturating. T3 also conducts more heavily and eventually
reaches the point of saturation. As T2 becomes more conducting, its
collector current increases. This in turn increases the voltage drop
across R1 which in turn means that the voltage across T2, i.e. VCE2,
decreases. This falls below the requirement for conduction in T4 and
the diode, D, so that both of these turn OFF prior to the saturation of
T3.
When T3 reaches the edge of saturation:
Vi  VBE 2 SAT  VBE 3 ON  VCE 1 SAT
Vi  0.8  0.7  0.1  1.4V
VO  VCE 3 SAT  0.2V
Point D : Vi  1.4V,
VO  0.2V
2.4 Noise Margins
Using points C and D on the transfer characteristic in Fig. 2.1 to
identify the critical points, we have:
ViL MAX  1.2V
VOL MAX  0.2V
NML  1.0V
ViHMIN  1.4V
VOHMIN  2.8V
NMH  1.4V
The manufacturer’s specification guarantees:
ViL MAX  0.8V
VOL MAX  0.4V
NML  0.4V
ViHMIN  2.0V
VOHMIN  2.4V
NMH  0.4V
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