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Memory models and computer architectures: We will describe several architectures that have been developed to allow more than one program to share memory, and discuss the problems of memory management in each. Architecture I: Basic von Neumann architecture. Represented most recently by 8-bit microcomputers. Outline for Lecture 15 I. Architecture I. Unprotected address space II. Architecture II. Partitions within main memory Swapping III. Architecture III Two segments/process IV. Architecture IV • The address space is of fixed size; no address translation. (Logical address = physical address.) Segmented v.m. Addressing Address translation Hence, any process can write anywhere in physical memory. • May have index registers, which implement the simplest kind of address modification. They are needed for addressing array elements. An indexed address is a pair (i , x), where i denotes an index register and x denotes the displacement. Then Physical address = (contents of index register i ) + x Problems not solved by the basic von Neumann architecture: • Size of operating system. When the size of the OS changes, all programs may have to be recompiled. • Size of address space. Programs cannot be larger than physical memory, since there is no way to generate an address larger than the maximum physical address. Lecture 15 Operating System Principles Page 145 • Protection. A program can write anywhere in physical memory. • Sharing of code. Two users are running the same code “simultaneously.” How are they to be kept from overwriting each other’s data? The first of these problems can be solved by partitioning main memory into several regions. Architecture II: Partitions within main memory. Each program runs within a partition of memory. In the simplest case, there are just two partitions, one containing the OS, and the other containing a single user program. Usually the OS is at the low end of memory, because that is where the interrupt vector is. In a more general case, there can be more than one user program. Each program has associated with it a single base-length register pair. The example below shows three programs occupying main memory. © 1998 Edward F. Gehringer CSC/ECE 501 Lecture Notes Page 146 0 0 Process 1 15000 40000 Process 1 0 55000 Process 2 30000 0 Process 3 70000 Process 3 105000 35000 Three Addresslogical mapping address function spaces Process 2 135000 One physical address space Typically, the contents of the base register are added to each logical address. (Note: The base register is loaded by the operating system.) Q R base register length register Physical address = contents of Q + contents of index register +x If the logical address is greater than the contents of the length register, it is an error, and the requested memory access is not performed. if contents of index register + x ≥ contents of R then error. Hence this architecture provides protection between processes. Lecture 15 Operating System Principles Page 147 From now on, we will “forget about” index registers in giving memory-mapping functions; they always take part in the computation of a logical address, but for simplicity, we omit the details. Architecture II still has these limitations: • It is still impossible to share programs or data. • It is still impossible to protect one module of a program from another. • Though many programs can fit in physical memory at once, no single program can be larger than physical memory. Swapping (S&G, §8.3): In a multitasking system, several processes may be resident simultaneously in main memory. • The processor “takes turns” working on each one. • But some processes may be idle for a “long time” (if, e.g., the user walks away from his terminal). Such processes “waste space” in memory that could better be used by other processes. So the solution is to swap out the idle processes to secondary storage. Swapping of processes is very similar to swapping of segments in virtual memory, and we will treat it in more detail later. But three special aspects of process swapping should be noted. • Can a process be swapped out while waiting for input/output? • Can swapping be done if the program has been relocated by a loader instead of by base-length registers? © 1998 Edward F. Gehringer CSC/ECE 501 Lecture Notes Page 148 • Suppose a process is only using part of the physical memory that is allocated to it. How can swapping be made more efficient? Nowadays, process swapping is used mainly on PCs. • In Microsoft Windows, when a new process is loaded and there is not enough memory, an old process is swapped to disk. The user decides when to bring it back. • Windows/NT, however, supports paging. Physical memory can be managed like a single large array, using any appropriate memory-management strategy (a few of which we will consider later). Architecture III: Two segments per process. Same as Architecture II, except for a hack to allow sharing: Each process is given two base-length registers, (Q0, R0) and (Q1, R1). • The first register points to a non-sharable partition into which the program may write. • The second register points to a sharable partition that contains code and (sometimes) read-only data. • A bit in the address Lecture 15 Q0 R0 Data Q1 R1 Code Operating System Principles Page 149 field of each operand can select which partition is to be used for each reference. Still, programs can’t be larger than main memory. Example: The DEC-10 kept code and read-only data in “high” memory— if the leading bit of an address was 1, the contents of Q1 (in the diagram above) were added to the logical address to find the physical address. If the leading bit of an address was 0, it referred to non-sharable “low” memory, where read/write data is kept. Example: The Univac 1108 had a similar scheme, but did not allow read-only data to be kept with code. Instruction references referred automatically to memory in the sharable region; data references referred automatically to memory in the non-sharable region. Thus the Univac 1108 did not need an extra bit in each address. Architecture IV: Segmented virtual memory. To run programs which are larger than physical memory, there must be some way of arranging to have only part of a program in memory at one time. Any operating system which allows a program to be larger than physical memory is called a virtual-memory system, because it allows a program to “use” primary memory which is not physically present. To achieve virtual memory, we generalize Architecture III to allow more than one sharable and/or non-sharable segment. • It is possible for a process to share portions of its code (e. g., I/O routines) and its data (e. g., databases) without sharing all code or all data. • The segments can now be swapped independently; not all need to be in memory at once. © 1998 Edward F. Gehringer CSC/ECE 501 Lecture Notes Page 150 • Since swapping of segments is now independent of swapping of programs, the question of when to swap something or other becomes more complicated. • With more entities being swapped, memory fragmentation becomes more serious. Swapping rules: • Read-only segments need not be copied out to secondary storage. • Segments which have not been written into since being swapped in need not be swapped out either. • Uninitialized segments need not be swapped in. Addressing in segmented memory: A logical address is of the form (s, d ), where s is the segment number and d is the displacement. s d The number of segments may be large; hence there are no “segment registers,” but rather a segment table. The segment table contains segment descriptors, each of which hold— • a base address (physical address of first word or byte), • a length field (giving length in bytes or words), and • an access-rights field (read, write, and perhaps execute ). Here is a diagram of addressing using a segment table. Lecture 15 Operating System Principles Page 151 Segment-table base register Logical address s b d Add > Compare s Physical address Add b l r Segment table for current process Address translation: The naïve method would be to consult the segment table each time a memory reference is to be performed. Instead, some form of content-addressable, or associative memory is usually used. • This memory is smaller than a segment table. Value v1 v2 … … • The input is compared Input against all keys simultaneously. If the input matches a key, then the corresponding value is output. Key k1 k2 kn vn Output Usually this memory is called a translation lookaside buffer, or TLB, because the processor “looks aside” to it as it is translating an address. The next page shows a diagram of address translation using a TLB. Each time the TLB is accessed, this procedure is followed: • If an entry matching the segment number is found, the length is checked, and the base address returned. © 1998 Edward F. Gehringer CSC/ECE 501 Lecture Notes Page 152 • If no matching entry is found, a victim entry is chosen from among the TLB slots. The victim is chosen to be an entry that is not very “active.” We will discuss what this means later. A TLB’s hit ratio is the number of entries found / the number of times searched. Segment-table base register b Logical address s d Add Try this first s b l r Only if match in TLB Translation-lookaside buffer (most active segments only) s b l Add r Segment table Physical address If no match in TLB for current process The TLB does not have to be very large to produce a good hit ratio. Early studies showed— • Burroughs B6700— 98% with 8 cells. • Multics— 98.75 with 16 cells. However, this was 20 years ago, when programs were much smaller. Today’s TLBs typically have from 128 to 2048 entries. Lecture 15 Operating System Principles Page 153 Let a be the time to search the TLB, m be the time to access main memory, and h be the hit ratio. Then the effective access time is h (a+m ) + (1–h )(a+2m ) = a + (2–h )m (This formula only applies in a one-level segment table.) Segment faults: When a segment is referenced, it may not be in main memory. Each segment descriptor contains a presence bit , which tells whether or not the segment is “present.” (For simplicity’s sake, the presence bit was not shown in the diagrams above.) If a segment is not in main memory when it is referenced, it must be swapped in. • This is called a segment fault. • Usually, it will necessitate swapping some other segment(s) out. • Thus the segment descriptor must also contain a secondary-storage address. How many fields does a segment descriptor contain altogether? © 1998 Edward F. Gehringer CSC/ECE 501 Lecture Notes Page 154