Download An Ideal Inverter Real Inverters

14
An Ideal Inverter
■
Real Inverters
Voltage transfer curve for an inverter -- it should yield 0 V when a high voltage is
input and the high voltage, V+, when a low voltage is input. An ideal inverter
would be very forgiving of imperfect input voltages ...
VIN >VM = V+/ 2 --> VOUT = 0 V
The inverters which we can build are approximations to the ideal inverter. A typical
inverter characteristic is:
VOUT
VMAX
VOH
VIN < VM = V+/ 2 --> VOUT = V+
Note that the ideal inverter returns correct logical outputs (0 V or V+) even when
the input voltage is corrupted by noise, voltage spikes, etc. that are nearly half
the supply voltage!
VOL
VMIN
0
VOUT
V+
V+
+
+
VIN
VOUT
−
−
VOUT = VIN
0
VIL
VM
VIH
V+
VIN
On the output and input axes, several voltages are defined:
VM = voltage midpoint where VOUT = VIN = VM.
V +/2
VOL = “voltage output low” = max. output voltage for a valid “0”
0
0
(a)
= −1
VM
VM =
V+
2
(b)
V+
VIN
VOH = “voltage output high” = min. output voltage for a valid “1”
VIL = “voltage input low” = smaller input voltage where slope equals -1
VIH = “voltage input high” = larger input voltage where slope equals -1
VMAX = VOUT for VIN = 0 V; usually, VMAX = V+, the supply voltage
VMIN = VOUT for VIN = V+ and is the minimum output voltage
EE 105 Fall 1998
Lecture 14
EE 105 Fall 1998
Lecture 14
Noise Margins
■
Inverter Circuits:
Digital electronic circuits consist of series of logic gates; the voltage signals are
contaminated by “noise” -- actually, mostly generated by capacitive coupling
from other parts of the circuit
■
NMOS-Resistor Pull-Up
First example: motivate the concept of a MOSFET switch enabling an
approximation to the inverter.
VDD
vNOISE
1
2
R
VOH1
NMH
VIH1
Voltage
VOH2
VIL1
VIH2
VIL2
VOL1
NML
VIN
VOL2
CL
+
VOUT
_
NMH = VOH − VIH
NML = VIL − VOL
■
■
Output of inverter #1 is at least VOH1 (assuming it had a valid low input
VIN1 < VIL1); therefore, there’s a margin of VOH1 - VIH2 to spare before the input
to inverter #2 has an invalid high input.
For the case of cascaded identical inverters, we define noise margins
NMH = VOH - VIH = noise margin (high)
VDD = 5 V (typically)
CL = load capacitance (from interconnections and from other inverters connected
to the output
VBS = 0 V -- bulk-to-source short-circuit is assumed to be present unless
indicated otherwise
NML = VIL - VOL = noise margin (low)
EE 105 Fall 1998
Lecture 14
EE 105 Fall 1998
Lecture 14
Finding the Voltage Transfer Curve
■
■
Voltage Transfer Curve using Load Line Technique
Approach 1: start with VIN = 0 and increase it; figure out the operating regions
for the MOSFET and substitute ID = ID (VGS, VDS) = ID(VIN, VOUT) and find
■
Graphical intersection of ID versus VOUT characteristics with load line
ID
V OUT = V DD – I D R
Approach 2: use a graphical technique
>> we know ID(VIN, VOUT) from the MOSFET’s drain characteristics
VIN
VDD
R
>> we can find another equation relating ID and VOUT from KVL --
VDD
VOUT = VDD - ID R
ID = (VDD - VOUT) / R
ID
VOUT
R
* Given µnCox = 50 µA/V2, (W/L) = 4.5/1.5 = 3, VTn = 1.0 V, and λn = 0
+
VOUT
V
_ DD
we don’t
care what
goes here!
VOUT
(V)
Inverter Characteristics
5.0
load line
R = 5 kΩ
R = 25 kΩ
4.0
3.0
2.0
1.0
■
Intersections between the family of drain characteristics and the load line yield
VOUT as a function of VIN
EE 105 Fall 1998
Lecture 14
0.0
0.0
1.0
2.0
3.0
4.0
5.0
VIN
(V)
EE 105 Fall 1998
Lecture 14
Improved Inverters
■
Small-Signal Model of Inverter
First try: quantify how increasing the resistor R affects the slope of the voltage
transfer curve at the midpoint (a measure of the steepness of the transition
region)
dv OUT
= Av
----------------dv IN
*Finding the small-signal circuit, neglecting capacitors:
R
replace with
small-signal
model
VM
From our small-signal modelling concepts, this slope is equal to the ratio of the
small-signal voltages vout and vin
v out
---------- = A v
v in
VM
short
+
V
_ DD
vOUT = VOUT + vout
CL
+
vin
_
+
VIN = VM
_
short
How to find vout / vin? Use the small-signal model!
----------------------------------------* No backgate effect generator included
since vbs = 0
Small-signal model of the battery VDD --> a short circuit!
Why?
vDD = VDD + vdd ... by definition, an ideal battery has
R
* gm and ro are evaluated at the bias point:
VGS = VM and the corresponding ID.
vDD = VDD which implies that vdd = 0.
+
g
vin
gmvgs
_
EE 105 Fall 1998
Lecture 14
vout
ro
s
EE 105 Fall 1998
Lecture 14
Small-Signal Analysis
■
Solving for the small-signal voltage gain -- the slope of the transfer curve at VIN
= VM :
v out
---------- = – g m ( R r o ) ≅ – gm R = A v
v in
where we have assumed that R << ro, which is reasonable for small λn
■
The transconductance is a function of the DC drain current, which is in turn a
function of R through the load line equation:
g m ≅ 2µ n C ox ( W ⁄ L )I D =
V DD – V M
2µ n C ox ( W ⁄ L )  -------------------------
R
so that A v ∝ R
■
Why not increase R to say 500 kΩ? The answer lies in the dynamic response of
the inverter. Tiny DC drain currents --> very slow transitions
Therefore, we want to have a large Av with a large ID ...
EE 105 Fall 1998
Lecture 14