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Confidential
Final
Peak Current-Mode DC-DC Converter Stability Analysis
Timothy Hegarty (email: [email protected])
Principal Engineer, Infrastructure Power Division (IPD), National Semiconductor, Tucson AZ
offered in section VII while SIMPLIS simulation is outlined
in section VIII to qualify the theoretical analysis.
I. Introduction
The popularity and perceived advantages of current-mode
control (CMC) have made it de rigueur as a loop control
architecture with many power management IC
manufacturers and power supply vendors. Also known as
multi-loop control, an external voltage loop and a widebandwidth inner current loop are standard. Peak, valley,
average, hysteretic, constant on-/off-time, and emulated
(sample-and-hold) current-mode techniques are realizable.
But each technique, like being the most famous golfer in the
world, has upsides and downsides. Top of the agenda is
usually peak current-mode control (PCMC) with slope
compensation. Notable advantages of PCMC include
automatic input line feedforward, inherent cycle-by-cycle
overload protection, and current sharing capability in multiphase converters. Acute shortcomings are current loop noise
sensitivity and switch minimum on-time limitations,
particularly in high step-down ratio, non-isolated converter
applications. The emulated architecture[1,5] largely alleviates
these shortcomings, however, while preserving the benefits
of PCMC.
Loop stability in fixed switching frequency, naturallysampled, peak current-mode controlled, buck-derived DCDC converters * is the basis for this discussion. Section II
underpins the peak current-mode architecture operating
principles while section III presents the small-signal model,
including control-to-output transfer function, of the currentmode buck converter. Design of the current loop, including
condition for slope compensation, is pursued in section IV.
Section V provides insight into the compensator transfer
function using an error amplifier with finite gain-bandwidth
characteristic. The reader solely interested in current-mode
control loop compensation can read the abridged version of
this article by proceeding directly to section VI where low
entropy, understandable expressions are derived from the
context of the small-signal model and from which an
intuitive compensator design procedure for a PCMC buck
converter is illustrated. The simplicity and expediency of the
procedure renders it viable for everyday use by the
practicing power electronics engineer. A design example
based on a commercially available PWM controller is
*
Valley current-mode control has been eschewed given its slope
compensation implementation difficulties and poor line feed-forward
characteristic. Hysteretic current-mode control has excellent transient
response but requires variable switching frequency. Average current-mode
control, widely used in low THD PFC boost pre-regulators, benefits from
elimination of the external ramp, increased low frequency current loop gain,
and improved noise immunity. The present discussion concentrates on fixed
frequency DC-DC applications where PCMC is the prevalent control
architecture.
Draft Article
Final Rev
II. Peak Current-Mode Control and Slope
Compensation Review
The converter in Figure 1 is that representing a single-phase
buck topology operating in continuous conduction mode
(CCM), and whose duty cycle, D, is determined by recourse
to the principles of PCMC. Note that the parasitic resistances
of the filter inductor and output capacitor are denoted
explicitly. Other buck-derived power stage topologies –
including isolated forward, full-bridge, voltage-fed push-pull
– could also be inserted here, while retaining a similar loop
configuration (feedback isolation excepted).
Vin
LM27222
Driver
&
Deadtime
Buck Converter Power Stage
L
Rdcr
Vo
SW
Resr
iL
R
Io
Co
Sensed
Current
Modulator
Slope Comp
Ramp
Q R
+
Type-II Voltage Loop
Compensator
+
-
COMP
gm
+
S
PWM
Comparator
Clock
Ts
Vref
Error
Amp
Rcomp
Rfb1
+
-
FB
Chf
Ccomp
Rfb2
Figure 1: DC-DC synchronous buck converter schematic
of power train, driver stage and peak current-mode
PWM control loop structure with transconductance
error amplifier
In a peak current-mode architecture, the state of the inductor
current is naturally sampled by the PWM comparator. The
outer voltage loop employs a type-II voltage compensation
circuit and a conventional transconductance type error
amplifier (EA) is shown with its inverting input, labeled the
feedback (FB) node, connected to feedback resistors Rfb1 and
Rfb2. A compensated error signal appears at the EA output,
labeled COMP, the outer voltage loop thus providing the
reference command for the inner current loop. COMP
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Final
vcomp  iLavg Ri  0.5Sn DTs  Vslope D
effectively represents the programmed inductor current
level.
The current loop converts the inductor into a quasi-ideal
voltage-controlled current source, effectively removing the
inductor from the outer loop dynamics, at least at DC and
low frequencies. In fact, the current loop acts as a lossless
damping resistor by splitting the complex conjugate poles of
the LC filter into two real poles – one pole appears at low
frequency and is related to the output capacitor and load
resistance; the other pole reappears at high frequency when
the inductor impedance equals the current loop gain[1].
Sn+Se
iLpeakRi
(1)
where Gi is the current sense amplifier gain (if used) and Rs
is the current sensor gain given by one of
 Rshunt , current shunt resistance

 Rdcr , inductor parasitic DC resistance

Rs    
 Rds (on) , MOSFET on-state resistance

 N CT Rburden , CT turns ratio & burden resistance
Inductor
Current
iLavgRi
Sf
Sn
Sn 
iLvalleyRi
Vslope = SeTs
The current sensing location in Figure 1 is shown
schematically after the inductor. The implementation could
be a discrete shunt resistor, or losslessly using inductor DCR
current sense or MOSFET on-state resistance[2].
Alternatively, a current sense transformer can be exploited
but only if the current sense location is such that the current
waveform is zero for part of the switching period to allow
transformer reset, e.g. in series with the high-side FET. In
any event, the equivalent linear amplifying multiple is given
by
Ri  Gi Rs 
COMP
Voltage
vcomp
D
Sf
D
Slope
Comp
Ramp
Se
Duty
Cycle
Clock
DTs 2
D Ts
DTs
Ts  1 f s  2 s
Figure 2: Time sequence diagram of the peak currentmode modulator waveforms
III. CMC Small-Signal Analysis Review
The analytical nexus around which a small-signal dynamic
model is based on Middlebrook and Cuk’s famous state
space averaging (SSA) technique or Vorpérian’s PWM
switch model. An intuitive model of the small-signal
current-mode system is illustrated in the block diagram
format of Figure 3[1].
Z L (s)







A perfect current-mode converter relies only on the DC or
average value of inductor current. In practice, a peak-toaverage error exists in a PCMC implementation and this
error can manifest itself as a sub-harmonic oscillation of the
current loop in the time domain at duty cycles above 50%.
Slope compensation is the well-known technique of adding a
ramp to the sensed inductor current to obviate the risk of this
sub-harmonic oscillation. Figure 2 illustrates how a turn-on
command is activated when the clock edge sets the PWM
latch. A turn-off command is imposed when the sensed
inductor current peak plus slope compensation ramp reaches
the COMP level and the PWM comparator resets the latch.
This is known as trailing edge modulation. Se, earmarked in
Figure 2, is the external slope compensation ramp slope and
Sn and Sf are the on-time and off-time slopes of the sensed
current signal, respectively. D  1  D is the duty cycle
complement.
Draft Article
Final Rev
KM
vsw (s)
L
Rdc
Modulator
iL (s)
Ri=GiRs
+
–
Gi
He(s)
Current
Sense Amplifier
vcomp (s)
Rs
vo (s)
Resr
Co
AC output
variation

Ro Z o (s)



Gc(s)
Compensator
Figure 3: Simplified small-signal control loop block
diagram of a buck converter with peak current-mode
control
Modulator gain KM is the gain from the duty cycle to the
switch node voltage. Contingent upon the load characteristic,
Ro represents the small-signal AC load resistance given by
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 R  Vo I o


Ro   RD



Final
The dominant filter pole and capacitor ESR zero frequencies
are given respectively by
resistive load
small-signal dynamic resistance,
non-linear load, e.g. LED
 p  2 f p 
current source load
whereas R represents the DC operating point of the load. The
component Rdc in Figure 3 is the cumulative series resistance
attributed to the inductor DCR, MOSFET on-state
resistance, and PCB trace resistance
Rdc  DRds(on) hi side  DRds (on)loside  Rdcr  Rpcb
(2)

m D  0.5
1
 c
Ro Co
f s LCo

1
Resr Co
(8)
(9)
A typical control-to-output transfer function frequency
response is elucidated in Figure 4. The pole and zero
locations are denoted by  and o symbols, respectively.
40
45
Contol-to-Output Phase

0
fp
20
Contol-to-Output Gain
-45
(3)
vo (s)  vsw (s)
Co  Ro K M Ri 
esr  2 fesr 
From Figure 3, the small-signal AC variation of the switch
node and output voltages are written as
vsw (s)  K M vcomp (s)  Gi H e (s)Rs iL (s)
1
Z o (s)
Z o (s)  Z L (s)
0
Gain
(dB
fL
-90
Phase
(°
-20
-135
fesr
Thus
-40
Gv (s) 
vo (s)
vcomp (s)

vin (s)0
K M Z o (s)
(4)
Z o (s)  Z L (s)  K M Ri H e (s)
-180
-60
0.01
0.1
1
10
100
-225
10000
1000
Frequency (kHz)
This describes the small-signal behavior of the modulator
and power stage when the small-signal input voltage
variation is zero. The expressions for impedances Zo(s) and
ZL(s) can be substituted into (4) to obtain the pole/zero form
of the control-to-output transfer function as

s 
Adc 1 

 esr  H (s)
Gv (s) 

s 
1 

 p 


(5)
H(s), the high-frequency extension in the control-to-output
transfer function to model the modulator sampling gain, is
discussed in more detail in the next section. The relevant
gain coefficients can be derived as
Adc 
K M Ro
R
 o
Ro  Rdc  Rs  K M Ri Ri
KM 
Draft Article
Ro
 mc D  0.5
fs L
1
T V
 0.5  D  Ri s  slope
L
Vin
IV. Modulator Sampling Gain and
Optimum Slope Compensation
A current-mode control system is a sampled system, the
sampling frequency of which is equal to the switching
frequency (except hysteretic). A traditional low-frequency
averaged model can be modified to include the sampling
effect in the current loop by one of two generally accepted
methods:
1.
Include a complex RHP double zero term, H e (s) , in the
current feedback path as advised by Ridley[3] and
included in Figure 3
2
1
1
Figure 4: Typical control-to-output small-signal
frequency response
(6)
(7)
Final Rev
H e (s)  1 
s
s
 2;
Qn ωn  n
Qn 
2

, ωn 
ωs
  fs (10)
2
This is represented in the control-to-output transfer function
as a pair of complex RHP poles such that
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1
H (s) 
2
1
(11)
s
s

Qωn  2n
1
  mc D   0.5 
peaking in the current loop gain and ultimately voltage loop
instability as duty cycles exceeds 50%.
V.
For any converter, the quality factor, Q, is
Q
Final
(12)
Compensator Transfer Function
A type II compensator using an EA with transconductance,
gm, is shown in Figure 5. The dominant pole of the EA openloop gain is set by the EA output resistance, REAout, and
effective bandwidth-limiting capacitance, Cbw, as follows
GEA (openloop ) (s)  
with the slope compensation parameter defined as
mc  1 
2.
Se
Sn
(13)
Insert a real pole of frequency L  2 f L in series with
the modulator gain block as averred by Tan and
Middlebrook[4] such that
H (s) 
1
s
K R
 s 
Q M i

L
 2 
L  
(15)
  A fb g m Z EAout (s)

1
Z EAout (s)  g m REAout  Rcomp 

sCcomp

(18)
 1

 sChf

1
(19)
sCbw
and the feedback attenuation factor is
For single-cycle damping of an inductor current
perturbation, the baseline requirement is that the slope
compensation ramp should equal the inductor down-slope[1],
i.e.
Afb 
Vref
Vo

R fb 2
(20)
R fb1  R fb 2
Vo
Accordingly, a perturbed inductor current will return to its
original value in one switching cycle and the resultant Q
factor, calculated from (12), is equal to 2/ or 0.637. Even
though most PCMC implementations exploit a fixed slope
compensation ramp amplitude, the ideal slope compensation
level is proportional to output voltage. Note that excessive
slope compensation increases mc, decreases Q, and reduces
the current loop gain and bandwidth. This portends
additional phase lag in the voltage loop and stymies the
maximum attainable crossover frequency. The load pole and
sampling-gain pole converge and the system is inherently
tilted towards voltage-mode control. Conversely, insufficient
slope compensation decreases mc and increases Q, causing
Final Rev
Rfb1
Error Amplifier
Model
(16)
mc D  1
Draft Article
vo (s)
with
where Q is also defined by (12).
V
Se  S f  o Ri
L
V
Vslope  Se Ts  o RiTs
L
vcomp (s)
(14)
L
(17)
The influence of any EA high frequency parasitic poles is
neglected in the above expression. The compensator transfer
function from output voltage to COMP, including the gain
contribution from the feedback resistor divider network, is
given by
Gc (s) 
1
g m REAout
1  sREAout Cbw
COMP
–
Rcomp
+
FB
Vref
Chf
pEA2
gm
zEA
Rfb2
Ccomp pEA1
REAout Cbw
Figure 5: Transconductance EA small-signal
representation; the components representing two poles
and one zero are circled
Evaluating (19) gives an expression of the form
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Z EAout (s)  REAout
1  s  zEA



1  s  pEA1  s  pEA1 pEA2
2

(21)
As  pEA1 and  pEA2 are well separated in frequency, the
low Q approximation applies and (21) becomes
1
Z EAout (s)  REAout
Final
Here, the feedback attenuation is unity and the EA has openloop DC gain of 50dB and 5MHz single-pole gainbandwidth characteristic. Again, the poles and zeros are
denoted with  and o symbols, respectively, and a + symbol
indicates the EA bandwidth. Note that the 180° phase lag
related to the EA in the inverting configuration is not
included in the phase plots.
Compensator pole pEA1 appears at very low frequency and
can be superseded by an integrator term. (22) simplifies to
s
 zEA

s 
s
1 
 1 
  pEA1    pEA2


(22)




1
Gc (s)  
where
s
 zEA
Ac
s 1 s
(24)
 pEA
1
;
Rcomp Ccomp
 zEA 
pEA1 
pEA2 
The integrator gain term, Ac, is given by
1



1
;
REAout Ccomp


1
;
Rcomp Chf


REAout Ccomp  Chf  Cbw
1


Rcomp Ccomp Chf  Cbw
Typically, Rcomp  REAout , Ccomp  Chf  Cbw and the
approximations set forth in (23) are valid. The components
creating the two compensator poles and one compensator
zero are circled in Figure 5. The typical frequency response
of the open-loop EA and the compensator is given in Figure
6.
f pEA(open loop ) 
f pEA1 
1
Ac 
(23)
1
2 REAout Cbw
VI.
EA Open-Loop Gain
40

90
Co
mp
ens
a
20
Gain
(dB
t or
Ga
in
45
Phase
(°
EA Open-Loop Phase
0

0
-45
-20
Compensator
Phase
0.01
0.1
Frequency (kHz)
1
10
f zEA 
100
1000
1
2 Rcomp Ccomp
f pEA2 
fGBW 

s 
Ac 1 

  zEA 

T (s)   

s 
s 1 

  pEA 


gm
2 Cbw
1
2 Rcomp Chf
Figure 6: Open-loop EA and compensator small-signal
frequency response
Draft Article
Final Rev
one compensator pole, pEA1, positioned to provide
high gain in the low frequency range, minimizing
output steady state error for better load regulation;
one compensator zero located to offset the
dominant load pole, zEA = p. Typically, the
minimum load resistance (maximum load current)
condition is used;
one compensator pole positioned to cancel the
output capacitor ESR zero, pEA2 = esr;
The loop gain is expressed as the product of the control-tooutput and compensator transfer functions. Substituting (5)
and (24), the loop gain is
-90
10000
-40
CMC Compensator Design
A frequently employed, yet corrigible, compensation
strategy is to equate the control-to-output transfer function to
the compensator transfer function term by term to attain a
single-pole –20dB/decade roll-off of the loop response. To
demonstrate, consider
135
g m REAout
(25)
Note that both feedback resistors, Rfb1 and Rfb2, factor into
the control loop gain when a transconductance type EA is
used. In contrast, if an op-amp type EA is employed, the FB
node is effectively at AC ground and Rfb2 bears no influence
on the loop dynamics.

2 REAout Ccomp
60
gm
A fb
Ccomp
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
s 
Adc 1 

 esr 

s 
s 
1 
 1
  p   L 


(26)
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The crossover frequency, c = 2fc, where the loop gain is
0dB, is usually selected between one tenth and one fifth of
the switching frequency. If zEA = p and pEA = esr, the
loop gain reduces to
T s   
Ac Adc

s 
s 1 

 L 

T j p  T  jzEA   Ac Adc Rcomp Ccomp  gm Afb Adc Rcomp (28)
Using basic bode plot principles, it is apparent that


T j p 
c
p
(29)
A straight-forward solution for the crossover frequency is
thus derived as
fc  f p gm Afb Adc Rcomp
(30)
Finally, compensator component values can be calculated
sequentially as
Rcomp
fc
1

;
g m A fb Adc f p
Ccomp
1

;
 p Rcomp
resonant
frequency,
1
1
 Ccomp 
;
 p Rcomp
LC Rcomp
(32)
Furthermore, a smaller compensation capacitance is
advantageous when the transconductance EA has a low
output drive current capability.
VII. CMC Compensator Design Example
The circuit operating conditions, key component values and
control circuit parameters of a buck converter based on one
channel of a LM5642X dual-channel synchronous buck
PWM controller are specified in Table 1.
Vin
24V
fs
375kHz
Cbw
11pF
Vo
5.0V
Rdc
5m
Vslope
0.25V
Io
5A
Resr
5m
Se
94mV/s
D
0.208
Rs
20m
Sn
353mV/s
L
5.6H
Gi
5.2
mc
1.266
Co
50F
gm
720-1
Q
0.634
Table 1: LM5642X buck converter parameters
KM 

 V

; R fb1  R fb 2  o  1


0.1mA
 Vref

Vref
Adc 
An initial value is selected for Rfb2 based on a practical
minimum current level flowing in the divider chain. Note
that the compensation zero frequency represents the
dominant time constant in a load transient response
characteristic. A large Ccomp capacitor is thus antithetical to a
fast transient response settling time. Ccomp can be reduced,
however, to tradeoff phase margin and settling time. A phase
margin target of 50° to 60° is ideal. It is found that the
compensator zero is optimally located above the load pole
Draft Article
stage
Ri  Gi Rs   5.2  20m   0.104;
1

 Cbw ;
 esr Rcomp
R fb 2 
below the power
LCo , so that
LC  1
The relevant gains and power stage corner frequencies are
calculated using expressions (6) through (9) as follows:
(31)
Chf
but
(27)
Assuming a well designed current loop as described in
section IV (Q = 0.637), the sampling-gain pole is located at
20-30% of switching frequency. This assumption precludes
the case where too much slope compensating ramp is added.
The magnitude of the loop gain at the dominant pole
frequency is

Final
Final Rev

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1
 0.5  D  Ri
Ts Vslope

L
Vin
1
 0.5  0.208 0.104 
2.66μs 0.25V

5.6μH
24V
K M Ro
Ro  Rdc  Rs  K M Ri
 40.22 1 
1  5m  20m   40.22  0.104 
 40.22; (33)
 7.72;
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Final
80
1
fp 
2πCo  Ro K M Ri 
1

 3.95kHz;
(34)
2π  50μF  1   40.22  0.104   


1
1
f esr 

 636kHz
2 Resr Co 2π  5m  50μF 
90
Lo
o
Ide p Ga
i
al
EA n,
Compensator
Pole
60
40
Gain
(dB
20
The compensation component values, assuming a desired
crossover frequency of 60kHz, are found using (31) and (32)
as
Compensator
Zero
Loop
Non-I Phase,
deal
EA
0
45
Load
Pole
Loop Gain,
Non-Ideal EA
-45
Rcomp
Ccomp
Chf 
1
 esr Rcomp
Loop Phase,
Ideal EA
-20
-135
-40
-180
-60
0.01
0.1
1
10
-225
1000
100
fc =
60kHz
Compensator
Pole
Using a LM5642X PWM controller in a buck converter
configuration per Table 1, a SIMPLIS switching mode
circuit simulation is used to substantiate the analysis
heretofore. The SIMPLIS schematic is presented in Figure 8.
 Cbw
20m
Rs
S1
D
Vin
X1
24
5.6u
5m
L
Rdcr
Vo = 5V
U1
0.1mA
5.2

1.2364V
 12.4k;
0.1mA
Vramp
Mod1
Q
R
QN
S2
1
Ro
Itran
5m
Resr
Gi
Vclock
T = 2. 667us
IN
OUT
Output
= OUT/IN
AC 1 0
Vosc
Control
37.8k
Rfb2
(35)
11k
Rcomp
Figure 7 shows a Mathcad derived loop gain and phase plot
of the exemplified converter. The equivalent plots with an
ideal EA are also shown. The phase margin, M, is the
difference between the loop phase and –180° (EA inversion
phase lag notwithstanding). Note that if Chf is not installed,
the EA itself provides high-frequency attenuation by virtue
of its finite gain-bandwidth.
Final Rev
gm
Vcomp
12p
Chf
Draft Article
S
Vo
50u
Co
1–D
Vslope
 V

R fb1  R fb 2  o  1
 Vref



 5V

= 12.4k 
 1  37.8k
1.2364V


Output
Capacitor
ESR Zero
VIII. SIMPLIS Simulation
Ri=Gi*Rs
Vref
M =
55°
Figure 7: LM5642X based buck converter loop gain and
phase plot
1

 11pF = 12pF;
2π  636kHz 11k 
R fb 2 
Phase
(°
-90
Frequency (kHz)
fc
1

g m A fb Adc f p
1
60kHz

 11k;
1.2364V
3.95kHz

1 
720μ 
  7.72 
 5V 
1

LC Rcomp
1

 1.5nF;
2π  9.5kHz 11k 
0
Sampling
Gain Pole
11p
Cbw
500k
REAout
720u
FB
1. 2364
Vref
12.4k
Rfb1
1.5n
Ccomp
Figure 8: LM5642 based buck converter SIMPLIS AC
analysis simulation schematic
The loop gain T(s) of the system is measured by breaking the
loop at the upper feedback divider resistor, injecting a
variable frequency oscillator signal, and analyzing the
frequency response. The element with reference designator
X1 in Figure 8 is the SIMPLIS clock edge trigger to find the
circuit periodic operating point (POP) before running the AC
analysis. The AC source with reference designator Vosc is
the input stimulus for the AC sweep. Figure 9 illustrates the
bode plot simulation result that aligns closely with the
analytical result in Figure 7.
2/18/2010
Page 7 of 8
Confidential
Y2
[3] R. B. Ridley, ‘A New, Continuous-Time Model for
Current-Mode Control’, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991, pp. 271-280.
Y1
250
60
Loop Gain
200
[4] F. D. Tan, R. D. Middlebrook, ‘A Unified Model for
Current-Programmed Converters’, IEEE Transactions on
Power Electronics, Vol. 10, No. 4, July 1995, pp. 397-408.
0
Phase / degrees
Gain / dB
40
20
150
100
[5] National Semiconductor LM3000 Dual Synchronous
Emulated Current-Mode Controller from PowerWise®
Family, http://www.national.com/pf/LM/LM3000.html
Loop Phase
50
-20
-40
Final
0
-60
10
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
200k
500k
1M
freq / Hertz
Figure 9: Bode plot simulation result
Using a SIMPLIS transient analysis, load-on and load-off
transient responses are obtained using high (3.7nF) and low
(1.5nF) compensation capacitor values chosen so that the
compensator zero is located directly at the load pole and the
power stage resonant frequencies, respectively. The load
step is from 50% to 100% full load at 1A/s. It is evident
that the lower compensation capacitance imputes a much
more favorable settling time. Interestingly, this is achieved
with very little relative change in the bode plot:
approximately 1kHz decrease in crossover frequency and 4°
less phase margin using the 1.5nF capacitor.
Y2
Y1
5
5.1
Output
Current
Vo with Ccomp
= 1.5nF
4.5
5.05
3.5
VOUT / V
IOUT / A
4
5
4.95
3
Vo with Ccomp
= 3.7nF
4.9
2.5
2
4.85
0
0.2
0.4
time/mSecs
0.6
0.8
1
200 uSecs /div
Figure 10: Load step transient response simulation with
two values of compensation capacitance
IX.
Further Reading
[1] R. Sheehan, National Semiconductor, ‘Current-Mode
Modeling – Reference Guide’,
http://www.national.com/analog/power/conference_paper_d
esign_ideas
[2] National Semiconductor LM5642 High Voltage, Dual
Synchronous Buck Converter with Oscillator
Synchronization from the PowerWise® Family,
http://www.national.com/pf/LM/LM5642.html
Draft Article
Final Rev
2/18/2010
Page 8 of 8