LTC6403-1 - 200MHz, Low Noise, Low Power Fully Differential Input
... test circuit of Figure 1 by applying a voltage on the VOCM pin and testing at both mid supply and at the Electrical Characteristics table limits to verify that the differential gain has not deviated from the mid supply VOCM case by more than 1%, and the common mode offset (VOSCM) has not deviated by ...
... test circuit of Figure 1 by applying a voltage on the VOCM pin and testing at both mid supply and at the Electrical Characteristics table limits to verify that the differential gain has not deviated from the mid supply VOCM case by more than 1%, and the common mode offset (VOSCM) has not deviated by ...
DATA SHEET UDA1334BTS Low power audio DAC
... converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achie ...
... converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achie ...
Ω MAX4721/MAX4722/MAX4723 4.5 Dual SPST Analog Switches in UCSP
... The MAX4721/MAX4722/MAX4723 dual SPST analog switches operate from a single +1.8V to +5.5V supply. The MAX4721/MAX4722/MAX4723 offer excellent AC characteristics, <0.5nA leakage current, less than 2ms differential skew, and 15pF on-channel capacitance. All of these devices are CMOS-logic compatible ...
... The MAX4721/MAX4722/MAX4723 dual SPST analog switches operate from a single +1.8V to +5.5V supply. The MAX4721/MAX4722/MAX4723 offer excellent AC characteristics, <0.5nA leakage current, less than 2ms differential skew, and 15pF on-channel capacitance. All of these devices are CMOS-logic compatible ...
Complete Quad, 16-Bit, High Accuracy, Serial Input, ±5 V DAC AD5765 Data Sheet
... permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the fa ...
... permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the fa ...
Synery Operation Manual
... working fuse and a spare fuse inside the fuse drawer. The drawer can only be opened once the mains lead is removed from the connector. The fuse is provided to protect both the mains and your amplifier as well as reducing the degree of damage if an internal fault exists. When replacing the fuse, repl ...
... working fuse and a spare fuse inside the fuse drawer. The drawer can only be opened once the mains lead is removed from the connector. The fuse is provided to protect both the mains and your amplifier as well as reducing the degree of damage if an internal fault exists. When replacing the fuse, repl ...
MAX769 完备的电源及监控系统，简化设计、降低成本、节省空间
... Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Current into the NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw si ...
... Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Current into the NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw si ...
DAC8805 数据资料 dataSheet 下载
... The DAC8805 dual, multiplying digital-to-analog converter (DAC) is designed to operate from a single 2.7V to 5.5V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale o ...
... The DAC8805 dual, multiplying digital-to-analog converter (DAC) is designed to operate from a single 2.7V to 5.5V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale o ...
MAX13170E +5V Multiprotocol, 3Tx/3Rx, Software- Selectable Clock/Data Transceiver General Description
... The MAX13170E is a three-driver/three-receiver multiprotocol transceiver that operates from a +5V single supply. The MAX13170E, along with the MAX13172E and the MAX13174E, form a complete software-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that supp ...
... The MAX13170E is a three-driver/three-receiver multiprotocol transceiver that operates from a +5V single supply. The MAX13170E, along with the MAX13172E and the MAX13174E, form a complete software-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that supp ...
LT6600-20
... the LT6600-20 using single-ended instruments with 50 source impedance and 50Ω input impedance. For a unity gain configuration the LT6600-20 requires a 402Ω source resistance yet the network analyzer output is calibrated for a 50Ω load resistance. The 1:1 transformer, 53.6Ω and 388Ω resistors satisfy ...
... the LT6600-20 using single-ended instruments with 50 source impedance and 50Ω input impedance. For a unity gain configuration the LT6600-20 requires a 402Ω source resistance yet the network analyzer output is calibrated for a 50Ω load resistance. The 1:1 transformer, 53.6Ω and 388Ω resistors satisfy ...
MAX1951A 1MHz, 2A, 2.6V to 5.5V Input, PWM DC-DC General Description
... The internal high-side MOSFET has a current limit of 3.1A (typ). If the current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the synchronous rectifier turns on. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded ...
... The internal high-side MOSFET has a current limit of 3.1A (typ). If the current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the synchronous rectifier turns on. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded ...
AD7839 数据手册DataSheet 下载
... VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V VREF(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V VR ...
... VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V VREF(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V VR ...
DAC8822 数据资料 dataSheet 下载
... tracking for the full-scale output when combined with an external, current-to-voltage (I/V) precision amplifier. A RSTSEL pin allows system reset assertion (RS) to force all registers to zero code when RSTSEL = '0', or to midscale code when RSTSEL = '1'. Additionally, an internal power-on reset forc ...
... tracking for the full-scale output when combined with an external, current-to-voltage (I/V) precision amplifier. A RSTSEL pin allows system reset assertion (RS) to force all registers to zero code when RSTSEL = '0', or to midscale code when RSTSEL = '1'. Additionally, an internal power-on reset forc ...
Dual Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable FEATURES APPLICATIONS
... current-feedback op amps. Operating on a very low 5.1mA/ch supply current, the OPA2691 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. Thi ...
... current-feedback op amps. Operating on a very low 5.1mA/ch supply current, the OPA2691 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. Thi ...
Inverting and non-inverting amplifier
... gain, high input impedance and low output impedance. Op-amp is basically a differential amplifier whose basic function is to amplify the difference between two input signals. Op-amp has five basic terminals, that is, two input terminals, one o/p terminal and two power supply terminals. Pin2 is calle ...
... gain, high input impedance and low output impedance. Op-amp is basically a differential amplifier whose basic function is to amplify the difference between two input signals. Op-amp has five basic terminals, that is, two input terminals, one o/p terminal and two power supply terminals. Pin2 is calle ...
MAX2510 Low-Voltage IF Transceiver with Limiter/RSSI and Quadrature Modulator ________________General Description
... levels beyond the mixer’s 1dB compression level. Input 1dB compression point is limited by MIXOUT voltage swing, which is approximately 2Vp-p into a 165Ω load. Note 5: Assuming the supply voltage has been applied, this includes limiter offset-correction settling and Rx or Tx bias stabilization time. ...
... levels beyond the mixer’s 1dB compression level. Input 1dB compression point is limited by MIXOUT voltage swing, which is approximately 2Vp-p into a 165Ω load. Note 5: Assuming the supply voltage has been applied, this includes limiter offset-correction settling and Rx or Tx bias stabilization time. ...
RBE-12/20-D48 Series
... All capacitors are low-ESR types mounted close to the converter. These capacitors are necessary for our test equipment and may not be needed in the user’s application. ➁ Input (back) ripple current is tested and specified over 5 Hz to 20 MHz bandwidth. Input filtering is Cbus = 220 μF, Cin = 33 μF and ...
... All capacitors are low-ESR types mounted close to the converter. These capacitors are necessary for our test equipment and may not be needed in the user’s application. ➁ Input (back) ripple current is tested and specified over 5 Hz to 20 MHz bandwidth. Input filtering is Cbus = 220 μF, Cin = 33 μF and ...
1.6 V, Micropower 12-Bit ADC AD7466-KGD Known Good Die FEATURES
... in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. SCLK low pulse width. SCLK high pulse wid ...
... in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. SCLK low pulse width. SCLK high pulse wid ...
h 数据资料 dataSheet 下载
... Supply voltage (see Note 1): VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . ...
... Supply voltage (see Note 1): VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . ...
AD5310 数据手册DataSheet 下载
... as 30 MHz making the AD5310 compatible with high speed DSPs. On the sixteenth falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low o ...
... as 30 MHz making the AD5310 compatible with high speed DSPs. On the sixteenth falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low o ...
10-bit, 125 MS/s, 40 mW Pipelined ADC in 0.18 μm CMOS
... the analog input signal VIN is applied to capacitors CS(IN), CC1, and CC2. The analog input signal ranges from -4VR to +4VR. Simultaneously, reference voltages of +2VR, 0, and -2VR are applied to capacitors CS(-1), CS(0), and CS(+1), respectively. To prevent sample clock skew between the converter a ...
... the analog input signal VIN is applied to capacitors CS(IN), CC1, and CC2. The analog input signal ranges from -4VR to +4VR. Simultaneously, reference voltages of +2VR, 0, and -2VR are applied to capacitors CS(-1), CS(0), and CS(+1), respectively. To prevent sample clock skew between the converter a ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.