Product Specification
... Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CCFL, for instance, becomes more than 1 [M ohm] when CCFL is damaged. *4 Generall ...
... Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CCFL, for instance, becomes more than 1 [M ohm] when CCFL is damaged. *4 Generall ...
Evaluates: MAX5926 MAX5926 Evaluation Kit General Description Features
... 0.3V/ms. Refer to the MAX5926 IC data sheet for more details on calculating C2 for a different slew rate. Short-circuit detection must be used on the MAX5926 EV kit when no RSENSE is used, and must not be used when an RSENSE is used. Table 7 shows the jumper JU7 settings to enable or disable short-c ...
... 0.3V/ms. Refer to the MAX5926 IC data sheet for more details on calculating C2 for a different slew rate. Short-circuit detection must be used on the MAX5926 EV kit when no RSENSE is used, and must not be used when an RSENSE is used. Table 7 shows the jumper JU7 settings to enable or disable short-c ...
Digital Logic
... magnetizes core and causes normally closed (nc) contact to be pulled open when no current flows, the spring of the contact returns it to its normal position ...
... magnetizes core and causes normally closed (nc) contact to be pulled open when no current flows, the spring of the contact returns it to its normal position ...
Manual - Precision Digital
... Cascade Mode Multiple Unit I/O Connections When using Cascade Mode (see page 19), I/O terminals I and O shown in Figure 5 may be used to link together multiple converters, and provide additional inputs and outputs for monitoring. An unlimited number of units may be connected in this way. To connect ...
... Cascade Mode Multiple Unit I/O Connections When using Cascade Mode (see page 19), I/O terminals I and O shown in Figure 5 may be used to link together multiple converters, and provide additional inputs and outputs for monitoring. An unlimited number of units may be connected in this way. To connect ...
MAX9157 Quad Bus LVDS Transceiver General Description Features
... voltage transition time = 1ns (20% to 80%). Input common-mode voltage VCM = 1.2V to 1.8V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5) ...
... voltage transition time = 1ns (20% to 80%). Input common-mode voltage VCM = 1.2V to 1.8V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5) ...
Design And Construction of Anti-Bag Snatching
... The output from pin 6 of IC1 is fed to trigger pin 2 of IC NE555 (IC2) via coupling capacitor C1 (0.0047 μF). IC2 is configured as a monostable. Its trigger pin 2 is held high by resistor R4 (10 kilo-ohms). Normally, the output of IC2 remains low and the alarm is off. Resistor R6, along with c ...
... The output from pin 6 of IC1 is fed to trigger pin 2 of IC NE555 (IC2) via coupling capacitor C1 (0.0047 μF). IC2 is configured as a monostable. Its trigger pin 2 is held high by resistor R4 (10 kilo-ohms). Normally, the output of IC2 remains low and the alarm is off. Resistor R6, along with c ...
ADS1100 数据资料 dataSheet 下载
... carries data; SCL provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has se ...
... carries data; SCL provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has se ...
MAX3387E 3V, ±15kV ESD-Protected, AutoShutdown Plus General Description
... forces the transmitters on for 100ms, allowing enough time for the other system to realize that the MAX3387E is awake. If the other system outputs valid RS-232 signal transitions within that time, the RS-232 ports on both systems remain enabled. ...
... forces the transmitters on for 100ms, allowing enough time for the other system to realize that the MAX3387E is awake. If the other system outputs valid RS-232 signal transitions within that time, the RS-232 ports on both systems remain enabled. ...
MAX6351–MAX6360 Dual/Triple-Voltage µP Supervisory Circuits General Description
... The MAX6351–MAX6360 microprocessor (µP) supervisors with multiple reset voltages significantly improve system reliability and accuracy compared to separate ICs or discrete components. If any input supply voltage drops below its associated preset threshold, all reset outputs are asserted. In addition ...
... The MAX6351–MAX6360 microprocessor (µP) supervisors with multiple reset voltages significantly improve system reliability and accuracy compared to separate ICs or discrete components. If any input supply voltage drops below its associated preset threshold, all reset outputs are asserted. In addition ...
ADC and DAC
... Very fast for high quality audio and video. Very expensive for wide bits conversion. Sample and hold circuit usually NOT required. The number of comparators needed is 2N-1 which grows rapidly with the number of bits – E.g. for 4-bit, 15 comparators; ...
... Very fast for high quality audio and video. Very expensive for wide bits conversion. Sample and hold circuit usually NOT required. The number of comparators needed is 2N-1 which grows rapidly with the number of bits – E.g. for 4-bit, 15 comparators; ...
a +5 V Fixed, Adjustable Low-Dropout Linear Voltage Regulator ADP3367*
... reached, the DD output starts sourcing current into the SET input through R3. This increases the SET voltage so that the regulator feedback loop does not drive the internal PNP transistor as hard as it otherwise would. As the input voltage continues to decrease, more current is sourced, thereby redu ...
... reached, the DD output starts sourcing current into the SET input through R3. This increases the SET voltage so that the regulator feedback loop does not drive the internal PNP transistor as hard as it otherwise would. As the input voltage continues to decrease, more current is sourced, thereby redu ...
2.2.2 Monostable Circuits Word Document
... From the work in our first topic, you should realise that 29kΩ is not one of the preferred resistor values from the E24 series. There are two options, either use a 27kΩ resistor and two 1kΩ in series, or increase the resistance slightly to 30kΩ, which is what we will do in this case. We can now comp ...
... From the work in our first topic, you should realise that 29kΩ is not one of the preferred resistor values from the E24 series. There are two options, either use a 27kΩ resistor and two 1kΩ in series, or increase the resistance slightly to 30kΩ, which is what we will do in this case. We can now comp ...
AD9760 数据手册DataSheet 下载
... differential output configuration. The current outputs may be tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V. The on-chip reference and control amplifier are configured f ...
... differential output configuration. The current outputs may be tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V. The on-chip reference and control amplifier are configured f ...
analog -.. devices
... Low Cost: Two-wire transmitters minimize total system installation cost. Inexpensive, unshielded copper wire, usually in the form of a twisted wire pair, may be used for signal transmission. DC power is furnished to the transmitter over the same two-wire line by a power supply at the receiving end. ...
... Low Cost: Two-wire transmitters minimize total system installation cost. Inexpensive, unshielded copper wire, usually in the form of a twisted wire pair, may be used for signal transmission. DC power is furnished to the transmitter over the same two-wire line by a power supply at the receiving end. ...
NB3H83905CDGEVB Evaluation Board User's Manual •
... terminated by the oscilloscope (or frequency counter) input module’s internal 50 Ohms to GND impedance. ...
... terminated by the oscilloscope (or frequency counter) input module’s internal 50 Ohms to GND impedance. ...
SN65LBC182 数据资料 dataSheet 下载
... The driver outputs and the receiver inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus. This port operates over a wide range of common-mode voltage, making the device suitable for party-line applications. The device also ...
... The driver outputs and the receiver inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus. This port operates over a wide range of common-mode voltage, making the device suitable for party-line applications. The device also ...
MAX5180/MAX5183 Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs General Description
... AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 to AGND ...................................................-0.3V to +6V VREF to AGND ....................... ...
... AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Inputs to DGND.............................................-0.3V to +6V OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 to AGND ...................................................-0.3V to +6V VREF to AGND ....................... ...
DS1250Y/AB 4096k Nonvolatile SRAM FEATURES PIN ASSIGNMENT
... 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE ...
... 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE ...
MAX1272/MAX1273 Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range General Description
... Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input Data Format section. ...
... Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input Data Format section. ...
MAX9377/MAX9378 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four General Description
... The MAX9377/MAX9378 are fully differential, highspeed, low-jitter anything-to-LVPECL and anything-toLVDS translators, respectively, with a selectable divide-by-four function. Low propagation delay and high speed make them ideal for various high-speed network routing and backplane applications at spe ...
... The MAX9377/MAX9378 are fully differential, highspeed, low-jitter anything-to-LVPECL and anything-toLVDS translators, respectively, with a selectable divide-by-four function. Low propagation delay and high speed make them ideal for various high-speed network routing and backplane applications at spe ...
isscc 2013 / session 24 / energy
... The proposed IRC is applied to a 0.37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static CMOS latches, instead of flip-flops, are used ...
... The proposed IRC is applied to a 0.37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static CMOS latches, instead of flip-flops, are used ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.