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op-amp 4mhz,CA5160E.pdf
op-amp 4mhz,CA5160E.pdf

ELEC 7770: Advanced VLSI Design Spring 2010 Radio Frequency (RF) Testing
ELEC 7770: Advanced VLSI Design Spring 2010 Radio Frequency (RF) Testing

...  Z0 = 50Ω for wireless communications devices  Z0 = 75Ω for cable TV devices  Gain and frequency characteristics  S-Parameters of an RF device  S11 : input return loss or input reflection coefficient  S22 : output return loss or output reflection coefficient  S21 : gain or forward transmissio ...
PKD01 Monolithic Peak Detector with Reset-and
PKD01 Monolithic Peak Detector with Reset-and

4.5 V to 42 V Input, 5 A, Step Down DC
4.5 V to 42 V Input, 5 A, Step Down DC

MAX9508 CVBS/S-Video Filter Amplifier with SmartSleep and Bidirectional Video Support General Description
MAX9508 CVBS/S-Video Filter Amplifier with SmartSleep and Bidirectional Video Support General Description

... The MAX9508 video filter amplifier with SmartSleep and bidirectional video support is ideal for set-top boxes (STBs), portable DVD players, and portable media players (PMPs). The inputs can be directly connected to the digital-to-analog converter (DAC) outputs. The reconstruction filter removes high ...
AD7440 数据手册DataSheet下载
AD7440 数据手册DataSheet下载

... The AD7440/AD7450A are 10-bit and 12-bit high speed, low power, successive approximation (SAR) analog-to-digital converters with a fully differential analog input. These parts operate from a single 3 V or 5 V power supply and use advanced design techniques to achieve very low power dissipation at th ...
TS3DDR3812 数据资料 dataSheet 下载
TS3DDR3812 数据资料 dataSheet 下载

... Continuous current through VDD or GND ...
AD7984 数据手册DataSheet下载
AD7984 数据手册DataSheet下载

... Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is hig ...
TPS543C20 4 Vin to 16 Vin, 40-A Stackable, Synchronous Step
TPS543C20 4 Vin to 16 Vin, 40-A Stackable, Synchronous Step

2. delay elements
2. delay elements

1 Exploring methods for fast harmonic magnitude and phase
1 Exploring methods for fast harmonic magnitude and phase

... DFT implementation defined by equation (1.39) requires N2 complex number calculations. Optimized FFT algorithm requires as small as Nlog2  N  operations. Main disadvantage of DFT is failing to accomplish the second condition in practice: if frequency of x  t  varies, observation time will not be ...
Second-order intermodulation mechanisms in CMOS downconverters
Second-order intermodulation mechanisms in CMOS downconverters

... second-order intermodulation constitutes a major problem, such as in frequency-division-duplexing systems, neither of the two architectures is intrinsically advantageous. In such cases, the realization of a highly integrated low-cost solution might even be prevented. Even more, a superheterodyne arc ...
TPS62000 数据资料 dataSheet 下载
TPS62000 数据资料 dataSheet 下载

... The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching frequency of 750 kHz. At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the converter enters a power save mode (pulse frequency modulation ...
150-W, 86% High-Efficiency Primary Side Regulated DCM/CCM
150-W, 86% High-Efficiency Primary Side Regulated DCM/CCM

TPS60140 数据资料 dataSheet 下载
TPS60140 数据资料 dataSheet 下载

... the inrush current into an empty output capacitor is limited because the current through the switches is limited before the charge pump starts switching. Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control logic. The device typically draws 0 ...
Kinetis KL16: 48MHz Cortex-M0+ 32-128KB Flash 32
Kinetis KL16: 48MHz Cortex-M0+ 32-128KB Flash 32

... 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting ...
See datasheet - Texas Instruments
See datasheet - Texas Instruments

... outputs, Y and Y (or Z and Z) which are equal in amplitude but opposite in polarity. This increases the versatility of the device. By proper choice of external connections, linear amplification, and linear attenuation, and many different applications requiring logarithmic signal processing are possi ...
SKY65081-70LF: 2000-3000 MHz Low-Noise Power
SKY65081-70LF: 2000-3000 MHz Low-Noise Power

FAN3240 / FAN3241 Smart Dual-Coil Relay Drivers FAN3240 / FAN32
FAN3240 / FAN3241 Smart Dual-Coil Relay Drivers FAN3240 / FAN32

... supply voltage range from 8 V to 60 V. The filter / timer block prevents inadvertent switching from noisy input signals by providing input-pulse qualification (tQUAL) and maximum output pulse width limit (tMAX). The output can operate in follow-input mode or maximum width mode. These parameters are ...
OPAx277 High Precision Operational Amplifiers
OPAx277 High Precision Operational Amplifiers

... ±2-V to ±18-V supplies with excellent performance. Unlike most operational amplifiers which are specified at only one supply voltage, the OPAx277 series is specified for real-world applications; a single limit applies over the ±5-V to ±15-V supply range. High performance is maintained as the amplifi ...
TPS54331 3-A 28-V Input Step Down DC
TPS54331 3-A 28-V Input Step Down DC

... The TPS54331 device is a 28-V, 3-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current mode control which reduces output capacitance and simplifies external frequency co ...
ADC音频放大器系列SSM2315 数据手册DataSheet 下载
ADC音频放大器系列SSM2315 数据手册DataSheet 下载

... component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2315 uses a Σ-Δ modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. Σ-Δ modulators do not produce a sharp peak wit ...
a 32-Channel Precision Infinite Sample-and-Hold AD5533B
a 32-Channel Precision Infinite Sample-and-Hold AD5533B

MURI Book 4
MURI Book 4

... a klystron is RT, then the maximum bandwidth attainable with a single-gap output is equal to the cavity R/Q multiplied by /2 and divided by RT. The single-gap distinction is important because as we shall see, extended interaction (multiple-gap) output circuits do not obey this rule and make possibl ...
electronic multi meter qlc-110/ qlc-110l
electronic multi meter qlc-110/ qlc-110l

< 1 ... 37 38 39 40 41 42 43 44 45 ... 241 >

Phase-locked loop

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is ""fed back"" toward the input forming a loop.Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis.Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
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