Logic Demo Board Kit Compact, easy-to-use boards for fast, www.nxp.com
... } High bandwidth (up to 500 MHz) for data-rich applications } High speed with low propagation delay (0.4 ns typ) } Ability to monitor I/O rise/fall times, plus propagation delays with different loads (capacitors and resistors) } Oversupply voltage tolerance up to 5.5 V for enable inputs } Low O ...
... } High bandwidth (up to 500 MHz) for data-rich applications } High speed with low propagation delay (0.4 ns typ) } Ability to monitor I/O rise/fall times, plus propagation delays with different loads (capacitors and resistors) } Oversupply voltage tolerance up to 5.5 V for enable inputs } Low O ...
AD7675 数据手册DataSheet下载
... When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7675 provides the conversion resul ...
... When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7675 provides the conversion resul ...
STEPS tutorial
... the number of octaves swept. Initial trials should therefore be carried out with conservative signal levels and frequency resolution (1/6 octave). Options available in STEPS include amplitude, phase, amplitude + phase, amplitude + distortion and % distortion. To see the correct phase relationship th ...
... the number of octaves swept. Initial trials should therefore be carried out with conservative signal levels and frequency resolution (1/6 octave). Options available in STEPS include amplitude, phase, amplitude + phase, amplitude + distortion and % distortion. To see the correct phase relationship th ...
3011800000306
... The phase shifter circuit is connected in parallel to the SRD circuit and the main purpose of the phase shifter circuit is to delay the sharp edge generated by the SRD, and to reverse the polarity of the delayed edge by a short circuit which terminates the phase shifter (or delay line) circuit. Act ...
... The phase shifter circuit is connected in parallel to the SRD circuit and the main purpose of the phase shifter circuit is to delay the sharp edge generated by the SRD, and to reverse the polarity of the delayed edge by a short circuit which terminates the phase shifter (or delay line) circuit. Act ...
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs General Description
... The MAX5874 is an advanced 14-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.8V supplies, this dual DAC offer ...
... The MAX5874 is an advanced 14-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.8V supplies, this dual DAC offer ...
E4400A Analog RF Signal Generator, 250 kHz to 1000 MHz
... Simultaneous Modulation All modulation types may be simultaneously enabled, except: FM with PM, AM with Burst. AM, FM, and PM can sum simultaneous inputs from any two sources (INT,EXT1, and EXT2.) Any given source (INT, EXT1, or EXT2) may only be routed to one activated modulation type. Remote Progr ...
... Simultaneous Modulation All modulation types may be simultaneously enabled, except: FM with PM, AM with Burst. AM, FM, and PM can sum simultaneous inputs from any two sources (INT,EXT1, and EXT2.) Any given source (INT, EXT1, or EXT2) may only be routed to one activated modulation type. Remote Progr ...
Chapter 4
... • S-R flip-flop has 2 inputs, S (set) and R (reset) like Diagram 3 below. In the diagram below, (also for JK and D flip-flops), they used another input called clock. It is to control the movement of input that is input will only occur when given a clock pulse (synchronous circuit) • The features of ...
... • S-R flip-flop has 2 inputs, S (set) and R (reset) like Diagram 3 below. In the diagram below, (also for JK and D flip-flops), they used another input called clock. It is to control the movement of input that is input will only occur when given a clock pulse (synchronous circuit) • The features of ...
Analysis of Conventional and Novel Delay Lines: A Numerical Study
... in Fig. 7(a), showing degradation of the pulse magnitude once the main signal is received. On the other hand, when T is shorter than 2t d , the received waveform consists of a train of pulses, each of duration T and separated by 2td - T, as shown in Fig. 7(b). The wave tracing analysis adopted here ...
... in Fig. 7(a), showing degradation of the pulse magnitude once the main signal is received. On the other hand, when T is shorter than 2t d , the received waveform consists of a train of pulses, each of duration T and separated by 2td - T, as shown in Fig. 7(b). The wave tracing analysis adopted here ...
NJW4191
... When the output voltage program function is unnecessary, connects FB pin to VOUT pin. At the time of charge pump operation, the discharge speed of output capacitor varies by a load condition. And the ripple voltage also varies that is generated by this intermittent operation. When the input voltage ...
... When the output voltage program function is unnecessary, connects FB pin to VOUT pin. At the time of charge pump operation, the discharge speed of output capacitor varies by a load condition. And the ripple voltage also varies that is generated by this intermittent operation. When the input voltage ...
DS4266 DDR Clock Oscillator General Description Features
... The DS4266 surface-mount ceramic crystal oscillator is part of Maxim’s DS4-XO crystal oscillator product family. The DS4266 is a 266MHz crystal oscillator designed to support high-performance DDR memory applications that require a stable, low-jitter, and tight duty-cycle clock source. The device pro ...
... The DS4266 surface-mount ceramic crystal oscillator is part of Maxim’s DS4-XO crystal oscillator product family. The DS4266 is a 266MHz crystal oscillator designed to support high-performance DDR memory applications that require a stable, low-jitter, and tight duty-cycle clock source. The device pro ...
Uses of the Astable Multivibrator
... • pins 4 and 8 are shorted and then tied to supply +Vcc, output (VOUT is taken form pin 3; • pin 2 and 6 are shorted and the connected to ground through capacitor C, ...
... • pins 4 and 8 are shorted and then tied to supply +Vcc, output (VOUT is taken form pin 3; • pin 2 and 6 are shorted and the connected to ground through capacitor C, ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.