0.5μm InP DHBT Technology for 100GHz+ Mixed Signal Integrated
... After fabrication, the static and dynamic frequency dividers were measured at room temperature on a wafer probe station. A conventional 50GHz CW source was used for low frequency measurement. Testing beyond 50GHz in the V, W and D-bands was performed with combination of low frequency source and freq ...
... After fabrication, the static and dynamic frequency dividers were measured at room temperature on a wafer probe station. A conventional 50GHz CW source was used for low frequency measurement. Testing beyond 50GHz in the V, W and D-bands was performed with combination of low frequency source and freq ...
200-MHz General Purpose Clock Buffer, PCI-X
... Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such informati ...
... Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such informati ...
14-Output Clock Generator with Integrated 2.0 GHz VCO AD9516-3
... and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or ...
... and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or ...
AVR1505
... the XMEGA A has a pipelined architecture. This means that a new analog voltage can be sampled each ADC clock cycle. Thus, a new ADC measurement can be started while other ADC measurements are ongoing. The result is that the conversion rate is much higher than the conversion time. ADC measurements ca ...
... the XMEGA A has a pipelined architecture. This means that a new analog voltage can be sampled each ADC clock cycle. Thus, a new ADC measurement can be started while other ADC measurements are ongoing. The result is that the conversion rate is much higher than the conversion time. ADC measurements ca ...
Evaluate: MAX11040K MAX11040K Evaluation Kit/Daughterboard General Description Features
... delay for the input channels. Output Data Rate Control There are three panels in the Output Data Rate Control group box, and each one of them has a different way to set up the data rate of the IC. The user can select one of them by checking the corresponding radio button on the left of the panel. To ...
... delay for the input channels. Output Data Rate Control There are three panels in the Output Data Rate Control group box, and each one of them has a different way to set up the data rate of the IC. The user can select one of them by checking the corresponding radio button on the left of the panel. To ...
a Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter AD9243*
... The input of the AD9243 is highly flexible, allowing for easy interfacing to imaging, communications, medical, and dataacquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) ...
... The input of the AD9243 is highly flexible, allowing for easy interfacing to imaging, communications, medical, and dataacquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) ...
AN4881, MPC57xx SAR ADC Implementation and Use
... Any SAR ADC will have two phases: sampling phase and conversion phase. During the sampling phase the input has to settle to the less than or equal to quantization level, i.e. 0.5 LSB. In the sampling phase, the sample and hold switch is closed, thereby charging the internal SAR ADC capacitors. Durin ...
... Any SAR ADC will have two phases: sampling phase and conversion phase. During the sampling phase the input has to settle to the less than or equal to quantization level, i.e. 0.5 LSB. In the sampling phase, the sample and hold switch is closed, thereby charging the internal SAR ADC capacitors. Durin ...
TLC2554 数据资料 dataSheet 下载
... This terminal controls the start of sampling of the analog input from a selected multiplex channel. A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. This input is independent from SCLK and works when CS ...
... This terminal controls the start of sampling of the analog input from a selected multiplex channel. A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. This input is independent from SCLK and works when CS ...
AD9241 Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter
... CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid implementations at a fraction of the power consumption and cost. It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An ...
... CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid implementations at a fraction of the power consumption and cost. It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An ...
6-Output Clock Generator with Integrated 2.5 GHz VCO AD9518-1 Data Sheet
... The AD9518-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. ...
... The AD9518-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. ...
EFFICIENT CONTROL OF THE SERIES RESONANT CONVERTER FOR HIGH FREQUENCY OPERATION
... limits of switching frequency are pushed. The goal of this thesis is to address two areas that practically limit the achievable switching frequency of resonant topologies. Traditional control methods based on single cycle response are impractical at high frequency; forcing the use of pulse density m ...
... limits of switching frequency are pushed. The goal of this thesis is to address two areas that practically limit the achievable switching frequency of resonant topologies. Traditional control methods based on single cycle response are impractical at high frequency; forcing the use of pulse density m ...
SN74SSTU32866 数据资料 dataSheet 下载
... receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers ...
... receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers ...
evk-hades1210
... The isolated switched mode power supply is a regulated flyback DC-DC converter providing both isolated gate drivers with the positive and negative supply voltages required to drive the different types of FETs. The DC-DC converter function is fully integrated in CHT-HADES2P device. It provides as wel ...
... The isolated switched mode power supply is a regulated flyback DC-DC converter providing both isolated gate drivers with the positive and negative supply voltages required to drive the different types of FETs. The DC-DC converter function is fully integrated in CHT-HADES2P device. It provides as wel ...
MONITOR AND CONTROL STRATEGIES TO REDUCE THE IMPACT OF PROCESS
... Adaptive techniques try to overcome the impact of PVTA variations by adjusting circuits once they have been manufactured. Post-silicon tuning is an effective solution to reduce the distribution of maximum clock frequency and power consumption, and thus, to improve Yield [26]. ...
... Adaptive techniques try to overcome the impact of PVTA variations by adjusting circuits once they have been manufactured. Post-silicon tuning is an effective solution to reduce the distribution of maximum clock frequency and power consumption, and thus, to improve Yield [26]. ...
Z8 Low-Voltage ROM MCU with Infrared Timers
... registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex wavef ...
... registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex wavef ...
Layout Design Guide
... geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depends on the type of PCB techno ...
... geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depends on the type of PCB techno ...
Nyquist-rate digital-to-analog converter
... string DACs have no Fig. 4 Three bit current steering flash DAC architecture (a) with unary weighted current sources, and (b) load driving ability. If the DAC output has an binary weighted current sources appreciable current draw, native implementation of the resistor this current is siphoned off of ...
... string DACs have no Fig. 4 Three bit current steering flash DAC architecture (a) with unary weighted current sources, and (b) load driving ability. If the DAC output has an binary weighted current sources appreciable current draw, native implementation of the resistor this current is siphoned off of ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.