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S&S (5ed): Sec. 7.2
S&S (6ed): Sec. 8.2
Active Load
In integrated circuits, it is difficult to fabricate resistors. Instead, amplifier configurations
typically use active loads (i.e. loads made with active devices). This can be done using a current
source configuration, i.e. having a current source as a load (instead of RD).
ro 2
Large Signal (Bias)
Small Signal
As can be seen from the above circuits, the current mirror reduces to a current source which
biases the transistor. For small signals, current mirror appears as a resistor, ro2 (See page 5-11),
i.e., RD = ro 2
Therefore (Note RG is left for completeness but does not exist in the above circuit)
Rin = RG
Ro = ro1 // ro 2
Avo = − g m1 ⋅ (ro1 // r o 2 )
Another advantage of active loads is that they allow for much larger gain.
For a CS amplifier biased with a RD , we have
VDS = VDD − I D ⋅ RD
(If biased with two voltages sources, replace VDD in above with VDD + VSS). Since
ECE102 Lecture Notes (Winter 2010)
7- 1
gm =
2 ⋅ ID
VGS − Vth
Avo = g m ⋅ (ro // RD ) ≤ g m ⋅ RD
Avo ≤
2 ⋅ I D ⋅ RD
2 ⋅VDD
≤
VGS − Vth VGS − Vth
The value of (VGS – Vth) is typically limited to > 50 mV (strong inversion assumption). As a
result, the maximum gain is 40⋅ VDD. Over the years with newer process generations, the supply
voltage has been lowered to 1.2V (reason: lower power consumption and needed to ensure
reliable operation when device sizes shrink).
With an active load:
Avo = g m1 ⋅ (ro1 // ro 2 )
Avo =
ro =
VA
ID
VA =
1
λ
V
VA
2 ⋅ ID
⋅ A =
VGS − Vth 2 ⋅ I D VGS − Vth
With VA ≈ 25 V, the gain can be up to around 500 (typically less though).
This can also be seen in the operating space of Q1 (below). A KVL through Q1 and Q2 provides
the “load curve” of the circuit. Operating point for the amplifier is between points A and B. The
inverse of the slope of this line is the effective RD seen by the CS amplifier (ro2 in this case). The
figure shows that much larger VDD would be required if we try to achieve the same gain with a
discrete resistor (passive load).
Clearly, a current mirror can also be used as an active load for other MOS amplifier
configurations.
RD = r02
VDD→
ECE102 Lecture Notes (Winter 2010)
7- 2
Cascode
A Cascode amplifier is a combination of a
CS and CG amplifier
vo
v2
Letting RL → ∞ (to get the open-loop gain) and using node-voltage method (note vgs2 = -v2)
− g m2 ⋅ v2 +
g m1 ⋅ vi +
Avo =
Thus,
vo − v2
=0
ro 2
⇒ v2 =
v2
=0
ro1
⇒ ro1 g m1 vi = −
1
1 + g m 2 ⋅ ro 2
⋅ vo
1
1 + g m 2 ⋅ ro 2
⋅ vo
vo
= − g m1 ⋅ ro1 ⋅ (1 + g m 2 ⋅ ro 2 ) ≈ − g m1 ⋅ ro1 ⋅ g m 2 ⋅ ro 2
vi
The output impedance of the amplifier can be found by “zeroing” the input voltage (vi = vsg1 = 0)
and finding the effective resistance between vo and the ground. Since vsg1 = 0, the first
controlled source becomes an open circuit as is shown below. Because of the second current
source, we need to find Ro by attaching a voltage source, vx, between vo and the ground and
calculating ix.
R + r0 + g m ⋅ R ⋅ r0
AC
R
AC
v gs 2 = − ro1 ⋅ i x
KVL:
v x = (ix − g m 2 ⋅ v gs 2 )ro 2 +ro1 ⋅ i x = (ix + g m 2 ⋅ ro1 )ro 2 +ro1 ⋅ ix = i x (ro 2 +g m 2 ⋅ ro1ro 2 +ro1 )
Ro =
vx
= ro1 + ro 2 + g m 2 ⋅ ro1 ⋅ ro 2 ≈ g m 2 ⋅ ro1 ⋅ ro 2
ix
ECE102 Lecture Notes (Winter 2010)
7- 3
To better understand the impact of the CG part of the Cascode amplifier, we consider an
alternative approach to computing Avo. We note that the output stages of a voltage amplifier and
a transconductance amplifier (below) are equivalent: the voltage amplifier output is in Thevenin
form and the transconductance amplifier output is in Norton form, with Ro being the same and
the “short-circuit” transconductance, Gm is related to open-loop voltage gain, Avo. through
Avo = G m Ro
This equivalency leads to another method to compute Avo through computing Gm which may be
easier in some problems and/or provides additional insight. For example, for the Cascode
amplifier above,
Ignoring ro1 and ro2, one finds (note the direction of io)
io = −G m vi = −G m v gs1 = g m1v gs1 = g m 2 v gs 2
G m = − g m1
Avo = G m Ro = − g m1 .g m 2 ⋅ ro1 ⋅ ro 2
This shows that Gm for the cascode amplifier is the same for the first stage CS amplifier (see
small circuit model in page 7-3), the CG amplifier acts as a current buffer increasing the output
resistance and overall open-loop gain of the circuit.
If we do not ignore ro1 and ro2,
io = −G m v i = −G m v gs1 = g m 2 ⋅ v gs 2 +
v gs 2
= g m1 ⋅ v gs1 −
ro 2
1 1
(g m2 +
+ ).v gs 2 = g m1 ⋅ v gs1
ro 2 ro1
v gs 2
g m1 ro1 .(1 +ro 2 g m 2 )
Gm = − g m 2
=−
v ogs1
ro1 + ro 2 + g m 2 ⋅ ro1 ⋅ ro 2
v gs 2
ro1
Which would leads the same expression for Avo in page 7-3.
ECE102 Lecture Notes (Winter 2010)
7- 4
Cascode current steering circuits
Since the current source will also need to implement with MOSFETs, it is important to also
increase its small signal resistance. This is possible using a cascode transistor there as well.
Approximate:
R + r0 + g m ⋅ R ⋅ r0
AC
R
AC
R3 = ro 2 + ro 3 + g m 3 ⋅ ro 2 ⋅ ro 3 ≈ g m 3 ⋅ ro3 ⋅ ro 2
Differential pair with active load and differential output
If a differential output is necessary (e.g. the
output of the difference amplifier is attached to
another difference amplifier), the active load is a
potion of current mirror circuit (drain-gate
connected transistor part lead to a constant bias
voltage of VG. As can be seen the circuit is
symmetric and behave as a difference amplifier
with resistors RD. As such,
Ad = − g m ⋅ ( R D || ro1 ) = − g m ⋅ ( ro1 || ro 3 )
ACM = 0
ECE102 Lecture Notes (Winter 2010)
7- 5
Differential pair with active load and single ended output
If a single-ended output is required, a current mirror pair can be utilized as the active load (Q3
and Q4 are identical and Q1 and Q2 are identical). Note that this circuit is NOT symmetric
anymore.
Bias: Since VGS3 = VGS4 , ID3 = ID4 = I/2 = ID1=ID2 as is shown (Bias will be symmetric)
ECE102 Lecture Notes (Winter 2010)
7- 6
Small signal analysis:
Because the circuit is NOT symmetric, we cannot use half circuit. However, since gate currents
are zero, the drain-gate connected transistor will act as a diode-connected transistor and the small
signal circuit becomes:
vo
v gs 3 = − g m1 .(ro1 || ro 3 ||
Node vo
+ g m2 ⋅
g
v
1 vd
). ≈ −( m1 ). d
g m3 2
g m3 2
v d vo
v
+
+ g m3 ⋅ v g 3 + o = 0
2 ro 2
ro 4
Noting that gm1 = gm2 , we get
Ad = − g m12 ⋅ (ro 2 // ro 4 )
The common mode gain can be found in a similar manner (see Sedra & Smith 6ed, sec. 8.5.4)
ECE102 Lecture Notes (Winter 2010)
7- 7
Two-stage CMOS amplifier
v1
= − g m12 ⋅ (ro 2 // ro 4 )
vd
⇒
Ad =
vout
= − g m 6 ⋅ (ro 6 // ro 7 )
v1
vout
= g m12 ⋅ (ro 2 // ro 4 ) ⋅ g m 6 ⋅ (ro 6 // ro 7 )
vd
(We will discuss high-frequency operation and Miller Theorem in the next section)
Now lets assume the dominant pole is created by Miller capacitor CC. Remember, the Miller
effect causes this capacitor to appear larger.
Ceq = CC ⋅ (1 − A2 ) = CC ⋅ (1 + g m 6 ⋅ ( ro 6 // ro 7 )) ≈ CC ⋅ g m 6 ⋅ ( ro 6 // ro 7 )
Rsig = ro 2 // ro 4
ω3dB ≈
1
1
=
Rsig ⋅ Ceq CC ⋅ g m 6 ⋅ (ro 6 // ro 7 ) ⋅ (ro 2 // ro 4 )
The GBW is: GBW = Ad ⋅ ω3dB =
g m12
CC
ECE102 Lecture Notes (Winter 2010)
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