Download Low voltage, scalable nanocrystal FLASH memory

Low voltage, scalable nanocrystal FLASH
memory fabricated by templated self
assembly
 Presented by:
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10/11/2005
Michael Logue
Pierre Emelie
Zhuang Wu
J.R. Edwards
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
10/11/2005
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Introduction to Flash Memory
 Flash memory is a type of EEPROM chip
 EEPROM (Electrically Erasable
Programmable Read-Only Memory)
 Flash memory chips don’t have to be removed
from the circuit board and exposed to UV light to
be erased
 Flash memory is “non-volatile” memory
 Meaning that the data stored in memory is
retained even when it is not being powered
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How Flash Memory Works
 A Flash chip has a grid of columns and
rows with a cell that has two transistors
at each intersection
 The transistors are separated from each
other by a thin oxide layer. One is
known as the floating gate and the other
is the control gate.
 The floating gates only link to the row, or
wordline, is through the control gate. As
long as this link is in place, the cell has a
value of 1. To change the value to a 0
requires a curious process called
Fowler-Nordheim tunneling.
 Tunneling is used to alter the placement
of electrons in the floating gate.
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How Flash Memory Works
 Tunneling (continued)
 An electrical charge, usually 10-13 V, is applied to the floating
gate. The charge comes from the column, or bitline, enters the
floating gate and drains to ground
 This charge causes the floating gate transistor to act like an
electron gun. The excited electrons are pushed through and
trapped on other side of the thin oxide layer, giving it a negative
charge. These negatively charged electrons act as a barrier
between the control gate and the floating gate.
 If the flow through the gate is greater than 50 percent of the
charge, it has a value of 1. When the charge passing through
drops below the 50-percent threshold, the value changes to 0.
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How Flash Memory Works
 Erasing
 The electrons in the cells can be returned to normal ("1") by
applying an electric field. Flash memory uses in-circuit wiring to
apply the electric field either to the entire chip or to
predetermined sections known as blocks. Flash memory works
much faster than traditional EEPROMs because instead of
erasing one byte at a time, it erases a block or the entire chip,
and then rewrites it.
 Flash chips are made on silicon wafers using a process
that takes 6-12 weeks and hundreds of manufacturing
steps. The process requires multiple uses of
photolithography, etch, diffusion, thin film deposition,
planarization, and ion implantation.
 The width of the Control/Floating Gates will average between 12
and 25nm, depending on the process technology and the density
of the number of cells on a chip (measured in megabytes)
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Benefits of Flash Memory
 Provides a shock insensitive, non-volatile
form of data storage.
 Has miniscule energy requirements
 Flash is small, light and relatively
inexpensive
 Flash is noiseless, has no moving parts,
and allows faster access than a hard disk
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Limitations of Flash memory
 Cost per megabyte of a hard disk is
drastically cheaper and capacity is
substantially more
 Tolerates a limited number of write cycles
 This is because electrical charges provide
permanent retention of transistor states.
These charges are isolated by oxide layers,
which help maintain consistent state, but also
dissipate over time.
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Common Failure Mechanisms
 Improperly specified speed ratings used in flash
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card
Poor interconnects and construction in card
Flash card connector failure
Flash card structural failure due to excessive
stress
Inserting card and applying a voltage while the
card is wet
Tunnel oxide degradation-ultimate wear out
mechanism
Package interconnect failure
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Types of Flash Memory
 Cell Types
 The way the cells actually work depend on whether they are
NOR or NAND types. NOR flash is linearly addressable using a
conventional processor, and thus also works for delivering
executable code. However it’s slower than NAND, and requires
more energy to read and write. It’s used primarily for burning
and accessing programs in firmware.
 NAND also scales better than NOR, allowing for 4 and 8 GB
products, and works from a command-based bus interface.
However memory controller overhead is higher and more
complex, and conventional processors require translation
routines to enable them to read and write to NAND flash memory
 Chip Types
 Computers BIOS chip, SmartMedia, CompactFlash, Memory
Stick, PCMCIA Type I and II, memory cards for video game
consoles
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Applications
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Computer BIOS Chip
Digital Cameras
Appliances
Video and stereo
equipment
 Automobiles
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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Device Fabrication of Scalable
Nanocrystal Flash Memory
 Silicon nanocrystals were defined using diblock
copolymer thin film self assembly
 Process involves spin-coating a dilute polymer
solution and annealing to promote phase separation
into nanometer-scale polymer domains
 The diblock copolymer was composed of polystyrene
(PS) and poly(methyl methacrylate) (PMMA). Their
molecular weight ratio produces hexagonally-closedpacked PMMA cylinders in a PS matrix.
 The PMMA is removed with an organic solvent,
leaving a porous PS film. This film is used as a
sacrificial layer to define nanocrystals at sublithographic dimensions.
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Device Fabrication of Scalable
Nanocrystal Flash Memory
 Fig 1-(a )form porous PS film on
thermal oxide hardmask; (b) etch PS
pattern onto oxide; (c) grow program
oxide (2-3nm) and conformally
deposit a:Si; (d) etch a:Si using an
anisotropic RIE process
 The nanocrystals’ dimensions are the
same as the original polymer film,
20nm(+/-10%), and a center-center
spacing of 40nm
 The nanocrystal density was found to
be 6.5*1010/cm2. Using polymers with
lower molecular weight can produce
smaller dimensions
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Device Fabrication of Scalable
Nanocrystal Flash Memory
 The devices are
completed by depositing
a control oxide (7-12nm)
on top of the nanocrystal
array, then depositing,
doping and patterning the
polysilicon gate. A single
metal layer is used to
contact the gate.
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Device Fabrication of Scalable
Nanocrystal Flash Memory
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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Performance of Nanocrystal
FLASH memory
 “Writing”: injection of charges into
the nanocrystals
 “Erasing”: expelling charge from
the nanocrystals
 High frequency CV measurements
are shown for device E
 Stored charge shifts the device flat
band voltage VFB
 VW = -4 V → ΔVFB > 0.5 V
 Potentially low voltage operation
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Performance of Nanocrystal
FLASH memory
 Larger VFB shifts are achieved
using larger VW (read voltage -2 V
and write time of 20 s)
 Magnitude and slope of ΔVFB
depend on:
- program oxide thickness tprog
- control oxide thickness tctrl
 Control of the fabrication leads to
control of device performance
 Control device F (with no
nanoctrystals) show no ΔVFB at
|VW| < 9 V
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Performance of Nanocrystal
FLASH memory
 At high |VW|, charge begins to leak
through the control oxide
 ΔVFB saturates
• Device breakdown is set by the
control oxide thickness tctrl
 Again, control of the fabrication
leads to control of device
performance
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Performance of Nanocrystal
FLASH memory
 Effect of the program oxide
thickness tprog (for fixed tctrl) is
shown on this figure
 Devices with tprog = 3 nm (C and D)
show larger ΔVFB than tprog = 2 nm
(A and B)
 Due to the larger voltage on the
floating gate for the same VW
• ΔVFB increases with write time for a
fixed VW
• Write time of 50 µs → ΔVFB ~ 0.2 V
• Devices are fully erased with a 100
µs erase voltage pulse of +4 V
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Performance of Nanocrystal
FLASH memory
 Stability of the written and erased
memory states is measured on this
figure (VW = -6 V and VE = +4 V)
 Small signal capacitance at -2 V is
measured as a function of time and
converted to ΔVFB by tracking along
a CV curve
 Up to 500 s, ΔVFB remained larger
for tprog = 3nm (C and D) than for
tprog = 2 nm (A and B)
 Logarithmic fit for A and B devices
projects retention time > 106 s
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Performance of Nanocrystal
FLASH memory
 Device endurance is measured
using (VW = -6 V, 50 µs) and
(VE = +4 V, 50 µs)
 Read voltage of -2 V
 Write/erase window remains
unchanged out to 109 cycles
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Performance of Nanocrystal
FLASH memory - Conclusion
 Charge is stored in small islands of Si rather than in a
continuous floating gate
 Precise control of nanocrystal size and position can be
achieved
 Control of the device fabrication (especially the dielectric
thickness) makes things easier in terms of
manufacturability, scalability and control of the device
performance
 Devices exhibit low voltage memory operation with
promising retention and endurance properties
=> Nanocrystal FLASH memory may improve reliability in
FLASH devices
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Performance of Nanocrystal
FLASH memory - Limitations
 Nanocrystal storage does not change the transistor
physics: it’s the same mechanism for read and write
It does not solve all the problems associated with FLASH
devices mentioned earlier
• It will probably not help FLASH memory scale to smaller
geometries
• It will probably never be used for FLASH memory
devices but it shows a novel fabrication technique with
promising applications
• FLASH memory will probably be replaced in the next ten
years by other emerging non-volatile memory
technologies
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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CBRAM
Conductive Bridging RAM
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Basic principles
 On/off states correspond to presence or
lack of a conductive bridge between
electrodes.
 Writing/erasing follows the formation and
removal of the bridge;
 Reading is done by measuring resistance
between electrodes.
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How to achieve the bridges
 a redox reaction drives metal ions in the
chalcogenide glass forming metal-rich clusters
that lead to a conductive bridge between the
electrodes.
 Writing voltage 250mV, writing current 2µA
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How to remove a bridge
 The memory element can be switched
back to the OFF-state by applying a
reverse bias voltage. In this case metal
ions are removed and due to that size and
number of metal-rich clusters are reduced
resulting in an erased conductive bridge
 Here, the erasing voltage is -80mV
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CBRAM cell resistance and threshold
voltage as a function of storage
material area.
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CBRAM data retention measured
at elevated temperatures.
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The Ferro-electric RAM
 FRAM is an array of ferroelectric
capacitors, with a thin ferroelectric film in
between, which is typically made of lead
zirconate titanate (PZT).
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 The bit is read by applying an electric field
on the memory capacitor. The amount of
charge needed to flip the memory cell to
the opposite state is measured and the
previous state of the cell is revealed.
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Re-write
 The read operation destroys the memory
cell state, and has to be followed by a
corresponding write operation, in order to
write the bit back.
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Magneto-resistive RAM
 A cell is made up of three major parts
 One of the two plates is a permanent magnet set
to a particular polarity, the other's field will
change to match that of an external field
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 Data is written to the cells by creating an
induced magnetic field in a grid of write lines
above and below the cells
 current creates an induced magnetic field, which
flips the polarity of the "writable" plate to match
the induced field
 if the two plates have the same polarity this is
considered to mean "0", while if the two plates
are of opposite polarity the resistance will be
higher and this means "1".
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 By measuring the resistance along the
read lines, the state (field) of any particular
cell can be determined
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
10/11/2005
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ORAM
 Organic Random Access Memory
 Reversible resistive operation by voltage application
 Requires boosted voltage for WRITE operation
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ORAM Scaling
 Resistance ratio
decrease with device
area
 Extrapolation indicates a
resistance ratio of >10 at
20x20nm2
 Switching voltages are
independent of device
area
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ORAM Performance
 Promising distribution
functions for threshold
voltage
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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PCRAM
 Phase Change Random Access Memory
 Chalcogenide glass (GexSbyTez)
 Same material family as used in rewritable
CD/DVD disks
 Rather than laser beam, uses current to heat
material
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Basic PCRAM Structure
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PCRAM Characteristics
 Short, high current pulse
to make amorphous state
(high resistance RESET
state)
 Longer, medium current
pulse to make
polycrystalline state (low
resistance SET state)
 Low current pulse to
differentiate state (READ
state)
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PCRAM RESET Pulse
 Temperature of
programmed volume of
phase-change material
exceeds the melting point
 Eliminates the
polycrystalline ordering
 Device quenches to
“freeze in” the disordered
structural state
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Cho et al., http://www.epcos.org/pdf_2004/17paper_cho.pdf
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PCRAM SET Pulse
 Temperature of
programmed volume
of phase-change
material maintained in
rapid crystallization
range
 Maintained for a
sufficient time for
crystal ordering
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PCRAM READ Pulse
 Low current pulse,
with essentially no
joule heating
 Current used to sense
resistance
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PCRAM Scaling
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PCRAM Scaling
 Normalized radial
temperature
distribution
 Heat plume scaled
down with device
diameter
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Outline
 Traditional Flash Devices
 Introduction to Flash memory
 Performances, Applications, Limitations
 How to improve Flash memory
 Nanocrystal Device fabrication
 Performance of Nanocrystal FLASH memory
 Emerging Nonvolatile Memory Technologies
 CBRAM, FeRAM, MRAM, ORAM, and PCRAM
 Final Conclusions
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Conclusion
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