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DIGITAL ELECTRONICS II
Chapter 0
ComBinaTionaL loGic deSign
deSiGn conCepTs
– Design Procedure
– CAD Tools
– Propagation Delay
– Programmable Logic
Block Diagram of Combinational
Circuit
Design Topics
Modern digital design
– Techniques & tools for complex circuits &
systems design
Some important concepts
– CAD tools, HDL, logic synthesis, design
hierarchy, top-down design
Design Hierarchy
Approach to design complex digital system
– E.g VLSI circuits
“Divide & Conquer” approach
– Break up circuit into smaller pieces / blocks
– Interconnect the blocks to form complete
circuit
Hierarchical Design

To control the complexity of the function mapping inputs
to outputs:
◦ Decompose the function into smaller pieces called blocks
◦ Decompose each block’s function into smaller blocks, repeating
as necessary until all blocks are small enough
◦ Any block not decomposed is called a primitive block
◦ The collection of all blocks including the decomposed ones is a
hierarchy

Example: 9-input parity tree (see next slide)
◦ Top Level: 9 inputs, one output
◦ 2nd Level: Four 3-bit odd parity trees in two levels
◦ 3rd Level: Two 2-bit exclusive-OR functions
◦ Primitives: Four 2-input NAND gates
◦ Design requires 4 X 2 X 4 = 32 2-input NAND gates
Example : 9 – input odd
function
Design Hierarchy Concepts
1. Reduces complexity of schematic
diagram
2. Reuse of blocks
– One block is used multiple times
– Cascaded
– “Functional blocks”
Diagrams Representing
Hierarchy
Top – down Design
Describe circuit function by text, including
constraints on cost, performance &
reliability
Divide circuit into hierarchy levels
Bottom – up Design
Used to design certain portions of big
design
Starts with design of functional blocks
– So that functional blocks can be reused
multiple times
Top-Down versus Bottom-Up




A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
Designs usually proceed from both directions
simultaneously
◦ Top-down design answers: What are we building?
◦ Bottom-up design answers: How do we build it?
Top-down controls complexity while bottom-up focuses
on the details
Computer Aided Design (CAD)
Schematic capture tools
– Drawing of blocks & interconnections at all
hierarchy levels
Libraries of graphic symbols
– Ready – made primitives & functional blocks
design
Libraries in Max Plus II
Prim
– Basic Fbs
Mf
Mega_lpm
Edif
Own libs from self-created symbols
CAD
Logic simulator
– To verify behavior & timing of each hierarchy
blocks / complete circuit
– Apply a set of inputs to determine the outputs
Hardware Description Language
Important to design complex circuits
Similar to other programming languages
Describe hardware structures & behavior
Power of HDL
Used to represent
– Schematic information
– Boolean equations
– Truth tables
Can use hierarchical design approach
– High – level description can be partitioned into
lower – level descriptions
Logic synthesis
– An HDL description written at an intermediate
level called
Register Transfer Language (RTL)
– It can be converted into interconnection of
primitive components that forms the circuit
HDLs are portable across CAD design
tools
HDL Languages
VHDL
– Very High – Speed ICs
– Developed by DoD, US
– IEEE standard
Verilog HDL
– IEEE standard
AHDL
What have been discussed
Design hierarchy
– Top – down
– Bottom – up
CAD (Computer Aided Design)
HDL (Hardware Description Language)
Logic synthesis
Analysis Procedure
Analysis
– To determine the function of a circuit
Derive Boolean equation
Derive truth table
Analyze this logic diagram
T3
T1
T2
T4
T5
Boolean Equation
T1 =BC
T2 =AB
T3 =A+T1=A+BC
T4 =T2 + D = AB + D
T5 =AB+D
F1 = (A+BC) + (AB + D)
F2 = T5 = AB + D
Analyze this Binary Adder
R1
R2
R3
C
Truth Table
X
Y
Z
C
C
R1
R2
R3
S
Truth Table
X
Y
Z
C
C
R1
R2
R3
S
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
0
1
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
1
0
1
Logic Simulation
A fast and accurate method of analyzing a
combinational circuit
Using simulator software
Results :
– Waveforms
– A complete truth table
– Part of a truth table
Logic Simulation
How is the circuit described in the software
?
– Schematics
– HDL
Schematic for Binary Adder in
Xilinx
Waveforms for Binary Adder
Simulation in Max Plus II
Waveforms in MaxPlus II
Point to ponder….
Why do we compare the simulation results
vs the theoretical results?
Design Procedure
Given : Specifications of the problem
1. Determine input & output
2. Derive truth table
3. Obtain Boolean equation (K-map)
4. Draw schematics
5. Verify design
Design of BCD to Excess – 3
Code Converter
Specifications :
Input in decimal numbers, 0 – 9, in binary
form
Output is excess – 3 code
E.g
– Decimal = 5 (101)
– Excess – 3 code = 5 + 3 = 8 (1000)
BCD  Excess – 3
Step 1.
– Input : 0 to 9, 4 – bit binary code
 A, B, C, D
– Output : 3 to 12, 4 – bit binary code
 W, X, Y, Z
BCD  Excess – 3
Step 2 : Truth Table
Dec
0
1
2
3
4
5
6
7
8
9
A
0
0
0
0
0
0
0
0
1
1
B
0
0
0
0
1
1
1
1
0
0
C
0
0
1
1
0
0
1
1
0
0
D
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
0
1
1
1
1
0
0
0
0
1
Y
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
BCD  Excess – 3
Step 3 : Boolean equation
W
X
Y
Z
= A + BC + BD
= BC + BD + BCD
= CD + CD
=D
BCD  Excess – 3
Step 4 : Schematic diagram
BCD  Excess – 3
Step 4 : Schematic diagram
BCD  Excess – 3
Step 5 : Verify that schematic diagram
agrees with truth table
Design of BCD to 7 –segment
decoder
Specifications :
Input in decimal numbers, 0 – 9, in binary
form
7 Outputs – to display input number
7 – segment Display
BCD to 7 –segment decoder
Step 1 :
BCD to 7 – segment decoder
Step 2 : Truth Table
A
0
B
0
C
0
D
0
a
1
b
1
c
1
d
1
e
1
f
1
g
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
0
1
1
0
1
1
0
1
0
0
0
1
0
0
1
All other inputs
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
Exercise
A traffic light system has the following
specifications for a part of its controller. There
are 3 parallel lanes, each with its own red /
green light. One of these lanes, the priority lane,
is given priority for a green light over the other 2
lanes. On the other hand, an alternating scheme
is used for the other 2 lanes, which are left and
right lane. Design the circuit that determines
which light is to be green at a particular time.
The specifications for the controller are as
follows :
Exercise
Inputs :
PS – Priority Lane Sensor ( car present = 1; car absent = 0 )
LS – Left Lane Sensor ( car present = 1; car absent = 0 )
RS – Right Lane Sensor ( car present = 1; car absent = 0 )
AS – Alternating Signal ( select left = 1; select right = 0 )
Outputs :
PL – Priority Lane Light ( green = 1; red = 0 )
LL – Left Lane Light ( green = 1; red = 0 )
RL – Right Lane Light ( green = 1; red = 0 )
Exercise
1. If there is a car in the priority lane, PL = 1.
2. If there are no cars in the priority lane and the right lane, and there
is a car in the left lane, LL = 1.
3. If there are no cars in the priority lane and in the left lane, and there
is a car in the right lane, RL = 1.
4. If there is no car in the priority lane, there are cars in both the left
and right lanes, and AS = 1, then LL = 1.
5. If there is no car in the priority lane, there are cars in both the left
and right lanes, and AS = 0, then RL = 1.
6. If any PL, LL or RL is not specified to be 1 above, then it has value
0.
Propagation Delay
PROPAGATION DELAY
Definition:
 The delay time for the change in value of a
signal to propagate from input to output.
input
output
delaY vs sPeeD
“Operating Speed” is inversely
proportional to the longest propagation
delay.
Propagation Delay Parameters
Propagation delay is the time for a change on an input of
a gate to propagate to the output.
Delay is usually measured at the 50% point with respect
to the H and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
An HL input transition causes:
– an LH output transition if the gate inverts and
– an HL output transition if the gate does not invert.
Propagation Delay Parameters …
t PHL The high-to-low propagation time
the delay measured from the reference
voltage on the input voltage, IN, to the
reference voltage on the output voltage,
OUT, with the output voltage going from
H to L.
Propagation Delay Measurements
for an Inverter
Propagation delays measured at the midpoint between the L and H values
Propagation Delay Parameters …
t PLH The low-to-high propagation time
the delay measured from the reference
voltage on the input voltage, IN, to the
reference voltage on the output voltage,
OUT, with the output voltage going from
L to H.
Propagation Delay Parameters …
t PD
The propagation delay time
the maximum of the two delays,
t PLH and t PHL .
Propagation Delay Measurement Exercise
OUT (volts)
IN (volts)
Find tPHL, tPLH and tpd for the signals given
t (ns)
1.0 ns per division
ProGrammaBle loGic
Implementation Technology
Programmable Implementation Technologies
– Read-Only Memories, Programmable Logic Arrays,
Programmable Array Logic
Technology mapping to programmable logic
devices
Why Programmable Logic?
Facts:
– It is most economical to produce an IC in large
volumes
– Many designs required only small volumes of ICs
Need an IC that can be:
– Produced in large volumes
– Handle many designs required in small volumes
A programmable logic part can be:
– made in large volumes
– programmed to implement large numbers of different
low-volume designs
Programmable Logic - Additional Advantages
Many programmable logic devices are fieldprogrammable, i. e., can be programmed outside of
the manufacturing environment
Most programmable logic devices are erasable and
reprogrammable.
– Allows “updating” a device or correction of errors
– Allows reuse the device for a different design - the ultimate in
re-usability!
– Ideal for course laboratories
Programmable logic devices can be used to prototype
design that will be implemented for sale in regular
ICs.
– Complete Intel Pentium designs were actually prototype with
specialized systems based on large numbers of VLSI
programmable devices!
Technology Characteristics
Permanent - Cannot be erased and reprogrammed
Mask programming
Fuse
Antifuse
Reprogrammable
– Volatile - Programming lost if chip power lost
Single-bit storage element
– Non-Volatile
Erasable
Electrically erasable
Flash (as in Flash Memory)
– Build lookup tables
Storage elements (as in a memory)
– Transistor Switching Control
Stored charge on a floating transistor gate
– Erasable
– Electrically erasable
– Flash (as in Flash Memory)
Storage elements (as in a memory)
Programmable Configurations
Read Only Memory (ROM) - a fixed array of
AND gates and a programmable array of OR
gates
Programmable Array Logic (PAL) - a
programmable array of AND gates feeding a
fixed array of OR gates.
Programmable Logic Array (PLA) - a
programmable array of AND gates feeding a
programmable array of OR gates.
Complex Programmable Logic Device (CPLD)
/Field- Programmable Gate Array (FPGA)
The End