Download AN-1363: Meeting Biasing Requirements of

AN-1363
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Meeting Biasing Requirements of Externally Biased RF/Microwave Amplifiers with
Active Bias Controllers
by Kagan Kaya
INTRODUCTION
Radio frequency (RF) and microwave amplifiers provide their
best performance under specific bias conditions. The quiescent
current established by the bias point affects critical performance
metrics such as linearity and efficiency. While some amplifiers
are self biased, many devices require external biasing using
multiple supplies that must be sequenced properly for safe
operation.
This application note provides an overview of bias sequencing
requirements and the effects of using various bias conditions.
It presents an elegant solution for biasing amplifiers using active
bias controller such as the HMC980, HMC980LP4E, HMC981,
HMC981LP3E, HMC920LP5E, and all externally biased
RF/microwave amplifiers.
Rev. 0 | Page 1 of 16
AN-1363
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1 Operating Principles .....................................................................8 Revision History ............................................................................... 2 Adjusting the Default VNEG and VGATE Threshold Values.9 Biased Amplifiers.............................................................................. 3 Reducing VGATE Rise Time .................................................... 10 Power Supply Sequencing ........................................................... 3 Daisy-Chain Configuration ...................................................... 11 Self Biased Amplifiers .................................................................. 3 Testing the Functionality of the Active Bias Controller ........ 12 Externally Biased Amplifiers ...................................................... 3 Biasing Multiple DUTs by a Single Active Bias Controller ... 12 Cascode Amplifiers ...................................................................... 5 Sample Active Bias Controler Application Circuits............... 12 Using Active Bias Controllers to Bias Externally Biased
Amplifiers ...................................................................................... 6 Conclusion....................................................................................... 16 REVISION HISTORY
7/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Application Note
AN-1363
BIASED AMPLIFIERS
Analog Devices, Inc., has a wide selection of RF amplifier types.
Many RF amplifiers are based on a depletion mode, pseudomorphic, high electron mobility transfer (pHEMT) technology.
The transistors used in this process typically require supplies
for the drain pins and gate pins. This quiescent drain current is
a function of the gate voltage. See Figure 1 for the typical IV
characteristics of a typical field effect transistor (FET) process.
700
600
VGS = 0V
IDS (A)
12 GND
GND 2
11 GND
RFIN 3
10 RFOUT
GND 4
9
NIC 8
GND 1
GND
PACKAGE
BASE
GND
13164-002
14 NIC
13 VDD3
16 VDD1
Self biased amplifiers have an internal circuit that sets the optimal
bias point suitable for operation. These amplifiers tend to be best
suited for broadband, low powered applications. See Figure 2 for
a typical pinout of a self biased amplifier.
Figure 2. Typical Pinout for a Multistage Self Biased Amplifier with Multiple
Bias Pins
While self biased amplifiers are simple to use, they may not provide
the best performance because the internal resistive bias circuit
cannot fully compensate for lot, device, and temperature variations.
EXTERNALLY BIASED AMPLIFIERS
Externally biased amplifiers tend to provide higher performance
than self biased amplifiers under specific bias conditions. The
quiescent drain current of the amplifier affects parameters such
as power compression point, gain, noise figure, intermodulation
products, and efficiency. For these high performance externally
biased amplifiers, correctly sequencing the supplies is crucial for
safe and optimal performance.
This procedure also applies to other radio frequency integrated
circuits (RFICs), such as frequency multipliers, upconverters,
and downconverters. These products can require similar biasing
techniques. Table 1 lists externally biased RF products from
various product families.
500
400
300
Table 1. Externally Biased RF Devices
200
100
VGS = –2V
0
2
4
6
8
10
12
VDS (V)
13164-001
0
SELF BIASED AMPLIFIERS
NIC 7

Failing to follow the proper power supply sequencing
compromises the reliability of the device. Exceeding
breakdown voltage levels can result in instant failure.
Long term reliability degrades when out of bond
conditions are repeated multiple times, and the system is
stressed. In addition, continually violating the sequencing
pattern damages the on-chip protection circuitry and results
in long term damage, which can result in a failure in the field
operation.
Optimizing the bias level not only during power up and
power down but also during regular operation can improve
the performance of the RF amplifier, depending on the
configuration and the application requirements. For some
applications, changes can be made to the RF performance
of the amplifier to comply with different field scenarios. For
example, the output power can be increased for wider
coverage during rainy weather, or the output power can be
reduced during clear weather. The external gate control of
the amplifier can implement these arrangements.
15 VDD2

NIC 6
Power supply sequencing is critical while operating externally
biased amplifiers for the following reasons:
In real-world amplifiers, due to effects like channel length
modulation, these amplifiers can be broadly categorized into
two categories: self biased and externally biased amplifiers.
NIC 5
POWER SUPPLY SEQUENCING
Figure 1. Typical IV Characteristics of a Typical FET Process
As the gate to source voltage (VGS) increases, more electrons enter
the channel, resulting in a higher drain to source current (IDS).
Additionally, as the drain to source voltage (VDS) increases, the
drain to source current also increases (in the linear region)
due to the higher field force pulling the electrons.
Device Number
HMC1082LP4E
HMC1049 Bare Die
HMC7357LP5GE
HMC463
HMC996LP4E
HMC598
HMC1065LP4E
HMC6787ALC5A
HMC871LC5
Rev. 0 | Page 3 of 16
Product Family
Driver amplifier/medium power amplifier
Low noise amplifier
Power amplifier
Wideband distributed amplifier
Variable gain amplifier
Frequency multiplier chip
Downconverter
Upconverter
Optical modulator driver
AN-1363
Application Note
10 NIC
11 VDD
12 NC
Figure 3 shows the typical connections for the pins of an
externally biased amplifier and the corresponding transistor
pins. The pin mapping in Figure 3 is a simplified representation
of the amplifier.
The recommended bias sequence during power up for the
HMC1131 is the following:
GND 1
9 GND
RFIN 2
8 RFOUT
GND 3
7 GND
DRAIN
1.
2.
3.
4.
5.
GATE
PACKAGE
BASE
13164-005
NIC 6
VGG 5
NIC 4
SOURCE
GND
20 VDD4
19 NIC
21 VDD3
23 VDD1
22 VDD2
24 NIC
Furthermore, many externally biased amplifiers have multiple
stages to meet design requirements such as gain, bandwidth,
and power. Figure 4 shows a typical block diagram of the
HMC1131, which is a multistage externally biased amplifier.
17 GND
RFIN 3
16 RFOUT
1.5kΩ
18 NIC
1.5kΩ
NIC 1
14 NIC
NIC 12
NIC 10
VGG2 11
NIC 9
NIC 7
PACKAGE
BASE
GND
13164-008
13 NIC
VGG1 8
3.
4.
Turn the RF signal off.
Decrease VGG1 and VGG2 to −2 V to achieve an IDQ of
approximately 0 mA.
Decrease VDD1 through VDD4 to 0 V.
Increase VGG1 and VGG2 to 0 V.
In general, the recommended biasing sequence is similar for
most externally biased amplifiers. IDQ, VDDx, and VGGx values are
different for different devices. For GaAs devices, VGG is generally
set to −2 V or −3 V to turn off the amplifier, while that voltage
can be −5 V to −8 V for gallium nitride (GaN) amplifiers. Similarly,
VDDx can reach 28 V, even 50 V, for GaN devices, while it is
usually less than 13 V for GaAs amplifiers.
15 GND
NIC 6
1.
2.
When the gate voltage (VGGx) is −2 V, the transistors are
pinched off. Therefore, IDQ is typically close to zero.
GND 2
NIC 5
Connect to ground.
Set VGG1 and VGG2 to −2 V.
Set VDD1 through VDD4, the drain voltage bias pins, to 5 V.
Increase VGG1 and VGG2 to achieve an IDQ of 225 mA.
Apply the RF signal
The recommended bias sequence during power down for the
HMC1131 is the following:
Figure 3. Typical Connections of an Externally Biased Amplifier
GND 4
To achieve a target quiescent drain current (IDQ) of 225 mA, set
the voltage of the gate bias pins (VGG1 and VGG2) between 0 V
and −2 V. To set that negative voltage without damaging the
amplifier, follow the recommended biasing sequence during
power up and power down.
Figure 4. HMC1131 Multistage Externally Biased Amplifier
HMC1131 Biasing and Sequencing Requirements
The HMC1131 is a gallium arsenide (GaAs), pHEMT, monolithic
microwave integrated circuit (MMIC), medium power amplifier.
It operates from 24 GHz to 35 GHz. The 4-stage design typically
provides a 22 dB gain, 23 dBm output power for 1 dB compression
(P1dB), and 27 dBm saturated output power (PSAT) under the
bias conditions of VDD = 5 V and IDQ = 225 mA, where VDD is the
drain bias voltage and IDQ is the quiescent drain current. The
electrical specifications table of the HMC1131 data sheet, for the
24 GHz to 27 GHz frequency range, gives this information.
Figure 4 shows the pin connections of the HMC1131.
In general, for multistage amplifiers, the VGG pins are connected
and biased together. By following the same procedure, a user
can get the typical performance results provided on the data
sheet. Operating the amplifier under different bias conditions
may provide different performance. For instance, using a different
VGGx level for the HMC1131 gate bias pins to obtain various IDQ
values changes the RF and dc performance of the amplifier.
Rev. 0 | Page 4 of 16
Application Note
AN-1363
Figure 5 shows the P1dB vs. the frequency at various supply
currents, and Figure 6 shows the output third order intercept
(IP3) performance vs. the frequency at various supply currents
for the HMC1131.
30
28
26
CASCODE AMPLIFIERS
24
Analog Devices wideband distributed amplifiers often use
a cascode architecture to extend the frequency range. The
cascode distributed amplifier uses a fundamental cell of two
FETs in series, source to drain. This fundamental cell is then
duplicated a number of times. This duplication increases the
operation bandwidth. Figure 7 shows a simplified schematic
for a fundamental cell.
22
20
18
16
12
24
25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
VDD
13164-009
175mA
200mA
225mA
250mA
14
RFOUT
VGG2
Figure 5. P1dB vs. Frequency at Various Supply Currents
40
RFIN
13164-011
P1dB (dBm)
Another option for biasing externally biased amplifiers, is
setting VGGx for the desired IDQ of 225 mA and using a constant
gate voltage during normal operation. In this case, the IDD of the
amplifier increases under the RF drive. This behavior is shown
in the power compression at 30.5 GHz in the HMC1131 data
sheet (see the orange line). The performance of the amplifier
with constant gate voltage and with constant IDD can be different.
38
VGG1
36
With some exceptions, the cascode wideband amplifiers are
externally biased.
32
30
175mA
200mA
225mA
250mA
22
20
24
25
26
27
28
29
30
31
32
33
34
35
36
FREQUENCY (GHz)
32
31
30
29
28
27
26
25
24
Figure 6. Output IP3 vs. Frequency at Various Supply Currents,
POUT/Tone = 10 dBm
NIC
VGG2
NIC
NIC
RFIN
NIC
NIC
NIC
This flexibility is useful for some applications. If the performance
data of an amplifier provided on the data sheet meets some
requirements of the application easily, yet misses others by a
small margin, testing the performance under different bias
conditions can be advantageous without exceeding the absolute
maximum ratings given in the data sheet.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NIC 9
NIC 10
NIC 11
NIC 12
VGG1 13
NIC 14
ACG4 15
ACG3 16
Another option for biasing amplifiers with multiple VGGx pins is
to control the gate bias pins independently. This operation mode
helps users customize device performance by optimizing specific
parameters such as P1dB, IP3, NF, gain, and power
consumption.
NIC
NIC
NIC
RFOUT/VDD
NIC
NIC
NIC
NIC
PACKAGE
BASE
GND
13164-012
26
NIC
NIC
ACG1
ACG2
NIC
NIC
NIC
NIC
The HMC637A is a wideband amplifier that uses cascode
topology. The HMC637A is a GaAs, MMIC, metal semiconductor
field effect transistor (MESFET) distributed power amplifier that
operates between dc and 6 GHz. Figure 8 shows the pin
connections for the HMC637A.
28
13164-010
OUTPUT IP3 (dBm)
Figure 7. Simplified Fundamental Cascode Cell Schematic
34
Figure 8. HMC637A Pin Connections
The amplifier provides 14 dB of gain, 43 dBm of output IP3, and
30.5 dBm of output power at a 1 dB gain compression under the
bias conditions of VDD = 12 V, VGG2 = 6 V, and IDQ = 400 mA.
The electrical specifications table of the HMC637A data sheet
provides this information.
Rev. 0 | Page 5 of 16
AN-1363
Application Note
To achieve the recommended quiescent drain current of 400 mA,
VGG1 must be somewhere between 0 to −2 V. To set the desired
negative voltage, follow the recommended bias sequence during
power up and power down.
The recommended bias sequence for the HMC637A during power
up follows:
1.
2.
3.
4.
5.
6.
Connect to ground.
Set VGG1 to −2 V.
Set VDD to 12 V.
Set VGG2 to 6 V (VGG2 can be obtained by a resistive divider
from VDD).
Increase VGG1 to achieve a typical quiescent current (IDQ) of
400 mA.
Apply the RF signal.
The recommended bias sequence for the HMC637A during
power down follows:
1.
2.
3.
4.
5.
Turn off the RF signal.
Decrease VGG1 to −2 V to achieve IDQ = 0 mA.
Decrease VGG2 to 0 V.
Decrease VDD to 0 V.
Increase VGG1 to 0 V.
Designing bias circuits for amplifiers to keep the drain current
constant and provide necessary sequencing can be cumbersome.
Such control circuits are complicated and require not only multiple
external components such as low drop out regulators (LDOs),
charge pumps, voltage sequencing, and protection circuits, but
also calibration cycles. Such implementations occupy a large
printed circuit board (PCB) area that is usually much larger
than the amplifier itself.
The HMC920LP5E houses all the necessary operation blocks
in a compact 5 mm × 5 mm plastic surface-mount technology
(SMT) package. By eliminating multiple IC and external
component requirements, this compact size results in reduced
PCB area compared to the discrete biasing implementations.
Similar to the HMC920LP5E, active bias controllers require less
PCB space than discrete transistor solutions. When using the
HMC980LP4E, bias sequencing, constant gate voltage adjustment,
short-circuit protection, and negative voltage generation features
are implemented within 10 mm × 15 mm of PCB space.
The HMC981LP3E, HMC980LP4E, and HMC920LP5E are
3 mm × 3 mm, 4 mm × 4 mm, and 5 mm × 5 mm plastic
packaged active bias controllers, respectively. Figure 9 shows
the PCB area required for a typical application, including
external passive components.
USING ACTIVE BIAS CONTROLLERS TO BIAS
EXTERNALLY BIASED AMPLIFIERS
ACTUAL AREA REQUIRED
IN TYPICAL APPLICATION
There are two major approaches for biasing externally biased
amplifiers:

Constant gate voltage approach. In this approach, the gate
voltage value is varied to achieve the desired IDQ value. This
gate voltage value is then kept constant during operation,
which typically results in a variable drain current (IDD)
under the RF drive.
Constant IDD approach. In this approach, the gate voltage
value is varied to achieve the desired IDQ value, then the IDD
value of the amplifier is monitored, and the gate voltage
value is adjusted constantly to have the same IDD value for
different RF drive levels. Active bias controllers keep the
IDD of the device under test (DUT) constant.
Another approach, a subset of the constant IDD approach, consists
of following the constant IDD approach and switching in between
multiple constant IDD levels when necessary due to various field
scenarios. For instance, a user can bias a power amplifier stage
of a transmitter for high current levels during rainy weather to
compensate for the additional rain attenuation. Similarly, a user
can bias the same power amplifier for low current levels during
clear weather to reduce the power consumption.
HMC980LP4E
HMC920LP5E
13164-014

HMC981LP3E
Figure 9. PCB Area Required in Typical Application
The Analog Devices active bias controller family offers some key
advantages:



In general, Analog Devices RF amplifiers are characterized with
a constant gat voltage approach, using bench top power supply
units. Therefore, biasing those amplifiers with the constant IDD
approach can result in different RF performance than what is
given on the amplifier data sheet.
Rev. 0 | Page 6 of 16
Internal negative voltage generators generate the negative
voltage at the VGATE pin required for externally biased
amplifiers. These generators eliminate the need for voltage
inverters and reduce the device count, the PCB space, and, as
a result, the system cost.
Continuous internal gate voltage adjustment ensures a
constant DUT drain current.
Bias accuracy improves due to the reduction of device to
device variation effects. The optimum gate voltage level
required to obtain a desired IDD for different amplifiers
with the same device number is different due to device to
device variation. Therefore, setting the gate voltage to the
same value for separate DUTs results in a different RF
performance. Active bias controllers adjust the gate voltage
level separately for each individual DUT and reduce the
performance difference introduced by device to device
variation.
Application Note
AN-1363
125
Figure 10 and Figure 11 show this reduction on device to
device variation effects.
115
110
115
110
105
100
105
95
1
SN1
2
SN2
3
SN3 4 SN4
SAMPLES
5
SN5
6
SN6
7
13164-015
100
Figure 10. Bias Current Variation of a Typical Amplifier Under Fixed External
VGATE Bias
1
SN1
2
SN2
3
SN3 4 SN4
SAMPLES
5
SN5
6
SN6
7
13164-016
BIAS CURRENT (mA)
BIAS CURRENT (mA)
+85°C
+25°C
–40°C
120
95
+85°C
+25°C
–40°C
120
125
Figure 11. Improved Bias Current Variation of Same Amplifier when Biased
with the HMC920LP5E


Rev. 0 | Page 7 of 16
Internal bias sequencing circuitry ensures that positive
voltages on the VDRAIN pin and the VG2 pin are not
supplied to the DUT when the negative VGATE voltage is
not present. This feature eliminates the external components
used for sequencing during DUT power up and power down.
Short-circuit protection circuitry disables the VDRAIN pin
after the VGATE pin and therefore makes sure that the
DUT is safe, even under short circuit conditions.
AN-1363
Application Note
R10
1kΩ
NIC
R13
4.7kΩ
R12
301Ω
R11
301Ω
R14
10kΩ
19
20
CONTROL
BLOCK
4
16
13
VDRAIN
TP10
VGATE
TP9
VG2
TP8
12
NEGATIVE
VOLTAGE GENERATOR
11
6
10
14
9
C8
2.2µF
15
BAND GAP
HMC980LP4E
C3
100pF
VDD
R3
5.1kΩ
R4
3.3kΩ
C5
10nF
C6
1µF
GND
TP12
13164-017
C4
4.7µF
C9
10nF
17
5
7
VDIG
TP7
21
18
GATE
CONTROL
2
3
VDD
22
1
C2
10nF
8
VDD
TP1
C1
GND 4.7µF
TP2
S0
TP3
S1
TP4
EN
TP5
ALM
TP6
23
24
TRIG OUT
TP11
C7
10µF
Figure 12. Typical Application Circuit for the HMC980LP4E
Table 2. Selected Features of Active Bias Controllers
Device
Number
HMC920LP5E
HMC980LP4E
HMC981LP3E
Supply
Range (V)
5 to 16.5
5 to 16.5
4 to 12
VDRAIN (V)
3 to 15
5 to 16.5
4 to 12
IDRAIN (mA)
0 to 500
50 to 1600
20 to 200
IGATE (mA)
−4 to +4
−4 to +4
−0.8 to +0.8
With an internal feedback, the automatic gate voltage control
achieves a constant quiescent bias current through the amplifier
under bias, independent of the temperature and amplifier threshold
variations. The quiescent bias current is adjusted with a resistor
connected externally. Figure 12 shows the RSENSE resistor (R10)
connected to Pin 20 of the HMC980LP4E.
Over/Under
Current Alarm
Yes
Yes
No
Short-Circuit
Protection
Yes
Yes
Yes
VDRAIN LDO
Yes
No
No
Negative
Voltage
Generator
Yes
Yes
Yes
OPERATING PRINCIPLES
Further details on how to calculate the RSENSE and VDD values
can be found on the active bias controller data sheets.
For externally biased amplifiers, Analog Devices data sheets
highlight the biasing requirements for VGG and IDD at the bottom
of electrical specifications table. For instance, the HMC637A
requires its VGG1 to be adjusted from −2 V to 0 V to obtain a
typical IDQ of 400 mA. However, follow the recommended
sequencing during power-up and power-down to avoid
damaging the HMC637A.
Analog Devices offers three active bias controllers: the
HMC920LP5E, HMC980LP4E, and HMC981LP3E. Table 2
details selected features of these active bias controllers.
The HMC980LP4E employs an integrated control circuitry
to manage safe power-up and power-down sequencing of the
targeted amplifier.
The HMC980LP4E provides the ability to source high drain
currents, while the HMC981LP3E is best suited for devices that
require lower drain currents. In addition to the negative voltage
generator, the HMC920LP5E integrates a positive voltage
regulator, providing the ability to source drain pins.
During power up, the VDD and VDIG supplies of the bias
controller turn on, and then VNEG generates by the internal
negative voltage generator (NVG). VNEG starts to decrease and
stops when it reaches its default value (typically −2.46 V). The
VGATE output voltage also starts to decrease. Typically, once
VNEG = −2.5 V and VGATE = −2.1 V are reached, the VDRAIN
output is enabled, and VGATE begins to increase toward 0 V to
obtain the desired IDD value for the DUT.
Rev. 0 | Page 8 of 16
Application Note
AN-1363
8
Similar power-down protection circuitry also provides a safe
power down for the DUT. During power down, VGATE always
shuts down after VDD, even if there is a short circuit on the
VDD pins or on the VGG pins of the DUT. This feature introduces
advanced protection of the DUT, under excessive DUT IDD
current scenarios.
6
VOLTAGE (V)
4
8
2
0
4
–4
2
0
10
20
30
40
50
TIME (ms)
Figure 14. Default VNEG Value
0
VDD
VDRAIN
VDIG
VG2
VNEG
VGATE
–4
0
10
With the default configuration, the typical VGATE output
swing is in between −2 V and 0 V. However,
20
30
40
50
TIME (ms)


13164-018
–2
Figure 13. HMC981LP3E Enabling Sequence for Supply Rails
ADJUSTING THE DEFAULT VNEG AND VGATE
THRESHOLD VALUES
The typical VNEG value is −2.46 V, as seen in Figure 14. Due to
the internal logic that exists inside HMC980LP4E, this default
value limits the VGATE output voltage swing capabilities of the
HMC980LP4E.
Adjusting the default values of VNEG and VGATE by external
resistors solves both of these problems. The R5, R6, R7, and R8
resistors shown in Figure 15 are used for this purpose.
R10 = 150Ω/IDRAIN
VDD = VDRAIN + IDRAIN × RDS_ON
TRIGOUT
R11
301Ω
C2
10nF
VDD
S0
VDIG
S1
GND
EN
EN
ISENSE
21
22
23
24
VDD
C1
4.7µF
1
18
2
17
3
HMC980LP4E
16
4
15
5
14
6
CPVDD
7
CPOUT
8
VDIG
9
VREF
10
VNEGFB
11
VGATEFB
12
VDD
5.28V
TRIGOUT
R10
R14
10kΩ
19
R12
301Ω
20
R13
4.7kΩ
For some DUTs, gate voltages of less than −2 V are necessary.
Some DUTs have a gate voltage absolute maximum rating
(AMR) that is greater than −2.1 V, such as −1.5 V. In such a
case, the DUT is expected to have a typical gate voltage
higher than the AMR value of VGATE, such as −1 V.
During the power up, however, the VGATE output of the
HMC980LP4E always reduces to a typical value of −2 V.
VDRAIN
IDRAIN
VDRAIN
VDRAIN
VGATE
R7
R8
VGATE
VNEG
R5
R6
13
GND
C3
10nF
VDIG
3.3V TO 5V
C3
4.7µF
C4
10nF
D1 DUAL SCHOTTKY
C5
1µF
C6
10µF
Figure 15. External Resistors for Adjusting Default VNEG and VGATE Values
Rev. 0 | Page 9 of 16
13164-020
VOLTAGE (V)
VDD
VDRAIN
VDIG
VG2
VNEG
VGATE
–2
13164-019
6
AN-1363
Application Note
19 TRIGOUT
21 ALML
2
17
S0
3
16
S1
4
15 VNEG
EN
5
14 VG2
ALM
6
13 VG2_CONT
HMC980LP4E
VDD
VGATE
RFIN
DUT
RFOUT
VGG
R1
13164-022
VGATEFB 12
VREF 10
9
VDIG
VNEGFB 11
8
C1
It is recommended to configure the HMC980LP4E for VNEG
values greater than −3.5 V.
For example, if the desired VNEG = −1.5 V and VGATE =
−1.3 V, R5 = 631 kΩ, R7 = 477 kΩ, and R6 = R8 = open. In
addition, if the desired VNEG = −3.2 V and VGATE = −3 V,
R6 = 221 kΩ, R8 = 303 kΩ, and R5 = R7 = open.
20 ISENSE
1
VDD
7
During power up, VNEG is enabled if VNEG reaches a default
value of −2.46 V; therefore, the VNEG value must be less than
the VGATE value.
18 VDRAIN
VDRAIN
VDD
CPOUT
If the desired VGATE > −2.46 V, then R7 (kΩ) = 262/(262 ×
(1.44 − 0.815)/(50 × (0.815 – Desired VGATE)) − 1), and
R8 (kΩ) = open.
CPVDD
If the desired VGATE < −2.46 V, then R7 (kΩ) = open, and
R8 (kΩ) = 50/(50 × (Desired VGATE − 0.815)/(262 ×
(0.815 − 1.44)) − 1).
22 ISET
24 FIXBIAS
If the desired VNEG > −2.46 V, then R5 (kΩ) = 262/(262 ×
(1.44 − 0.815)/(50 × (0.815 − Desired VNEG)) − 1), and
R6 (kΩ) = open.
23 ALMH
The external circuit affects the gate rise time but not the
propagation delay. Figure 17 shows a typical VGATE connection
between the HMC980LP4E and a DUT amplifier. Generally,
the shunt capacitor, C1, is used on the VGG pins of the amplifiers,
where R1 is usually 0 Ω, that is, not used.
If the desired VNEG < −2.46 V, then R5 (kΩ) = open,
and R6 (kΩ) = 50/(50 × (Desired VNEG − 0.815)/(262 ×
(0.815 − 1.44)) − 1).
Figure 17. VGATE Connection Circuitry Between the HMC980LP4E and the DUT
When C1 = 10 μF, the typical rise time is greater than 1.5 ms
(see Figure 18). Reducing C1 to 1 μF reduces the rise time to
131 μs (see Figure 19).
REDUCING VGATE RISE TIME
A delay exists between the moment that the enable signal reaches
the enable pin of the active bias controller and the moment that
the VGATE voltage level at the DUT VGATE input pin settles
to the desired value. This delay is due to the combination of the
internal propagation delay of the bias controller and the settling
time of the VGATE signal. The VGATE settling time is affected
by the shunt capacitors used on the connection between the
active bias controller VGATE output and the DUT VGATE
input pin. The HMC980LP4E typical enable waveform (see
Figure 16) shows a VGATE settling time greater than 1 ms.
T
FALL (2): NO SIGNAL
RISE (2): NO SIGNAL
RISE (1): 1.62ms
1
4
CH1 500mV CH2
CH3
12
1.46V
Figure 18. Typical VGATE Rise Time with C1 = 10 μF
8
T
4
0
–4
0
1
2
3
4
5
TIME (ms)
4
6
PROPAGATION
DELAY
Figure 16. HMC980LP4E Typical Enable Waveform
CH1 500mV CH2
CH3
CH4 1.00V
M324.0ms
A CH4
T
100.0ms
1.46V
Figure 19. Typical VGATE Rise Time with C1 = 1 μF
Rev. 0 | Page 10 of 16
13164-024
–12
1
EN (V)
VDRAIN (V)
VG2 (V)
VNEG (V)
VGATE (V)
–8
FALL (2): NO SIGNAL
RISE (2): NO SIGNAL
RISE (1): 131µs
13164-021
VOLTAGE (V)
M2.030ms
A CH4
T
1.000ms
13164-023
16
Application Note
AN-1363
When C1 = 100 nF, the VGATE rise time is reduced to 15.5 μs,
but overshooting introduces ringing (see Figure 20). Adding a
series resistor, R1, with a value of 68 Ω to C1 = 100 nF improves
the response and keeps the rise time within a similar level (see
Figure 21).
VDD
DUT
RF
IF
– LO
VGG
VDD
VGG
DUT
ACTIVE BIAS EN
CONTROLLER
13164-028
T
TRIGOUT ACTIVE BIAS EN
CONTROLLER
Figure 23. Daisy-Chain Configuration Where DUT Amplifiers Are on Different
Signal Paths
1
Figure 24 shows the VDRAINx and VGATEx responses of two
active bias controllers in a daisy-chain configuration, powering
two DUTs individually. The second bias controller enables by
the trigger signal sourced from the first bias controller. This
architecture ensures that the second DUT enables after the
first DUT.
4
CURRENT
15.5µs
MAX
76.0µs
CH1 500mV CH2
CH3
CH4 1.00V
STD DEV
26.890µs
MEAN
27.900µs
MIN
15.5µs
COUNT
5
M176.0ms
T
50.0ms
A CH4
1.46V
T
13164-025
MEASURE
RISE (1):
EN1
EN2/TRGOUT1
Figure 20. Typical VGATE Rise Time with C1 = 100 nF
T
2
VDRAIN1
VDRAIN2
1
4
MAX
11.5µs
CH1 500mV CH2
CH3
CH4 1.00V
CURRENT
11.5µs
STD DEV
0.0s
MEAN
11.500µs
CH1 5.00V
CH3 2.00V
MIN
11.5µs
COUNT
1
M149.5ms
T
50.0ms
CH2 5.00V
CH4 2.00V
M2.245ms
A CH1
T
500.0ms
1.31V
Figure 24. VDRAINx Responses of Two Active Bias Controllers in a DaisyChain Configuration, Powering Two DUTs Individually
A CH4
1.46V
13164-026
MEASURE
RISE (1):
13164-029
3
T
EN1
Figure 21. Typical VGATE Rise Time with C1 = 100 nF and R1 = 68 Ω
EN2/TRGOUT1
DAISY-CHAIN CONFIGURATION
2
When multiple active bias controllers bias multiple DUTs, they
can be used in a daisy-chain configuration. The TRIGOUT
output of the active bias controller generates when the VDRAIN,
VG2, and VGATE outputs settle. Using the TRIGOUT signal to
enable another bias controller with the enable pin (EN) improves
the system safety level. A daisy-chain configuration has many
applications, Figure 22 and Figure 23 show two applications. The
number of DUT stages and bias controllers can be increased.
EN
TRIGOUT
ACTIVE BIAS
CONTROLLER
DUT
VGG
VGATE2
CH1 5.00V
CH3 1.00V
VDD
RFOUT
RFIN
DUT
VGG
CH2 5.00V
CH4 1.00V
M2.245ms
A CH1
T
500.0ms
1.31V
Figure 25. VGATEx Responses of Two Active Bias Controllers in a Daisy-Chain
Configuration, Powering Two DUTs Individually
RFOUT
13164-027
VDD
RFIN
VGATE1
13164-030
ACTIVE BIAS
CONTROLLER
3
Figure 22. Daisy-Chain Configuration with Two Amplifiers in Cascade
Configuration
Rev. 0 | Page 11 of 16
AN-1363
Application Note
TESTING THE FUNCTIONALITY OF THE ACTIVE
BIAS CONTROLLER
Note, however, that using this approach limits the benefits that
an active bias controller offers for the following reasons:
The VDRAIN and VGATE outputs of active bias controllers can
bias a DUT, such as an FET or an amplifier with external
biasing requirements. Once the DUT is connected to the bias
controller, the feedback loop is closed and the bias controller
becomes operational.

An active bias controller is not able to compensate deviceto-device gate voltage variation that is common with GaAs
devices. As a result, two devices can be biased using one
gate voltage, resulting in nonoptimal performance.
If one of the DUTs draws excessive current due to a short
circuit or other terms of failure, the bias controller shuts
down all DUTs under bias. Although this does not damage
the devices, it compromises system functionality.

Because the loop does not close, it is not feasible to test the
functionality of an active bias controller with a fixed load, like a
resistor.
Although testing active bas controllers without a DUT does not
provide useful information, perform the following diagnostic
checks.
SAMPLE ACTIVE BIAS CONTROLER APPLICATION
CIRCUITS

To bias the HMC460LC5 with the HMC981LP3E, do the
following:

Set R10 to 426 Ω to set IDD = 75 mA for the HMC981LP3E.
A common resistor value of 430 Ω can be used.
Calculate a VDD value of 8.75 V.
Use R4 and R6 to ensure that the VGATE voltage is within
the Absolute Maximum Ratings section of the HMC981LP3E
data sheet. Refer to the Adjusting the Default VNEG and
VGATE Threshold Values section for details.
The shunt VGG capacitor values can be reduced to increase
the rise time (see HMC460LC5 in Figure 26). Refer to the
Reducing VGATE Rise Time section for further details.


For other bias controllers, these values can be extracted from
their data sheets.
BIASING MULTIPLE DUTS BY A SINGLE ACTIVE
BIAS CONTROLLER

It is possible to bias two or more DUTs by a single active bias
controller. To do so, calculate the RSENSE value considering the
total drain current of the DUTs.
R10 = 32 / IDRAIN (0.075A) = 426Ω
VDD = VDRAIN (8V) + IDRAIN (0.075A) × RDS_ON (10Ω) = 8.75V
D1 DUAL SCHOTTKY
C3
4.7µF
C4
10nF
C6
10µF
8
10nF
17
100pF
2.2µF
Figure 26. Application Circuit for Biasing the HMC460LC5 with the HMC981LP3E
Rev. 0 | Page 12 of 16
25
26
27
28
29
31
18
1nF
13164-031
R6
1.6MΩ
19
7
VGG
R4
1.6MΩ
20
6 GND
15
VNEG = –2V
GND 21
RFIN
14
9
8
7
VNEGFB
6
VGATEFB
CPOUT
5
VDIG
4
5
10
VNEG
EN
4
VG2
22
16
1nF
13 ACG2
HMC981LP3E
3
VDIG
3.3V TO 5V
4.7µF
11
12
2
23
RFOUT
3
11
14
15
13
12
VGATE
VG2CONT
SW
GND
VDRAIN
24
HMC460LC5
2
10
C2
10nF
1
9
C1
4.7µF
TRIGOUT
1
DISBLSC
16
ISENSE
VDD
VREF
R10
426Ω
ACG1 30
32
100nF
VDD


Biasing the HMC460LC5 with the HMC981LP3E
IDD = 0 mA results in a negligible voltage drop across the
VDD input and VDRAIN output; therefore, VDRAIN is
almost equal to VDD.
VNEG is typically −2.46 V.
VGATE hits a maximum value of VNEG + 4.5 V, which is
typically 2.04 V.
Application Note
AN-1363

Biasing the HMC1082LP4E with the HMC980LP4E
Use R5 and R7 to ensure that the VGATE voltage is within
the Absolute Maximum Ratings section of the HMC980LP4E
data sheet. Refer to the Adjusting the Default VNEG and
VGATE Threshold Values section for details.
The shunt VGG capacitor values can be reduced to increase
the rise time (see HMC1082LP4E in Figure 27). Refer to
the Reducing VGATE Rise Time section for further details.
To bias the HMC1082LP4E with the HMC980LP4E, do the
following:
Set R10 to 680 Ω to set IDD = 220 mA for the HMC980LP4E
Calculate a VDD value of 5.62 V.
R10 = 150Ω/IDRAIN (0.22A) = 680Ω
VDD = VDRAIN (5V) + IDRAIN (0.220A) × RDS_ON (2.8Ω) = 5.62V

TRIGOUT
21
VDD2
19
20
VDD3
22
24
VDD1
RFOUT
2.5kΩ
4
2.5kΩ
5
6
14
13
12
GND
16
15
HMC1082LP4E
7
VGATEFB
11
VNEGFB
10
9
VREF
8
VDIG
CPOUT
13
17
RFIN
11
14
7
3
R5
1.6MΩ
VG2_CONT
18
2
10
15
VG2
5
6
100pF
1
VGATE
R7
1.6MΩ
VNEG
4
ALM
100pF
9
16
HMC980LP4E
EN
EN
100pF
VGG
GND
1nF
8
3
S1
1nF
19
20
TRIGOUT
21
ISENSE
22
ALML
23
ISET
24
VGATE
S0
GND
IDRAIN =
220mA
VDRAIN = 5V
VNEG = 2.0V
C2
10nF
VDRAIN
18
VDRAIN
17
12
C1
4.7µF
VDD
1
VDD
2
ALML
FIXBIAS
VDD
5.62V
1nF
2.2µF
R10
680Ω
R14
10kΩ
23
5kΩ
CPV DD
C3
100pF
VDIG
3.3V TO 5V
C3
4.7µF
C4
10nF
D1 DUAL SCHOTTKY
C5
1µF
2.2µF
1nF
100pF
C6
10µF
Figure 27. Application Circuit for Biasing the HMC1082LP4E with the HMC980LP4E
Rev. 0 | Page 13 of 16
13164-032


AN-1363
Application Note

Biasing the HMC659LC5 with the HMC980LP4E
Use R5 and R7 to ensure that the VGATE voltage is within
the Absolute Maximum Ratings section of the HMC980LP4E
data sheet. Refer to the Adjusting the Default VNEG and
VGATE Threshold Values section for further details.
The shunt VGGx capacitors value can be reduced to increase
the rise time (see HMC659LC5 in Figure 28). Refer to the
Reducing VGATE Rise Time section for further details.
To bias the HMC659LC5 with the HMC980LP4E, do the
following:
Set R10 to 500 Ω to set IDD = 300 mA for the HMC980LP4E.
Use a common resistor value of 510 Ω.
Calculate a VDD value of 8.84 V.
Use R3 and R4 to set VGG2 for the HMC980LP4E.

R10 = 150ΩIDRAIN (0.3A) = 500Ω
VDD = VDRAIN (8V) + IDRAIN (0.3A) × RDS_ON (2.8Ω) = 8.84V
TRIGOUT
R13 R12 R11
4.7kΩ 301Ω 301Ω
R10
500Ω
R14
10kΩ
100nF
C3
100pF
VDIG
3.3V TO 5V
C3
4.7µF
D1 DUAL SCHOTTKY
C5
1µF
C6
10µF
Figure 28. Application Circuit for Biasing the HMC659LC5 with the HMC980LP4E
Rev. 0 | Page 14 of 16
25
26
27
28
18
8
0.47µF
C4
10nF
29
30
7
17
10nF
2.2µF
13164-033
VDD
19
16
R4
4.74kΩ
20
6
VGG1
R3
5kΩ
RFIN
15
11
13
12
VNEGFB
10
9
VREF
8
VDIG
CPOUT
7
VGATEFB
VG2_CONT
ALM
5
22
21
4
14
14
5
23
RFOUT/VDD
13
EN
3
VGG2
12
R5
1.6MΩ
VG2
31
32
15
4
6
R7
1.6MΩ
VNEG
24
HMC659LC5
2
VGATE
16
HMC980LP4E
1
11
3
EN
IDRAIN =
300mA
VDRAIN = 8V
VGATE
S1
GND
VDRAIN
18
VDRAIN
17
9
GND
19
20
TRIGOUT
21
22
ALML
23
24
2
S0
0.47µF
10
C2
10nF
VDD
100nF
C1
4.7µF
ISENSE
1
ISET
VDD
ALML
VDD
8.84V
FIXBIAS
10nF
CPV DD




Application Note
AN-1363

Biasing the HMC659LC5 with the HMC920LP5E
Use R20 and R22 to ensure that the VGATE voltage is within
the Absolute Maximum Ratings section of the HMC920LP5E
data sheet. Refer to the Adjusting the Default VNEG and
VGATE Threshold Values section for details.
The shunt VGGx capacitor values can be reduced to increase
the rise time (see HMC659LC5 in Figure 29). Refer to the
Reducing VGATE Rise Time section for further details.
To bias the HMC659LC5 with the HMC920LP5E, do the
following:
Set RSENSE to 549 Ω to set IDD = 300 mA for the HMC920LP5E.
Set R8 to 30.9 kΩ to set VDRAIN = 8 V.
R15
5kΩ
C22
100nF
20
R20
1.6MΩ
VNEGIN
19
6
VNEGFB
EN
18
7
AGND
C14
4.7µF
DGND
16
17
15
CPOUT
VDD2
14
VREF
FIXBIAS
13
C20
100nF
R27
10kΩ
12
11
AGND
ALMSET
10
CURALM
9
R22
1.6MΩ
D1 DUAL SCHOTTKY
C13
0.33µF
5
25
26
27
28
29
30
31
21
RFIN
20
6
19
7
18
8
0.47µF
C6
10µF
VDD
Figure 29. Application Circuit for Biasing the HMC659LC5 with the HMC920LP5E
Rev. 0 | Page 15 of 16
22
17
10nF
C21
10µF
13164-034
5
VGATEFB
4
16
21
HMC920LP5E
23
RFOUT/VDD
VGG1
4
100nF
VGG2
15
10kΩ
VGATE
BGCAP
3
14
22
3
PORCAP
2
VDRAIN = 8V
24
HMC659LC5
13
VDRAIN
16kΩ
12
IDRAIN =
300mA
23
2
8
1
24
VDRAIN
VDIG
0.47µF
32
25
26
ISENSE
27
ALML
28
ALMM
29
ALMH
30
LDOCC
31
32
LDOFB
TRGOUT
VDD1
BGC
C1
1µF
10nF
11
C5
10µF
RESR > 0.2Ω
C24
100pF
VNEG = 2.0V
C2
10nF
VDDALM
1
C1
4.7µF
VDDCHK
VDD1
RSENSE
549Ω
10
C9
10µF
R8
30.9kΩ
VDD
9V TO 16.5V

9
R5
10kΩ
ALMTRIG


AN-1363
Application Note
CONCLUSION
Follow the recommended biasing sequence for externally biased
devices during power-up and power-down to ensure the safety
of the device. Operating amplifiers with an active bias controller
ensures that the device is sequenced properly and at the desired
level, improving overall system performance.
The active bias controller family from Analog Devices can
address the biasing requirements of externally biased RF/
microwave components, such as FETs, amplifiers, multipliers,
optical modulator drivers, and frequency converters. The gate
voltages of the DUTs are adjusted with a closed feedback loop
for the desired drain current. The sequencing feature of the
VGATE, VDRAIN, and VGG2 outputs of the bias controller
during power up and power down ensures that the DUT is
protected.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN13164-0-7/16(0)
Rev. 0 | Page 16 of 16