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Chapter 1 Nanoelectronics Emerging Research Devices Hsin-Chu, Taiwan August 25, 2004 Jim Hutchby – SRC Chair, Emerging Research Device Technical Working Group 小型化原則: Gate length: L/ Depletion Width: xd/ Voltage: V/ Oxide: tox/ Wire Substrate: *NA RESULTS: Higher Density: ~ 2 Higher Speed: ~ Power/ckt: ~1/2 Power Density: ~ Constant 1000 元件小型化 電壓, V/ Tox(Å) WIRING 100 tox/ W/ GATE nsource 10 Vdd(V) n+ L/ psubstrate, doping *NA drain xd/ classic scaling 1 Vt(V) 0.1 0.01 0.1 Gate Length, Lgate(m) 1 Power is an issue 1E+03 Active Power Density 1E+02 1E+01 Power (W/cm2) Leff and Vdd導致 Active Power Density ~ 1.3X/generation Passive Power Density ~ 3X/generationGate Leakage Power Density : 4X/generation 1E+00 1E-01 1E-02 1E-03 Standby Power Density 1E-04 1E-05 0.01 0.1 Gate Length (m) 1 Result : CMOS power densities escalate unacceptably 12 Bipolar Module Heat (watts/cm2) 10 CMOS 8 6 4 蒸氣熨斗 5W/cm2 2 0 1950 1960 1970 1980 Gate leakage: 10x/0.2nm PIDS Research Devices Working Group Participants George Bourinaoff Intel/SRC Joe Brewer U. Florida Toshiro Hiramoto Tokyo U. Jim Hutchby SRC Mike Forshaw UC London Tsu-Jae King UC Berkeley Rainer Waser RWTH A In Yoo Samsung John Carruthers OGI Joop Bruines Philips Jim Chung Compaq Peng Fang AMAT Dae Gwan Kang Hynix Makoto Yoshimi Kristin De Meyer Tak Ning Philip Wong Luan Tran Victor Zhirnov Ramon Compano Simon Deleonibus Thomas Skotnicki Yuegang Zhang Kentaro Shibahara Byong Gook Park Toshiba IMEC IBM IBM Micron SRC/NCSU Europe Com LETI ST Me Intel Hiroshima U. Seoul N. U. Where are TW’s experts? Emerging Research Devices Introduction and Scope Cast a broad net to introduce readers to device and architecture concepts for information processing --Concept --- not hardened solutions Identify Include Stimulate --- not endorse --- and quantify (new) --- and assess/critique (new) Emerging Research Devices Introduction and Scope Broadened Scope Compared to 2001 Chapter --New quantitative performance metrics --- potential versus to-date performance Provide in-depth critical assessment --- key application driven questions/issues Scaling Limit of Charge Based Switch An Example of Critical Assessment Observations Transistor critical dimension limited to ~ 1 nm (In the 2003 ITRS physical gate length = 7 nm for 2018) Power density, not critical dimension, limits gate density to ~ 1 x 109 gates/cm2 For the ITRS density and switching time, CMOS is approaching the maximum power efficiency Emerging Research Devices Organization & Component Tasks (2003) Emerging Research Devices Non-classical CMOS Research Logic and Memory Devices Functional Organization (Architectures) Scope of Emerging Research Devices Bulk CMOS New Memory and Logic Technologies Double-Gate CMOS New Architecture Technologies Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts CMOS Scaling Challenges Table 2a High Performance Logic Technology Requirements—2003 ITRS CALENDAR YEAR 2003 2004 TECHNOLOGY NODE (NM) 100 90 MPU GATE LENGTH 45 1.3 37 1.2 32 1.1 0.8 0.8 2.1 1.2 Gate Dielectric Equivalent Oxide Thickness (EOT) (nm) [1] Electrical Thickness Adjustment Factor (Gate Depletion and Quantum Effects) (nm) [2] Electrical Equivalent Oxide Thickness in Inversion (nm) 4 Vdd (V) [4] 2005 2006 2007 2008 2010 2013 2016 2018 65 45 32 22 18 28 1.0 25 0.9 0.8 18 0.7 13 0.6 9 0.50 7 0.45 0.7 0.7 0.4 0.4 0.4 0.4 0.4 0.4 2.0 1.8 1.7 1.3 1.2 1.1 1.0 0.9 0.9 1.2 1.1 1.1 1.1 1.0 1.0 0.9 0.8 0.7 Bulk-Si Performance Trends Maintaining historical CMOS performance trend requires new semiconductor materials and structures by 2008-2010... Earlier if current bulk-Si data do not improve significantly. 10.00 Normalized Device Performance IEDM Benchmark Technologies ITRS Projections Experimental (bulk-Si) Data 1.00 : Projected forward Bulk-Si Transport Properties “Best Case” Historical Trend (17% per year) 0.10 1985 1990 1995 2000 2005 Year 2010 2015 2020 MIT Antoniadis Single Gate Non-classical CMOS Device Transportenhanced Devices Ultra-thin Body Source/Drain Engineered Devices FD Si film isolation Application/ Driver Strained Si, Ge, SiGe, SiCGe or still other semiconductor; on bulk or SOI HP CMOS D Ground BOX (<20nm) Plane Bulk wafer Silicon Substrate Concept S Fully depleted SOI with body thinner than 10 nm HP, LOP, and LSTP CMOS Ultra-thin channel and localized ultrathin BOX HP, LOP, and LSTP CMOS Gate Gate BOX buried oxide silicide Bias nFET Strained Si, Ge, SiGe pFET S D Non-overlapped region Silicon Schottky barrier isolation Schottky source/drain HP CMOS Nonoverlapped SD extensions on bulk, SOI, or DG devices HP, LOP, and LSTP CMOS Multiple Gate Non-classical CMOS Device Multiple Gate FET N-Gate (N>2) FET Double-gate FET GATE Gate SOURCE Source Drain n+ n+ Si-substrate Concept Application/Driver Tied gates (number of channels >2) HP, LOP, and LSTP CMOS Tied gates, side-wall conduction HP, LOP, and LSTP CMOS DRAIN STI Tied gates planar conduction HP, LOP, and LSTP CMOS Independently switched gates, planar conduction LOP and LSTP CMOS Vertical conduction HP, LOP, and LSTP CMOS Technology Enhancements for High Performance Calculations performed using MASTAR – ST Microelectronics – T. Skotnicki Technology Enhancements for High Performance f (THz) 10 1 0.1 2000 2005 2010 2015 2020 Year Calculations performed using MASTAR – ST Microelectronics – T. Skotnicki Scope of Emerging Research Devices Bulk CMOS New Memory and Logic Technologies Double-Gate CMOS New Architecture Technologies Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts Emerging Research Devices Requirements & Motivations for Beyond CMOS Fundamental Requirements Energy restorative functional process (e.g. gain) Compatible with CMOS At or above room temperature operation Compelling Motivations Functionally scaleable > 100x beyond CMOS limit High information processing rate and throughput Minimum energy per functional operation Minimum, scaleable cost per function 2003 ITRS Emerging Research Devices MEMORY • Phase Change Memory • Floating body DRAM • Nanofloating Gate Memory • Single Electron Memory • Insulator Resistance Change Memory • Molecular Memory LOGIC • Rapid Single Flux Quantum Devices • 1D structures • Resonant Tunneling Devices • Single Electron Transistors • Molecular devices • Quantum Cellular Automata • Spin Transistors Emerging Research Memory Devices Emerging Research Memory Devices Memory element Capacitor Floating body DRAM • Charge stored in body of PDSOI MOSFET Resistor Phase-Change memory - R=f(crystalline - or amorphous - phase) Nanofloating Gate Memory • Flash with engineered tunnel Insulator resistance barrier OR charge stored on change Memory silicon nano-crystals • R=f(formation/dissolution of metal nanowire?) Single-electron memory • Charge stored on a quantum Molecular Memory dot channel of an Single R=f(bias voltage) Electron Transistor (SET) Floating Body Cell (FBC) of nFET on PD-SOI “1” Write: WL(+) BL(+ ) Operation of the cell in saturation injects holes into the body. “0” Write: Forward-biasing of the pn junction ejects holes from the body. (T.Ohsawa et. al.,©ISSCC’02,p.152) WL(+) BL() Medium-Term Emerging Devices Nano Floating Gate Memory Gate Gate Engineered barrier memory nodes memory node n+ n+ n+ n+ Si Si (A) Engineered tunnel barrier (B) Nanocrystal Nanofloating gate memory is evolution of conventional floating gate (FLASH) memory Nanofloating gate memory (NFGM) NFGM includes several possible evolutions of conventional floating gate memory. • Graded tunnel barrier – Engineered shape of tunnel barrier •Nano-sized memory node – Multiple silicon nanocrystal dots The multiple floating dots are separated and independent, and electrons are injected to the dots via different paths. The endurance problem can be much improved in multidot (nanocrystal) memory The Graded (crested) Barrier Concept • Engineered tunnel barriers serve to increase the write/erase performance of memory cells with keeping long retention time typical for floating gate memories. • Uses a stack of insulating materials to create a special shape of barrier enabling effective FowlerNordheim tunneling into/from the storage node. Nanocrystal Memory • Smaller write time – Smaller number of electrons per bit • Larger retention time – Prevents discharge through a localized path in defective insulator – Minimizes edge effects • Low write voltage – Field enhancement at nanodots • Multibit-per-cell storage • Improved endurance – Write current density is uniformly distributed along the nanodots – Write current per nanodot is self-limited by Coulomb blockade Phase Change Memory Structural States in Phase - Change Materials Changes in Resistance ENERGY BARRIERS Ge2Sb2Te5 R Energy AMORPHOUS INTERMEDIATE POLY CRYSTALLINE Atomic Order I, mA Tyler Lowrey, Energy Conversion Devices, Inc., http://www.ovonic.com Molecular Memory Current (pA) • Using individual molecules as building block of memory cells • Data are stored by applying external voltage that cause the transition of the molecule into one of two possible phase states. Reading data is performed by measuring resistance changes in the molecular cell • It is possible to combine molecular components with existing technology e.g. DRAM and floating gate memory IV Characteristics 1 1 Source: M.Reed et al - Yale U and Rice U. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Voltage (V) Factor 1 - - Individual Performance Potential for each Technology Evaluation Criterion 3 2 1 Substantially exceeds CMOS * or is compatible with CMOS architecture ** or is monolithically integrable with CMOS wafer technology ***or is compatible with CMOS operating temperature Comparable to CMOS * or can be integrated with CMOS architecture with some difficulty ** or is functionally integrable (easily) with CMOS wafer technology ***or requires a modest cooling technology, T > 77K Substantially (2×) inferior to CMOS * or can not be integrated with CMOS architecture ** or is not integrable with CMOS wafer technology ***or requires very aggressive cooling technology, T < 4K Factor 2 - - Individual Risk Assessment for each Technology Evaluation Criterion 3 Solutions to accomplish most of the Technology Evaluation Criteria for the Technology Entry are known resulting in lowest risk 2 Concepts to accomplish most of the Technology Evaluation Criteria have been proposed for the Technology Entry and are judged to be of moderate risk 1 No solutions or concepts have been proposed accomplish most of the Technology Evaluation Criteria for the Technology Entry and are judged to be of highest risk Overall Performance and Risk Assessment for Technology Entries Overall Performance and Risk Assessment (OPRA) = Sum [(Performance Potential) x (Risk Assessment)] (Summed over the eight Evaluation Criteria for each Technology Entry) Maximum Overall Performance and Risk Assessment (OPRA) = 72 Minimum Overall Performance and Risk Assessment (OPRA) = 8 Overall Performance and Risk Assessment for Technology Entries Potential for the Technology Entry is projected to be significantly better than silicon CMOS (compared using the Technology Evaluation Criteria) and solutions to accomplish the most of the Technology Evaluation Criteria are known resulting in lowest risk (OPRA > 50) Potential/ Risk Potential for the Technology Entry is projected to be comparable to or slightly less than silicon CMOS (compared using the Technology Evaluation Criteria) and concepts to accomplish most of the Technology Evaluation Criteria have been proposed and are judged to be of moderate risk (OPRA = 40 – 49) Potential for the Technology Entry is projected to be comparable to or less than silicon CMOS (compared using the Technology Evaluation Criteria) and concepts to accomplish a few of the Technology Evaluation Criteria have been proposed and are judged to be of higher risk (OPRA = 30 – 39) Potential/ Risk Potential for the Technology Entry is projected to be significantly less than silicon CMOS (compared using the Technology Evaluation Criteria) and no solutions or concepts have been proposed accomplish most of the Technology Evaluation Criteria and are judged to be of highest risk (OPRA < 30) Potential/ Risk Potential/ Risk Technology Performance and Risk Evaluation Emerging Research Memory Devices Potential/Risk Operate Energy temp efficiency [E]*** [F] Sensitivity Performance [A] Architecture compatible [B]* Stability and reliability [C] CMOS compatible [D]** Floating Body DRAM 2.3/2.3 3.0/3.0 2.0/2.7 3.0/3.0 3.0/3.0 2.0/3.0 2.3/2.9 2.8/2.7 Phase Change Memory 2.6/2.9 2.2/3.0 2.3/2.2 2.2/3.0 3.0/3.0 1.8/2.7 2.1/2.1 2.7/2.2 Nano-floating Gate Memory 3.0/2.2 2.9/3.0 2.0/2.7 3.0/3.0 3.0/3.0 2.1/2.8 1.6/2.0 2.4/2.0 Insulator Resistance Change Memory 2.4/2.1 2.7/2.7 2.2/2.4 2.1/2.8 3.0/2.9 2.8/2.0 2.1/2.0 2.7/2.4 Molecular Memory 1.6/1.2 1.8/2.0 1.8/1.4 1.9/2.1 2.8/2.3 2.3/1.9 2.1/1.7 2.6/2.2 Single/Few Electron Memory 1.1/1.3 1.9/1.3 1.1/1.0 2.4/1.9 1.3/1.3 2.4/1.2 1.3/1.0 2.6/1.4 Memory Device Technologies parameter) [G] Scalability [H] Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter Emerging Research Logic Devices Binary decision function Rapid Single Flux Quantum Devices Tunneling 1D in superconducting structures structures Drift electron transport in nanowires and nanotubes Resonant Tunneling Devices Resonant Single tunneling in semiconductor heterostructures Electron Transistors Single Molecular electron tunneling and coulomb blockade devices Electron Quantum transport in molecules Cellular Automata Tunneling Spin Transistors Spin transport in transistor structure Rapid Single Flux Quantum RSFQ logic is a dynamic logic based upon a superconducting quantum effect, in which the storage and transmission of flux quanta defines the device operation. The basic RSFQ structure is a superconducting ring that contains one Josephson Junction (JJ) plus an external resistive shunt. The storage element is the superconducting inductive ring and the switching element is the Josephson Junction. RSFQ dynamic logic uses the presence or absence of the flux quanta in the closed superconducting inductive loop to represent a bit as a “1” or “0,” respectively. The circuit operates by temporarily opening the Josephson Junction, thereby ejecting the stored flux quanta. CNT transistor Major Challenges for CNT FETs What are the ultimate limits to the speed, size, density and dissipated energy of an CNT switch (e.g. FET) switch? How can 100 or more CNTs be combined in parallel to provide a total current 100x current of a single CNT? Possibilities for integration of individual CNT components in a complex circuit (billions of components per cm2) are unclear. S. J. Wind,J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, Appl. Phys. Lett 80 (2002) 3817 Single Electron Transistor (SET) island source gate drain Electron movements are controlled with single electron precision Coulomb blockade effect Logic state set by 1) current or 2) phase Quantum Cellular Automata: “Wireless” or Systolic Logic Circuitry? Logic Cell Adder Circuit Technology Performance and Risk Evaluation Emerging Research Logic Devices Potential/Risk Logic Device Technologies 1D Structures RSFQ Devices Resonant Tunneling Devices Molecular Devices Spin Transistor SETs QCA Devices Performance [A] Architecture compatible [B]* Stability and reliability [C] CMOS compatible [D]** Operate temp [E]*** Energy efficiency [F] 2.3/2.2 2.2/2.9 1.9/1.2 2.3/2.4 2.9/2.9 2.6/2.1 2.6/2.1 2.3/1.6 2.7/3.0 1.9/2.7 2.2/2.8 1.6/2.2 1.1/2.7 1.6/2.3 1.9/2.8 1.0/2.1 2.6/2.0 2.1/2.2 2.0/1.4 2.3/2.2 2.2/2.4 2.4/2.1 1.4/1.4 2.0/2.0 1.7/1.3 1.8/1.4 1.6/1.4 2.0/1.6 2.3/2.4 2.6/1.3 2.0/1.4 2.6/1.3 2.2/1.7 1.7/1.6 1.7/1.7 1.9/1.4 1.6/2.0 2.3/2.1 1.4/1.7 2.0/1.4 1.1/1.2 1.7/1.2 1.3/1.1 2.1/1.4 1.2/1.8 2.6/2.0 1.0/1.0 2.1/1.7 1.4/1.3 1.2/1.1 1.7/1.8 1.4/1.6 1.2/1.4 2.4/1.7 1.6/1.1 2.0/1.4 Sensitivity Scalability parameter) [H] [G] Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter Emerging Technology Vectors Emerging Technology Sequence Cellular array RSFQ Phase change Transport enhanced FETs 1-D structures Defect tolerant Resonant tunneling Floating body DRAM UTB single gate FET SET Nano FG Source/Drain engineered FET Biologically inspired Molecular SET QCA Insulator resistance change UTB multiple gate FET Quantum computing Spin transistor Molecular Quasi ballistic FET Risk Architecture Logic Memory Nonclassical CMOS Emerging Research Devices Summary Potential solutions for device structures necessary to achieve the advanced nodes (< 45-nm) identified For the ITRS gate density and switching time Power density (not switch size) limits charge based logic density and performance CMOS is approaching the maximum power efficiency Emerging Research Device Technologies will extend CMOS into new application domains SET-Based Tunneling Phase Logic (TPL) Coulomb Blockade TPL Element E Bias 2 Q 2C Tunnel Junction -e/ 2 e/ 2 Q ac Pump Nonlinear Voltage-Charge Characteristic VJ e/2C q -e/2C e dq e R Vdc Vac cos(t) S(2q / e) dt 2C U. Minnesota UC - Berkeley