Download Topology Selection: Input

Project #2: Design of an Operational
Amplifier
By:
Adrian Ildefonso
Nedeljko Karaulac
I have neither given nor received any unauthorized assistance on this project.
Process: Baker’s 50nm
CAD Tool: Cadence Virtuoso
AI & NK, 10/31/2014
1
Topology Selection: Input
• Input topology decided by ICMR
(0.2–1V) for a supply voltage of 1.2V
• Use folded cascode topology for
high input swing
• PMOS folded cascode (shown in
figure):
– Vin,min = VOVN – VTHP – VSS = -210mV
– Vin,max = VDD – 2VOVP – VTHN = 780mV
• NMOS version would have the same
limitation on the minimum input
Paul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog
Integrated Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.
voltage
Solution: Use parallel NMOS and PMOS folded cascode
differential pair for the input stage.
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MG1
Topology Selection: Output
• Output topology decided by output
swing (0.2–1V)
• Low output resistance is desirable
• Class AB Source follower buffer
(shown in Figure)
– Vout,min = 2VOV + VTHP – VSS = 420mV
– Vin,max = VDD – 2VOV – VTHN = 780mV
• Must use class AB Push-Pull
amplifier, which will also be a
second gain stage
Paul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog
Integrated Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.
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Selected Topology
• Selected Topology:
– Input: Parallel NMOS and PMOS Folded Cascode
– Output/Second Stage: Push-Pull Amplifier
• Benefits
– Rail to Rail input
– High Swing output
– Higher Gain
• Drawbacks
– Gain is not constant across input range (not an issue due to high
open loop gain)
– Gain highly dependent on resistive load
– Added power consumption due to parallel differential amplifier
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MG2
Design
• For SR of 120V/us
– IT = SR*CL = 120 uA
• Current in cascode branch is 1.2 – 1.5 times the tail current
• For parallel differential pairs (required to meet ICMR), we
need more than, which is over the required power
• After literature review, no circuit was found (in research or
industry) that meets all the criteria for this project.
• We decided to sacrifice SR and BW in order to save power
• Tail current chosen: 40 uA
• This means that our SR should be around 40 V/us
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Design
• Because we are no longer concerned with ICMR, we can
choose any overdrive voltage for the input differential pair.
• Let’s choose 50mV to obtain higher gm.
• This would require W/L of NMOS input pairs to be around
150/2 = 7.5u/100n and PMOS to be 300/2 = 15u/100n
• Cascode transistors were chosen to conduct 1.3 times
current in one side of the differential pair to prevent them
from turning on.
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Design
• Output stage is a push pull amplifier, sized to conduct 20uA
• Cascode device was added to increase output resistance
and gain
• Compensation capacitor was added before the cascode
device to use the cascode as a buffer
– This helped greatly with the frequency response of the amplifier but
did not remove the RHPZ
– Resulted in bigger compensation capacitor because now the miller
capacitance is in series with the CDS of the cascode device,
reducing the effective capacitance
– Zero nulling resistor was added to remove RHPZ
7
AI & NK, 10/31/2014
Reference Schematic
Used topology in Baker’s Figure 20.47
Resistor value changed to obtain
desired currents
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MG3
Amplifier Schematic
Note these devices are 1.3 time the size of
the tail current sources. Also true for
NMOS at the bottom
Cascode tail currents to
increase CMRR
Note cascode output to
increase gain and output
resistance. This requires
complementary
compensation as shown
Complementary Folded
Cascode Differential Pair
Push/Pull Output Stage
9
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MG4
MG5
Simulation Test benches
Inductor in feedback
Open Loop Gain: Frequency sweep at input
ACM : Frequency sweep with shorted inputs
Buffer configuration
ICMR: DC sweep from -0.2 to 1.4
SR: Step from 0.1 to 1.1 V
THD: 1kHz Sine wave covering full output swing
Non-inverting Amplifier
Output Swing: Sweep input from -0.2 to 1.4
and see where output saturates
Note: Infinitely large inductor is used
to act as a short in DC but open in
AC. It allows for Cadence to
calculate the DC operating point
correctly.
AC sources on supply
PSRR: Sweep frequency at VDD and GND.
AI & NK, 10/31/2014
Note: iprobe acts as a short in
DC but open in AC. This is the
same as using an infinitely large
inductor, and the same
simulation values were obtained.
Inductor was used in Open Loop
Gain because it was easier to
simulate CMRR.
iprobe in feedback
Noise: Perform noise analysis on Cadence
10
Open Loop Response
Nam
Vis
3d
DC Gain
3dB Frequency
Unity Gain
180.0
135.0
179.9968deg
90.0
45.86191deg
Phase (deg)
45.0
134.8967deg
0.0
-45.0
-90.0
-135.0
-180.0
-225.0
-270.0
-315.0
-360.0
100
80.0
Open Loop Gain (dB)
60.0
80.22635dB
77.22662dB
40.0
20.0
0.0
35.4858udB
-20.0
-40.0
-60.0
-80.0
-100
0
10
1
2
10
3
10
10
4
10
5
10
Frequency (Hz)
6
7
10
10
8
10
9
10
10
10
11
AI & NK, 10/31/2014
Input and Output Swing
1.25
1.25
Min Input: ( 55.929347mV, 990.0m)
1.0
.75
Max Input: ( 1.1597325V, 990.0m)
.5
.5
.25
.25
0.0
0.0
-.25
1.25
-.25
12.5
1.0
dVout/ dVin
.75
10.0
Max Output: 1.0756326V
.75
7.5
.5
5.0
.25
2.5
dVout/ dVin
Vout (Non-Inverting Amplifier, A = 10) ( V)
Vout ( Buffer) ( V)
1.0
0.0
0.0
Min Output: 58.881285mV
-.25
-2.5
-.25
0.0
.25
.5
.75
1.0
1.25
1.5
Vin ( V)
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Transient Response
M6: 1.1595978us 1.0985998V
M3: 1.5042119us 1.0001732V
1.0
M1: 1.0202096us 1.0V
Voltage (V)
.75
.5
.25
M2: 1.0024586us 199.78604mV
M5: 1.6098323us 100.21264m
M4: 1.5279524us 200.41284mV
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Time ( us)
13
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PSRR
V1
-20.0
PSRR - VDD ( dB)
-30.0
-40.0
-50.0
-64.79598dB
-60.0
-70.0
-10.0
PSRR - GND (dB)
-20.0
-21.762635dB
-30.0
-40.0
-50.0
0
10
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1
10
2
10
3
10
4
10
5
10
freq (Hz)
6
10
7
10
8
10
9
10
10
10
14
Noise
15
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MG6
Spec Summary
Target
Achieved
Differential amplifier topology
Spec
N/A
Parallel Folded
Cascode
Reference topology
N/A
Baker 50 nm
Supply (V)
1.2
1.2
1 || 100
1 || 100
Loading (pF || kOhm)
Differential Gain (dB)
80
80.23
CMRR (dB)
120
94.76
ICMR (V)
0.2 - 1
56m – 1.16
Output Swing (V)
0.1- 1.1
59m – 1.08
Bandwidth - 3dB (kHz) (Loaded/Unloaded)
100
18.47 / 1.69
Gainbandwidth product (MHz)
N/A
76.4
Compensation capacitor (pF)
N/A
See schematic
Phase margin (degrees)
45
45.86
Gain of differential amplifier (dB)
N/A
47.7
Max Power consumption (uW) (Loaded/Unloaded) (Buffer Configuration)
200
178.4 / 173.5
Reference power consumption (uW)
N/A
93.4
OpAmp power consumption with zero input (uW) (Buffer Configuration)
N/A
178.4
Total power consumption (uW)
Slew Rate (V/us) (Positive/Negative)
AI & NK, 10/31/2014
N/A
271.8
120 / -120
40 / -34.7
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Spec Summary Cont’d
Target
Achieved
Supply Voltage (V) (Maximum/Minimum)
Spec
N/A
0.55 / 3.06
Nominal output voltage (V)
N/A
0.6
Input offset voltage (mV)
N/A
-12
Rise/Fall time (ns) (to 90% of final value)
N/A
20 / 23
Settling time (ns) (Rising / Falling Edge)
N/A
160 / 109
RMS Input referred noise (V) (1 Hz – 100MHz) (Simulated in open loop)
N/A
7.51 n
THD for full swing output (%) (Simulated in Buffer mode)
N/A
1.165 %
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How to improve design?
•
To improve CMRR, make tail current sources longer to increase RTail
•
•
To improve SR, increase tail current and current at output stage.
Ideally a buffer should be used for the output, but implementation of
high-swing low impedance buffer is difficult. Using a buffer would make
gain and bandwidth independent of loading
MG7
Use advanced
compensation techniques, such as those shown in the
references, to reduce capacitor size and increase phase margin
Better match currents in PMOS and NMOS differential pairs to reduce
offset voltage. This can be done by selecting a different overdrive
voltage for the input devices so that the tail current sources have a VDS
that results in better current matching. Constant gm amplifier might
also reduce this offset.
•
•
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Conclusion
• Completed design of two stage operational amplifier
• Opted for low power operation instead of high speed (SR
and Bandwidth)
• Parallel input differential pairs were necessary to meet
ICMR requirements
• Push pull amplifier was needed to meet output swing
requirements. Cascode devices were added to increase the
gain and output resistance. However, buffer should be used
for the output
• Design could be improved with relaxed power
specifications
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References
•
•
•
•
•
•
•
R. Jacob Baker. 2010. CMOS Circuit Design, Layout, and Simulation (3rd ed.). WileyIEEE Press.
Paul R. Gray and Robert G. Meyer. 1990. Analysis and Design of Analog Integrated
Circuits (2nd ed.). John Wiley & Sons, Inc., New York, NY, USA.
Grasso, A.D.; Palumbo, G.; Pennisi, S., "Comparison of the Frequency Compensation
Techniques for CMOS Two-Stage Miller OTAs," Circuits and Systems II: Express Briefs,
IEEE Transactions on , vol.55, no.11, pp.1099,1103, Nov. 2008
http://www.eit.uni-kl.de/koenig/deutsch/TESYS_Lutgen_09.pdf
http://www.ece.tamu.edu/~spalermo/ecen474/lecture14_ee474_folded_cascode_ota.pdf
http://www.ijser.org/researchpaper%5CDESIGN-OF-HIGH-GAIN-FOLDED-CASCODEOPERATIONAL-AMPLIFIER-USING-1.25-M-CMOS-TECHNOLOGY.pdf
http://www.aicdesign.org/SCNOTES/2010notes/Lect2UP250_%28100328%29.pdf
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