Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Electronic engineering wikipedia , lookup
Electronic paper wikipedia , lookup
Fault tolerance wikipedia , lookup
Skin effect wikipedia , lookup
Aluminium-conductor steel-reinforced cable wikipedia , lookup
Portable appliance testing wikipedia , lookup
Surface-mount technology wikipedia , lookup
IPC-2292 Working Draft Master April 2017 IPC-2292, Design Standard for Printed Electronics on Flexible Substrates Master Working Draft – April 2017 1 SCOPE This standard establishes specific requirements for the design of printed electronic applications and their forms of component mounting and interconnecting structures on flexible substrates. Flexible substrates, as pertain to this standard, are materials or devices which have some amount of flexibility or bendability (not rigid) but are not considered to be stretchable (e.g., fabrics, textiles, stretchable polymers, etc.). IPC plans to address printed electronics design for other materials and device types (rigid, 3D, fabrics, etc.) in separate standards. 1.1 Standard Printed Electronics Design (SPED) Classifications Standard print electronics design (SPED) types shall be in accordance with 1.2.1 through 1.2.3. For purposes of explanation, a basic variation of each SPED is shown in 1.2.1 through 1.2.3. See Appendix A for an extended collection of examples showing how the SPEDs can be used alone or in combination with other SPEDs (e.g., SPED1/SPED3, SPED1/SPED2/SPED3, etc.). Each IPC-2292 SPED consists of the following components: Substrate – Any flexible nonconductive and/or conductive (e.g., flexible PWB or other manufactured functional part) material. Printed element – Any conductive, semiconductive or dielectric material applied using additive/printing processes. Surfaces – The top and bottom sides of the substrate o First surface is the top of substrate o Second surface is the bottom of substrate Each additive process required to manufacture the finished flexible printed electronic is identified with an alphanumeric designation. The letter F (first/top surface) or S (second/bottom) indicates side of the substrate. The number indicates the print/process step. For example: F1 = first print on the first/top surface F2 = second print on the first/top surface S1 = first print on the second/bottom surface S2 = second print on the second/bottom surface It is important to note that the print/process step numbers can be repeated on each side, because the numbers only apply to printing elements on a specific side. 1.2.1 IPC-2292/SPED1 SPED1 has printed element(s), which can include vias between printed conductive elements, on one or both surfaces of a substrate. SPED1 does not have electrical/electronic interconnections from printed element(s) to the substrate. IPC-2292 Working Draft Master April 2017 Figure 1-1 IPC-2292/SPED1 1.2.2 IPC-2292/SPED2 SPED2 has printed element(s), which can include vias between printed conductive elements, on one or both surfaces of a conductive substrate and which are interconnected to the conductive substrate Figure 1-2 IPC-2292/SPED2 1.2.3 IPC-2292/SPED3 SPED3 has printed element(s) on both substrate surfaces (F and S), and those printed elements are also connected together through the substrate (via). IPC-2292 Working Draft Master April 2017 Figure 1-3 IPC-2292/SPED3 2 APPLICABLE DOCUMENTS 2.1 IPC IPC-FC-234 IPC-OI-645 IPC-TM-650 Method 2.5.4.1a3 Method 2.5.4.1a Method 2.5.6 Method 2.5.7 Method 2.5.7.2 IPC-CM-770 IPC-SM-780 IPC-CC-830 IPC-2221 IPC-2316 IPC-2500 IPC-2610 IPC-4202 IPC-4203 IPC-4204 IPC-4591 IPC-4921 IPC-7351 IPC-9191 IPC-9252 3 GENERAL REQUIREMENTS The information contained in this section describes the general parameters to be considered by all disciplines prior to and during the design cycle. Designing the physical features and selecting the materials for printed electronics involves balancing the electrical, mechanical and thermal performance as well as the reliability, manufacturing and cost of the printed electronics. The considerations in Table 3-1 identifies the probable effect of changing each of the physical features or materials. The items in the table need to be considered if it is necessary to change a physical feature or material from one of the established rules. Cost can also be affected by these parameters. IPC-2292 Working Draft Master April 2017 3.1 Terms and Definitions 3.1.1 Crease To make a line, ridge or groove on a printed electronic device by adding pressure to fold the substrate or device. 3.1.2 Panelization Panelization is a method used to reduce manufacturing costs. Panelization consists of a number or array of PCB’s which are grouped on to a substrate panel. Panel optimizer’s maybe used to determine the most efficient placement of the PCB’s array within the panel. The optimizer calculates all panel placement combination based on the panel dimensions and the PCB’s to be manufactured. 3.1.3 Substrate For purposes of this standard, a substrate is any conductive or nonconductive flexible manufactured part or base material. A variety of materials can be used as a base substrate from traditional flexible PWB materials to paper and other flexible materials. See 4.1.1 for properties that should be considered when selecting a base material. 3.2 Information Hierarchy 3.2.1 Order of Precedence In the event of conflict, the following order of precedence shall apply: 1. The procurement contract. 2. The master drawing or assembly drawing (supplemented by an approved deviation list, if applicable). 3. This standard. 4. Other applicable documents. 3.2.2 End-Product Performance Requirements The end-product performance requirements shall be defined prior to design start-up. Maintenance and serviceability requirements are important factors which should be addressed during the design phase. Frequently, these factors affect layout and conductor routing. Finished printed electronics shall meet the performance requirements as agreed upon between user and supplier. 3.3 Design Considerations The design process should include a formal design review of details by as many affected disciplines within the company as possible, including fabrication, assembly and testing. The approval of the layout concepts by representatives of the affected disciplines will ensure that these production-related factors have been considered in the design. The success or failure of a Printed Electronics design depends on many interrelated considerations. From an end-product usage standpoint, the impact on the design by the following typical parameters should be considered: Equipment environmental conditions in which the printed electronics are installed, such as ambient temperature, heat generated by the printed electronics, ventilation, shock IPC-2292 Working Draft Master April 2017 and vibration. If an assembly is to be maintainable and repairable, consideration shall be given to printed component/circuit density, the selection of conformal coating or final finish protective materials (although not normally considered for PE), installation interface that may affect the size and location of mounting holes, connector or electrical interface locations, and the placement of brackets and other hardware. Testing/fault location requirements that might affect printed component placement, conductor routing, interface or connector contact assignments, etc. Manufacturing limitations such as minimum conductor thickness, width, and spacing, shape or profile, and size. Coating and marking requirements. Assembly technology used, such as SMT, through hole, and mixed. Materials selection (see Section 4). Producibility of the printed electronics assembly as it pertains to manufacturing equipment limitations. This includes: Flexibility (Flexural) Requirements Electrical/Electronic ESD sensitivity considerations. Conductor density per layer. Balanced construction. Compatibility of materials, sintering temperatures, effect on adhesion etc. Partitioning of design for signal integrity, test and ease of design reuse, etc. Partitioning is performed in the preliminary printed electronic design phase. It includes trade-off studies, usually including several design concepts that could solve the problem. These design concepts are functionally block diagrammed and, as with any trade-off, a set of advantages and disadvantages is formulated and evaluated by the designer to make his decision on which solution is optimal for this design. It is at this point important to ensure all functional requirements, test connections, and any known growth requirements are being considered. These should flow from the project requirements as documented in the design requirements. The test requirements and growth requirements may not need to be implemented during the electrical design phase, but the interfaces, including printed elements, field programmable logic (FPL), and memory assets, should be allocated. The design partitioning for each concept needs to evaluate what can be implemented on the printed electronic. The following questions should be answered: What are the control requirements? What are the memory requirements? What are the data path requirements? What are the I/O requirements? It is difficult to convey all the considerations that should be evaluated. The few here have been included to provoke the thought process. Users are encouraged to consult with experienced designers if there is a need for assistance. 3.4 Schematic/Logic Diagram The initial schematic/logic diagram designates the electrical functions and interconnectivity to be provided to the designer for the printed electronics including its printed components. This schematic should define, when applicable, critical circuit layout areas, shielding requirements, grounding and power distribution requirements, the allocation of test points, and any preassigned input/output IPC-2292 Working Draft Master April 2017 connector locations. Schematic information may be generated as hard copy or computer data (manually or automated). 3.5 Density Evaluation A wide variety of materials and processes are used to create substrates for printed electronics. They all share a common attribute in that they provide a base to route signals through printed conductors. 3.6 Parts List A parts list, or bill of materials (BOM), is a tabulation of parts and materials used in the construction of a printed electronic. All end item identifiable parts and materials shall be identified in the parts list or on the field of the drawing. Excluded are those materials used in the manufacturing process, but may include reference information; i.e., specifications pertinent to the manufacture of the assembly and reference to the schematic/logic diagram. All mechanical parts appearing on the assembly pictorial shall be assigned an item number which shall match the item number assigned on the parts list. Printed electrical components, such as capacitors, resistors, fuses, ICs, transistors, etc., shall be assigned reference designators, (Ex. C5, CR2, F1, R15, U2, etc.). Electrical reference designators shall match the assignments given to the same components on the Logic/schematic diagram. It is advisable to group like items; e.g., resistors, capacitors, ICs, etc., in some sort of ascending or numerical order. The parts list may be handwritten, manually typed on to a standard format, or computer generated. 3.7 Test Requirement Considerations Normally, prior to starting a design, a testability review meeting should be held with fabrication, assembly, and testing. Testability concerns, such as circuit visibility, density, operation, circuit controllability, partitioning, and special test requirements and specifications are discussed as a part of the test strategy. During the design testability review meeting, tooling concepts are established, and determinations are made as to the most effective tool-cost versus printed electronic layout concept conditions. See 3.7.1 for layout recommendations relative to testability. During the layout process, any printed electronic changes that impact the test program, or the test tooling, should immediately be reported to the proper individuals for determination as to the best compromise. The testing concept should develop approaches that can check the printed electronic for problems, and also detect fault locations wherever possible. The test concept and requirements should economically facilitate the detection, isolation, and correction of faults of the design verification, manufacturing, and field support of the printed electronic life cycle. As printed structures build up with the addition of each layer, interim testing may be considered. As reworkability of inner layers becomes more difficult with the addition of each layer, the designer should consider the trade-offs between interim testing and associated yield costs. If interim tests are warranted, access to and testability of the interim design should be considered. 3.7.1 Electrical 3.7.1.1 Bare Printed electronic Testing When electrical testing is required it shall be specified in accordance with IPC-9252 including the assignment of a ‘‘Test Level’’ and including any user defined ‘‘AABUS’’ (As Agreed Between User and IPC-2292 Working Draft Master April 2017 Sup-plier) test options. It is the responsibility of the user to define test requirements appropriate to the end use of the printed electronic device. The selection of requirements should be carefully considered as these will at least in part determine the relative effectiveness of any test procedure. For example, electrical testing methods optimized for higher productivity may be less capable of detecting certain defects. The user is encouraged to discuss available test options with the supplier so that the appropriate requirements can be developed, which will provide the appropriate level of quality while allowing the greatest freedom in the supplier’s use of available tools. User defined options may include the following: Isolation Test Voltage for ‘‘Resistive Testing’’ (Maximum rated voltage should be specified; if not specified, it will be 40 volts minimum, which may not be sufficient to detect leakage failures). Continuity Test Current for ‘‘Resistive Testing.’’ Horizontal Adjacency Vertical Layer Adjacency Indirect Isolation and Continuity Testing by ‘‘Signature Comparison’’ ‘‘Hi-Pot’’ testing of dielectric integrity. Impedance testing of specialized circuitry. Embedded capacitance and or embedded resistance (test requirements for this technology are not covered by IPC-9252). Refer to IPC-2316 for guidance. Testing of other printed electronic components used in the PE design shall be AABUS. If test requirements are not otherwise defined they shall be tested to default IPC-9252 Test. 3.7.1.2 Test Methods The following electrical test methods are available or optional to the supplier in accordance with IPC9252. Not all test methods have an equal potential for effectiveness. Because of the variations in equipment, training, and practice no method should be considered as ‘‘100-percent’’ effective. a) Resistive Continuity Testing: This type of test measures the resistance of the net under test. If the resistance is lower than the specified threshold, the network under test passes. If resistance is higher than the specified threshold, the net-work under test fails and an open is reported. Minimum test thresholds are in accordance with IPC-9252. The test current applied shall not exceed that allowed for the smallest conductor in that circuit and should be stated on the master drawing. Resistive Continuity Testing may be performed on a fix-grid or a fixtureless moving-probe (flying-probe) or moving grid test system. b) Resistive Isolation Testing: This type of testing verifies that electrically isolated networks meet the minimum resistive threshold. If the isolation resistance measured is higher than the minimum specified in IPC-9252, the network passes. Faults detected are defined as either shorts or leakages. Resistive Isolation Testing may be performed on a fix-grid or a fixtureless moving-probe (flying-probe) system. However, the use of a moving-probe test system for resistive isolation testing may be considered impractical unless the supplier is permitted to use one of the adjacency sorting protocols to increase productivity the details of which (including adjacency distance) should be developed between user and supplier. c) Indirect Isolation & Continuity Testing by Signature Comparison: This type of testing indirectly verifies electrical isolation and continuity by measuring and recording electrical properties (such as capacitance, RF, impedance, etc.) of a printed electronic under test IPC-2292 Working Draft Master April 2017 and comparing them to a measured or calculated reference value which is capable of distinguishing between manufacturing and design faults. When faults by the indirect method are verified by the resistive method, they are classified as shorts, leakages, or opens. Otherwise network resistance values are not measured and should not be specified without exception where the intent is to allow the use of indirect testing. Indirect test methods are used with moving probe test systems running proprietary test software. d) Insulation Resistance Test This test is used to provide a quantifiable resistance value for all of a product’s insulation. A Direct Current (DC) test voltage is applied. The voltage and measured current value are used to calculate the resistance of the insulation. e) Flexibility Testing: IPC-9204 lists test methods that can be used to verify the reliability of printed electronics after bending, creasing or stretching. It will be up the application to determine which of the test methods listed should be used for product validation. In cases of hybrid applications, IPC-9204 also lists test methods that can be used to verify the bond strength of surface mount devices (SMDs) on printed conductors. In addition to the test methods listed in IPC-9204, the following test methods can also be used: ASTM F1681, Test Method for Determining the Current Carrying Capacity of Printed Conductive Material ASTM F1896, Test Method for Determining the Electrical Resistivity of a Printed Conductive Material ASTM F1995, Test Method for Determining the Shear Strength of the Bond between a Surface Mount Device (SMD) and Substrate ASTM F3147, Test Method for Evaluating of a Surface Mount Device (SMD) Joints on a Flexible Circuit by a Rolling Mandrel Test 3.7.1.2.1 HiPot Testing A HiPot test (also called a Dielectric Withstanding Voltage Test) verifies that the insulation of a product or component is sufficient to protect the hardware. In a typical HiPot test, high voltage is applied between a product’s current-carrying conductors and its metallic chassis. The resulting current that flows through the insulation, known as leakage current, is monitored by the HiPot tester. The theory behind the test is that if a deliberate over-application of test voltage does not cause the insulation to break down, the product will be safe to use under normal operating conditions. Three common high voltage tests include: Dielectric breakdown test (IPC-TM-650, Method 2.5.6) – The test voltage is increased until the dielectric fails, or breaks down, allowing too much current to flow. This test is performed on an Acceptable Quality Level (AQL) sample basis by the laminate material supplier. This test allows designers to determine the breakdown voltage of a product’s design. This value is often provided in the material supplier’s laminate specification sheet. Dielectric withstanding voltage (DWV) test (IPC-TM-650, Method 2.5.7) – A standard test voltage is applied (below the established Breakdown Voltage) for a specific length of time to determine any occurrence of flashover, spark over or breakdown. This test is routinely done on a monthly basis. Dielectric withstanding voltage (IPC-TM-650, Method 2.5.7.2) – thin dielectric layers and planar capacitance layers - The test voltage, voltage ramp rate, hold time at peak voltage, and current threshold are pre-programmed into the HiPot tester. This test allows IPC-2292 Working Draft Master April 2017 designers to determine the breakdown voltage of a product’s design. This value is often provided in the material supplier’s laminate specification sheet. Note: Capacitance effect within the printed electronic may affect testing procedures. The following are design considerations and documentation requirements for designs requiring high pot testing: a) Design Considerations 1) Inadequate (current) creepage distance between holes (conductor migration). 2) Inadequate clearance distances between conductive geometries in both the horizontal and vertical directions. Consideration should be given to laminate anomalies such as ‘‘eyebrow’’ cracks, which may affect the test result. 3) Solder mask or coating characteristics and thickness. 4) Dielectric characteristics. b) Documentation requirements 1) Peak voltage desired, which typically is specified by the user. 2) Specific circuit locations identified, if testing is required. 3) Voltage ramp rate. 4) Hold time at peak voltage. 5) Sampling plan for testing. 3.7.1.2.2 Impedance Considerations Conductor width and spacing is determined by modeling electrical impedance values in conjunction with printed element stack-up using a reliable industry accepted impedance calculator. Due to material and fabrication process variations, fabricator calculations will provide more accurate results. Coupons may be specified for evaluation of impedance requirements. 3.7.1.3 Test Data (Source Data) The designer should provide the manufacturer a schematic, bill of materials (BOM) and layout, if applicable. 3.7.2 Printed Electronic Assembly Testability Design of a printed electronic assembly for testability may involve systems level testability issues. In most applications, there are system level fault isolation and recovery requirements such as mean time to repair, percent up time, operate through single faults, and maximum time to repair. To meet the contractual requirements, the system design may include testability features, and many times these IPC-2292 Working Draft Master April 2017 same features can be used to increase testability at the printed electronic level. The printed electronic testability philosophy also needs to be compatible with the overall integrations, testing and maintenance plans for the contract. The factory testers to be used, how integration and test is planned, when printed electronics are conformal coated, the depot and field test equipment capabilities and personnel skill level are all factors that should be considered when developing the printed electronic test strategy. The test philosophy may be different for different phases of the program. For example, the first unit debug philosophy may be much different than the test philosophy for spares when all the systems have already been shipped. Before the printed electronic design starts, requirements for the system testability functions should be presented at the conceptual design review. These requirements and any derived requirements should be partitioned down to the various printed electronics and documented. The system and program level test criteria and how they are partitioned down to the printed electronic requirements are beyond the scope of this document. The two basic types of printed electronic assembly test are functional test and in-circuit test. Functional testing is used to test the electrical design functionality. Functional testers access the printed electronic assembly under test through the connector, test points, or bed-of-nails. The printed electronic assembly is functionally tested by applying pre-determined stimuli (vectors) at the assembly’s inputs while monitoring the assembly’s outputs to ensure that the design responds properly. In-circuit testing is used to find manufacturing defects in printed electronic assemblies. In-circuit testers access the printed electronics under test through the use of either: (1) a bed-of-nails fixture which makes contact with each node on the printed electronic; or, (2) flying probe tester which tests the ends of each net for continuity, and tests the isolation of net to net. 3.7.3 Functional Test Concern for Printed Electronics Functional test requirements necessary for approval of end-item requirements shall be communicated and agreed upon between the end customer and the designer. 3.7.4 Test Points and Connectors Consideration should be made for intermediate test points and interconnects in critical areas for fault isolation testing. 3.8 Layout Evaluation 3.8.1 Printed Electronics Layout Design The design layout should be such that designated areas are identified by function, e.g., power supply section confined to one area, analog circuits to another section, and logic circuits to another, etc. This will help to minimize crosstalk, simplify printed electronic test fixture design, and facilitate troubleshooting diagnostics. In addition, the design should: Ensure that printed components have all testable points accessible Have vias placed away from the device’s edges to allow adequate test fixture clearance. Require the printed electronics be laid out on a grid which matches the design team testing concept. Allow provision for isolating parts of the circuit to facilitate testing and diagnostics. IPC-2292 Working Draft Master April 2017 3.8.1.1 Layout Concepts The printed electronic layout depicts the physical size and location of all printed electronic and mechanical components, and the routing of conductors that electrically interconnect the printed components in sufficient detail to allow the preparation of documentation and artwork. 3.8.2 Feasibility Density Evaluation The designer shall create a feasibility density evaluation. The designer will create the evaluation after being provided approved documents for schematic/logic diagrams, parts lists, end-product requirements and testing requirements, and before beginning the actual drawing of the layout. The designer should base the evaluation on the maximum size of all parts required by the parts list and the total space the parts and their lands will require on the printed substrate, exclusive of interconnection conductor routing. The total printed electronics geometry required for mounting and termination of printed components should then be compared to the total usable device area for this purpose. Reasonable maximum values for this ratio are 70 % to 80 %. 4 MATERIALS 4.1 Material Selection Material type and construction is extremely important in designing flexible printed electronics. Care should be taken in material selection to ensure compatibility with adjacent materials. All materials shall be specified on the master drawing. For clarification, it is suggested that cross-sectional views be used to highlight material selection. See Figure 4-1. F1 Material X F2 Material Y F3 Material X ….. S2 Material W S3 Material Z Figure 4-1 NEED CAPTION 4.1.1 Substrate Material Options Printed electronics may be manufactured using base materials per IPC-4921, functional materials (conductive materials, insulator materials, semiconductor materials, barrier materials, emissive, and other functional materials) per IPC-4591, and adhesives per IPC-4202/IPC-4203/IPC-FC-234. In addition, materials per IPC-4204 and IPC-4203 may be used where individual components are specified. IPC-2292 Working Draft Master April 2017 Printed electronics may also be manufactured on materials which are not covered in this standard. The designer should consider the following properties at a minimum for those materials: Visual Dimensional Mechanical Surface Optical Chemical Electrical Environmental These documents group materials into slash sheets that are generic in nature. This means that materials meeting the minimum requirements have widely different typical properties. It is important to research the various products to choose the one best meeting the design requirements. Designers shall request from the supplier verification that their product meets the characteristics of an applicable material type specification sheet. If the product does not apply to a standardized material type specification sheet, the designer shall request the supplier to complete a blank specification sheet for the material type and submit it to the designer. The supplier should also be encouraged to submit the completed specification sheet to the IPC committee responsible for the material standard for inclusion in an amendment or revision of the standard. The following are some common substrate materials used for printed electronics and considerations for each: Polyester (polyethylene terephthalate (PET)) film - Raw polyester with no treatment or coating - Heat-stabilized polyester - Print treatment with coating - Print treatment with chemical etching - Available in variations of thickness, color and transparency Polyethylene-naphthalate (PEN) film - Withstands higher temperature than PET film Polyimide film - Even higher temperature stability, used also for wave solder SMT attach Polycarbonate film - Very clear film - Used for nameplates and growing interest in in-mold electronics - not as flexible as PET The materials in the preceding list are flexible, but most practically in only two dimensions at once. For more pliable and easily deformed printed electronics new substrate is becoming popular. Thermoplastic urethane (TPU) - Many grades with varied performance - Supplied in varied format (e.g., on release liner, applied to fabric or stand-alone film) - Valuable features (e.g., elastic recovery, weldability, moisture prevention, etc. IPC-2292 Working Draft Master April 2017 are available Resin-coated Fabric - Difficult to print conductive ink directly to fabric - Resin provides a smooth surface to allow vacuum hold-down – ideal for printed electronics - Many resin and fabric combinations are available Ink-transfer system - Used in the textile industry - Common decorative transfer inks are the substrate for the conductive inks which, when printed together in layers - Can be heat-laminated onto fabrics or other films See 4.1.1.1 through 4.1.1.7 for special considerations for material selection of flexible printed electronics. 4.1.1.1 Flex Applications Flex ductility, minimal thickness and minimal difference in flexible properties between layers are all key considerations when designing for dynamic flex. Consider the application and choose materials that can withstand the dynamic flexural requirements for the design. Minimize delta in flexibility and other properties of substrates and printed layers. IPC-9204 lists a variety of potential tests including variable bend, variable angle, free arc bending, DaMattia flexibility, and many others. Considerations should include: Number of cycles / fatigue; Multi-axis flex or single axis; Flexure approaching minimum bend radius. Key performance metrics include maximum allowable changes in resistance, adhesion, continuity. 4.1.1.2. Stretch and Elongation IPC-2292 Working Draft Master April 2017 Consider the application and choose materials that can withstand the stretch and elongation requirements for the design. Meander patterns on a nonstretchable film to allow stretch of the assembly (see Figure 4-2). Material thickness, tensile modulus, and adhesion between layers are all important parameters to consider (see IPC-9204). Figure 4-2 Meander Pattern 4.1.1.3 Crease and Crumple Flexible materials can experience bends that are non-recoverable. Consider the design needs and select materials that can achieve the minimum bend radii that are required. Crease susceptibility for flexible printed electronics can be addressed using many test methods listed in IPC 9204. ASTM Test Method F2749 is recommended specifically for documenting the resistance change when creasing a substrate with printed conductors. 4.1.1.4 Gap Bridging Applications In printed electronics there can be a need to bridge the printed materials over gaps. Consider required build angles and maximum span for self-supporting materials. Secondary support materials that are removed in post processing can be considered for some applications. For gap bridging and other applications that require free-standing features, the viscosity, cure process and shrinkage of materials are key considerations for self-supporting materials. The material deposit aspect ratio discussed in 4.1.2 will be another important factor. Secondary support materials can also be utilized. Mechanical and electrical properties, compatibility with interfacing materials, and process conditions are considerations when choosing secondary support materials. 4.1.1.5 Via Hole Aspect Ratio/Material Deposit Aspect Ratio The achievable aspect ratio is a key parameter to consider when generation of 3D features and through holes is required. The maximum achievable aspect ratio (via hole height/via hole width or printed height/printed width) will be dependent on the viscosity of the material to be printed, shrinkage IPC-2292 Working Draft Master April 2017 properties of the printed material when cured and the registration tolerances of the equipment printing the multiple materials and/or generating the holes. Hole aspect ratio = D / W (Fig 4-2a) Where, D = Opening Depth W = Opening Width Material deposit aspect ratio = H / W (Fig 4-2b) Where, H = printed conductor height W = printed conductor width Figure 4-2a.Hole Aspect Ratio Figure 4-2b.Material Deposit Aspect Ratio 4.1.1.6 Process Compatibility The materials and processes used will determine compatibility with subsequent processing, such as plating, soldering, coating, etc. The maximum temperature a material can withstand is an important consideration both when choosing a material and defining downstream processes. If printed conductors are to ultimately be soldered, it is important to use an ink that can withstand soldering temperatures, as well as one that will wet the solder. Often, the high temperature fluctuations of soldering can dissolve thin, printed conductors, so laser soldering may be considered in order to limit this issue. (Refer to 8.4.1 for more detail). Resistance of polymers to plating chemicals is another consideration, as is moisture adsorption. 4.1.1.7 Vertical Transition Angle Vertical transition angles (print angles) should be considered when selecting a material. Good vertical continuity is dependent on many process and material parameters. Secondary ramps materials may be required to improve the transition. CTEs of these materials should also be considered. In some cases, IPC-2292 Working Draft Master April 2017 Secondary ramps may be formed with squeeze out from the chip bonding material. Ramps made of conductive material can help maintain electrical continuity between layers. When space allows, a larger ramp is preferred to minimize the transition angle of the printed vertical element. Ramps can also be used to prevent unwanted flow of conductive trace material in between the substrate layers. 4.2 Printed Electronics Material Deposition Methods Printable electronics materials or functional inks may be deposited in a variety of methods. Tables 4-1 and 4-2 below identify many of the typical methods used today, and provide a relative comparison of the different methods. It should not be inferred just because a given method is capable of high resolution, speed, low cost, etc. when printing graphic inks that the same will be true when printing functional inks. Materials are formulated for the dispensing method used. 4.2.1 Analog Printed Electronics Material Deposition Methods Electronic or functional materials may be deposited using a variety of analog printing methods. Describing them in detail is beyond the scope/purpose of this document, and more information on these printing methods can be readily found in Handbook of Print Media Technologies and Production Methods or other references. Table 4-1 summarizes analog printing methods known to have been used to print functional inks. As noted above it should not be assumed that strengths of a given printing method relative to other will be maintained when printing functional inks. The most notable difference between graphic inks and functional inks tends to be the rate at which they can be dried and/or cured. Graphic inks only need be dried to a tack free state for stacking sheets or rewinding or can be rapidly UV cured. In contrast the ultimate performance achievable by some functional inks can be a function of the rate at which and how thoroughly they are dried from the wet state. Graphic inks for analog printing methods are usually formulated with more volatile solvents or water (or UV-curable photopolymers) which evaporate must quicker relative to functional inks. Therefore, most printing presses primarily used for graphic purposes have very small dyers/ovens relative to lines used for functional inks. Thus the drying capability of the press greatly limits the rate the press can be run or if a functional ink can even be printed on it. Another major consideration when choosing what printing method to use in producing an electronic device or subcomponent based on printed conductors is the maximum resistance the printed traces can have and the device function property. Typically based off this maximum resistance and the trace lengths and widths a maximum allowable sheet resistance value is determined. Then based on the resistivity achievable by the printed conductor using the manufacturers specifications a target dry film thickness can be determined. From the ink’s volume fraction of solids, a wet film thickness target can then be determined. Then it can be determined which printing methods may be appropriate to use. With many printing methods resolution (minimum line width and spacing) is inversely proportional to applied film thickness, so high resolutions may only be achieved when printing thin. Thus the electrical requirements may exclude using many analog print methods capable of high resolution printing of graphics. Table 4-1 Characteristics of Analog Printing Processes IPC-2292 Working Draft Master April 2017 4.2.2 IPC-2292 Working Draft Master April 2017 Digital Printed Electronics Material Deposition Methods Electronic or functional materials may be deposited using a variety of analog printing methods. Describing them in detail is beyond the scope/purpose of this document, and more information on these printing methods can be readily found in Handbook of Print Media Technologies and Production Methods or other references. Table 4-2 Characteristics of Digital Printing Processes April 2017 Working Draft Master IPC-2292 Digital Printing Methods Ink transfer mechanism Other key mechanisms Pressure Typical ink viscosity Drying mechanism with graphic inks Typical wet film thickness range Drop on Demand Ink Continuous Ink Jet Aerosol Jet Jet pressure impulse pressurized ink, piezo aerosol droplets ejects or jets droplets generates drops focussed travel deflected by charge ballistically 1-10 mPa*s 1-1000 mPa*s solvent evaporation, *** not used for graphic applications < 2.5 µm Ag & Cu PTF & nano, dielectrics, carbon based, more Valve Jet mechanical plunger ejects drops 1-50,000 mPa*s both extensive in PCB assembly, feasbility for PE assembly adhesives Adhesives, Ag pastes, most screen printable materials should be printable resolution limited, ink formulation must be stable to some concentration and solvent add back sheet sheet N/A not used for graphic applications > 3 µm filler particle size, multiple passes required, satellite particles sheet no known usage, feasbility demonstrated low resolution (large particles, multiple passes), single beam per head raster deposition process no known usage, feasbility demonstrated no known usage, feasbility demonstrated most nano inks should no known powders be printable marketed for this single beam per head limited depostion raster deposition rate, single beam per process head raster deposition process Ag nano 1-1000000 mPa*s solvent evaporation *** not used for graphic applications 10-100 µm 1-10 µm (dry film) both filler particle size, tip filler particle size, to substrate gap wetting control, wetting sheet almost any material should be printable with more advanced systems with valves controlling trace width without valve, clogging due to agglomerates in unfiltered inks limited known usage low resolution (larger filler particles, typical spherical) no known inks marketed for this limited known usage flexible & rigid sheets, flexible & rigid sheets flexible & rigid sheets flexible & rigid sheets, flexible & rigid sheets, flexible & rigid sheets, complex 3D surfaces 3D surfaces 3D surfaces complex 3D surfaces flexible sheets & R2R sheet 10-20 mPa*s or powder melting or anchoring powder or particles with heat/pressure, evaporating carrier Electro-hydrodynamic Atmospheric Plasma Microdispensing or Electrostatic or Micro Cold Spray Jet Spray Extrusion Electrophotography pulsed electric field atmospheric plasma high velocity jet of ink forced through a between nozzle & jet (high voltage, high aerosolized (dry) nozzle in near contact charging particles & substrate forms drops frequency) particles with substrate substrate oppositely creating dry aerosol, pneumatic only, auger forming charge image plastic deformation of style, mini-valve for on photoconductive particles to form film precision drum & inking with toner 1- 1000000 mPa*s solvent evaporation *** not used for graphic applications very small drops from aerosol fed into larger nozzle via plasma jet source Taylor cone effect solvent evaporation 15-100 µm solvent evaporation *** not used for graphic applications use of special coatings ink recylced and ink recylced and piezoelectric, on subtrate to prevent solvent added back to solvent added back to electromagnetic bleeding maintain solids maintain solids (solenoid), & pneumatic driven 1-30 mPa*s < 10 µm solvent absorption, solvent evaporation, evaporation, radiation absorption cross linking (uv) < 10 µm both filler particle size, filler particle size, filler particle size, filler particle size, filler particle size, filler particle size, drop volume, wetting, drop volume, wetting, drop volume, wetting, drop volume, wetting drop volume, wetting, drop volume, wetting, satellite drops satellite drops satellite drops spreading of low η spreading of low η inks, satellite drops inks, satellite drops both simples 3D surfaces Minimum line width drivers Press type: sheet, reel to reel, or both flexible sheets & R2R, rigid sheets some usage no known inks marketed for this limited % solids, single beam per head raster deposition process cell phone antennae limited % solids and dry film thickness (DFT) due to ink viscosity, ink formulation no known usage, feasibility demonstrated Substrate types Maximum web width Maximum press speed with graphic inks Commercial use in limited known usage production of electronic devices consumer electronics, Known PE applications OLED displays Ag & Cu nano, Ag Functional materials metalorganics, carbon, or inks available dielectrics, PEDOT, commercially more viscosity limited % solids & dry film thickness (spreading), drying/curing nano ink, substrate coating Challenges to this methods use for printing electronics IPC-2292 Working Draft Master April 2017 Consider resolution (minimum line width and gap width) and registration (placement of multilayers) of printing method. These parameters are highly dependent on the equipment and materials used, and not easily defined in a general sense. Depending on specific design needs, recommended deposition method may vary based on achievable resolution and registration. 4.2.3 Dispense Method Considerations Nozzle Diameter: For direct write and jetted printing, the inner diameter of the nozzle through which the ink is dispensed will impact the minimum achievable linewidth and resolution. Rule of thumb is minimum linewidth is approximately 1.5x nozzle inner diameter. Print Speed: For direct write and jetted printing, the speed at which the nozzle moves relative to the substrate will impact minimum achievable linewidth, pitch, and wet thickness. In general, faster print speeds yield narrower linewidths, but may not yield better linewidth uniformity. Nozzle Pressure: For jetted materials, the nozzle pressure will impact the dimensions and uniformity of the ink delivery, and can be altered along with other parameters to optimize the printing quality and dimensions. Ink Viscosity and Nanoparticle Size: For direct write and jetted printing, the viscosity of the ink, and the average particle size for nanopowder-loaded inks, will dictate the smallest nozzle diameter that can be used (and will also drive the desired nozzle pressure for jetted materials). Because of this, higher viscosities will in general yield larger minimum linewidths, and higher minimum wet thicknesses. However, highly wettable substrates may result in larger linewidths due to more spreading of low viscosity inks. Substrate Wettability: Substrate wettability is a function of the surface energy of the substrate and chemical composition of the ink. A highly wettable substrate indicates increased spreading of ink upon deposition. Wettability can be altered via plasma and chemical cleaning processes, as well as mechanical processes that alter the surface roughness. Substrate Roughness: The substrate surface roughness will impact the ink spread and minimum achievable linewidth for all printing processes. Standoff: Standoff is the distance between the nozzle and substrate in direct write and jetted materials. This will impact the minimum achievable linewidth, as well as the maximum step height (surface topography) that is achievable on a substrate. It will also dictate the maximum off-axis angle of printing, along with the nozzle and printer head dimensions. 4.2.4 Contact Resistance Electrical contact resistance refers to the measure of opposition that the current in a connection sees when flowing from one conductive surface connected to another. This opposition, or resistance at the contacting interface, is said to be responsible for contributing additional resistance to the total series path resistance from conductor to conductor in any given circuit. In the context of printed electronics, it is often desirable to minimize this increase in contact resistance by means of controlling the contributing factors that produce it. When a junction is formed by printing or layering overlapping similar or dissimilar metallic inks, the compatibility of the primary metal particles that will form the junction and supporting additives should be addressed. If it is not addressed, galvanic corrosion in the presence of an electrolyte will have adverse effects on conductive surfaces and contact resistance. Contributing factors to consider when trying to control contact resistance include: Thermophysical and mechanical properties of materials in contact Intrinsic electrical properties Characteristics of the contacting surfaces IPC-2292 Working Draft Master April 2017 Presence of gaseous or nongaseous media between the contacting surfaces Apparent contact pressure or stress Mean junction temperature and environment 4.2.5 Thermal Contact Resistance 04-07-2017 – Furman Thompson proposes a new section for this. 4.2.6 Compatibility of Inks to Inks With polymer thick film inks, the primary consideration is whether some solvent of a subsequent ink layer swells or dissolves a previous layer. For inks that function through charge transfer, the ionic nature of secondary inks could poison the second ink (i.e., when using electrochromic inks). Additional considerations include galvanic mismatch between metallic inks, wetting of inks, cure temperatures and coefficient of thermal expansion (CTE) differences between the inks. 4.2.7 Compatibility of Inks to Substrates The primary method to boost adhesion of functional inks to substrates (especially PET films) is through the application of thin coatings to the surface called in-line adhesion pretreatments or primers. In addition to this but less common for printed electronics, corona or plasma treatments and etches can be used to prime the surface for wettability of the ink. Refer to the surface treatments content in IPC-4921 for more information. 4.2.8 Ink Properties Initial properties of inks that will impact compatibility for an application include the solvent type, shrinkage, cure profile, viscosity, and dispense method. Final properties to consider are conductivity, dielectric properties, elongation/ductility, flexibility, stretch. Additionally, considerations for nanoparticle loaded inks include – percent loading, particle size, particle shape, solvent and dispersant, cure temperature and time, shelf life, diluting, stability of suspension/mixing, etc. 4.3 Dielectric Materials In the section below dielectric is used to refer to insulator materials with varying degrees of electrical susceptibility to polarization. This includes insulator materials with no susceptibility. 4.3.1 Dielectric Filaments These filaments are typically dispensed through a heated extruder, melted and solidify in place. They can to some degree be self-supporting. Full density is not always achieved and anisotropic properties are typically seen. 4.3.2 Dielectric inks materials These materials can be dispensed or sprayed and usually require post processing to cure (sinter, heat, UV). Cure steps need to be considered prior to next layer applications. 4.4 Adhesives 4.4.1 Adhesives (Liquid) Adhesives such as flexible epoxy, acrylic, RTV silicone or polysulfide can be used to provide strain relief in areas of high flexural stress or areas prone to fatigue cycling. These materials may be a potential outgassing issue for specific applications. IPC-2292 Working Draft Master April 2017 4.4.2 Flexible Adhesive Bonding Films (Dry Film Adhesive) Flexible adhesive bonding films are typically used in bonding multiple flexible layers and attachments used for thermal management or structural support. These materials offer high bond strength to the flexible dielectric. These bonding films may be formulated from low Tg resins to enhance adhesion and flexibility. In rigid-flex designs, these materials should be minimized or removed from the rigid sections to eliminate the problem of excessive Z-axis expansion. Reference IPC-FC-234 (use new spec) for more information on pressure-sensitive adhesives. 4.4.3 Pressure-Sensitive Adhesives (PSAs) Pressure-sensitive adhesives (PSAs) create their bond by relying on initial pressure and flow. This is unlike other adhesives, which rely on a chemical reaction or curing process. PSAs such as those commonly found on everyday tapes and stickers, are already cured, stay viscoelastic and have permanent tack throughout their lifetime. They can be laminated to substrates at different times and can be cut into specific design patterns to provide planar and multidimensional bonding. PSA inks are available in several forms: solvent, water or UV-cure-based chemistry. These can be selectively applied direct to the printed electronic and then laminated to the final structure or to a release liner for later lamination. Application methods include screen print, needle dispense, slot die, etc. Curing or drying methods include heat, UV or light-emitting diode (LED) curing. Selective application of PSA eliminates the need for die-cutting PSA tapes or spacers and their associated waste. PSAs allows for easy substrate-to-substrate, substrate-to-flex and substrate-to-surface bonds to be made. When choosing a PSA, it is important to consider substrates and their properties. Generally, softer adhesives translate into the following: Lower viscosity Faster flow Faster bond build rate High peel adhesion strength Increased flow into porous substrates This behavior allows for more mechanical interlock, better adhesion to low-surface-energy substrates and reduced high-temperature performance. Firmer adhesives usually retain: Better cohesive strength Stronger shear strength Increased solvent resistance Superior high-temperature performance Less adhesive ooze and easier cutting Slower to build ultimate bond strength At a minimum, the designer should consider substrates, application, environment and overall design when choosing the optimal PSA for the design. 4.5 Conductive Materials Conductive materials shall be in accordance with IPC-2221 and as stated in 4.4.1 through 4.4.7. IPC-2292 Working Draft Master April 2017 4.5.1 Conductive Inks Functioning by Percolation These print able conductor materials contain conductive filler particles dispersed in a vehicle consisting of solvents, soluble/solvated thermoplastic polymers, dispersing and wetting agents, and other performance modifying chemicals or materials. By nature, they must contain high enough loadings of conductive filler particles such that upon drying and/or curing the microstructure of the resulting films is a percolated network of the particles in close enough contact to allow current to pass through the volume. The most common class of these are screen printable versions called polymer thick film inks which usually contain mixtures of silver particles and/or ‘flakes’. Versions with conductive particles based on base metals, base metals coated with silver, carbon, graphene, and other materials also exist. For the purposes of printing electronics on flexible substrates a class of print able conductors know as fired or ceramic thick film inks is not applicable because they require cure temperatures exceeding the thermal stability of most polymeric and even metallic flex substrates. 4.5.2 Conductive Inks Functioning by Sintering These print able conductors differ from percolation conductors in that after drying and curing the resulting films have a microstructure of sintered metallic particles or metallic crystals that have formed via metalorganic decomposition. Typically, with proper formulation and curing these conductors achieve significantly lower volume resistivity than percolation conductors approaching that of bulk metal structures at lower film thicknesses. At higher film thicknesses more porosity can result during curing and resistivity deviate further from the bulk metal resistivity; still achieving values significantly better than percolation conductors. Typically to maintain the ability to sinter less polymer is used in these inks and as a result adhesion on nonprimered film substrates will typically be inferior to polymer thick film inks. Therefore, proper selection of substrate grade and specifically primer type should be a consideration. Examples of this class include silver and copper nanoparticle inks, hybrid nanoparticle/microparticle silver copper inks, metalorganic (metal atoms bonded via heterotom versus carbon in organometallics) inks, metalorganic and particle hybrid inks, amine complexes of metalorganics, etc. IPC-2292 Working Draft Master April 2017 Figure 4-3 NEED CAPTION 4.5.3 Conductive Filaments (wires, coated wires, or conductive filaments,) Conductive filaments are typically dispensed through a heated extruder, melted and solidify in place. They can to some degree be self-supporting. Full density is not always achieved and anisotropic properties are typically seen. Wires can be used when high conductivity is required but require additional considerations to be effectively implemented including wire routing, clearance channel creation, wire termination and interconnect. 4.5.4 Conductive Films/Foils/Grids Large conductive areas can be created through placing films, foils, or grids onto the substrate or onto or within the printed assembly instead of depositing and curing inks. Thermal transfer printing systems may be used to digitally print patterns of thin foils from a carrier ribbon. Processes using printing based equipment and methods exist for subtractive cutting or grinding away selective areas of metal/foil substrate laminates using dry processes. It is also possible to print resists onto foils and etch away areas as traditional PCBs and flexible PCBs are made. In some cases, it may be desirable to use these traditional approaches for some layers and printing other conductor layers. 4.5.5 Printed Conductive Seed Layers for Plating or “Print and Plate” Additive and semi-additive methods for producing conductive interconnects involving the printing of ‘seed’ layers and electro less or lytic plating up thickness exist. For electroless plating the seed layers do not need to be conductive only catalytic to allow for the plating reactions to proceed. For electrolytic plating ‘buss’ lines to the desired conductor patterns must be created to allow current to pass from the anode to them. Also the seed structures must have adequately low sheet resistance to result in uniform current distribution and plating of features further from the buss lines. Typically these buss structures must be cut or otherwise removed from the desired structures to singulate them. 03-21-2017 – Staff note – Need to ensure figure references are correct. 4.5.6 Conductive Interfaces and Out-of-Plane Interconnects Interconnects can be created through direct printing of conductive materials onto other conductive materials with or without dielectric apertures (see Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7). Interconnects through the substrate are typically constructed by conductively filling vias between the sides of the substrate (see Figure 4-7 and Figure 4-8). CTE between printed layers, the substrate and the conductive interface material should be considered. Z-Axis expansion as well as in plane expansion differentials may result in conductive material separation. CTE can also break conductive material connections that are printed between perpendicular surfaces. Ramps may be constructed to create more gradual transitions. The aspect ratio for printed or dispensed materials should be considered. Material has limitations for how far in depth it can be printed or dispensed based on viscosity, force of dispense, and the narrowness of the hole in the substrate or the aperture in the dielectric material (See Figure 4-1). Material shrinkage can typically occur during cure. As dispensed dimensions may vary from as cured dimensions. This should be considered when selecting materials and designing apertures. In order to achieve interconnects through via holes it is a good practice to dispense excess material beyond the conductive layer on both sides of the substrate to ensure good electrical connection. Allowances for this excess material should be considered. IPC-2292 Working Draft Master April 2017 Figure 4-8 Every Interconnect Method at Once 4.5.7 Isotropic Conductive Adhesives These materials conduct through percolation similar to conductive inks, but typically instead of containing thermoplastic polymers they contain thermoset epoxies which provide greater bond strength. Also, they may contain a higher ratio of polymer to conductive filler particles to result in better adhesion and mechanical properties. As a result, they tend to have significantly higher resistivity than conductive inks. 4.5.8 Anisotropic Conductive Adhesives These materials are designed to be deposited between the pads of a SMT component and conductive interconnect, and then thermally cured with some pressure being applied to the structure. The desired property of these materials is conduction only across the thickness of the film between the bond pads and not laterally which could create a short. Unlike isotropic conductive adhesives these materials contain significantly lower loadings of conductive filler particles to stay well below the percolation threshold and maintain electrical isolation of laterally adjacent traces. 4.5.9 Post-Plating Operations If the printed electronic will be subject to post-plating operations, the designer should use caution in selecting printed electronics materials. Not all printed electronics materials or base substrates are capable of surviving the temperatures required for post-plating operations. See Table 4-1 for material selection. 4.6 Coatings 4.6.1 Carbon for Printed Silver Coating inks are often printed over exposed silver traces for products to be used under environmental and electrical conditions where electromigration is a risk. By proper use of carbon electromigration of silver from printed conductors can be prevented. IPC-2292 Working Draft Master April 2017 4.6.2 Conductive Coatings for Shielding Conductive inks such as silver, copper, or carbon-filled polymers can be applied to the surfaces of dielectric layers to provide shielding. These coatings should be specified on the master drawing. Connection to ground can be made by direct attachment through an opening in the dielectric. 4.6.3 Organic Protective Coatings Organic protective coatings should be in accordance with IPC-2221 4.6.4 Conformal Coating, Spray coats Conformal coatings should generally be omitted from flexible areas to avoid stiffening of the flex structure and flaking or de-bonding of the conformal coating from the flex substrate/surface. Include in barrier coat 4.7 Other Cover Materials Cover material is a generic term applied to thin dielectrics that are used to encapsulate circuitry, most commonly for flexible circuit applications. There are three types of cover materials, including coverlay, coverfilm and covercoat. 4.7.1 Coverlay The coverlay is a combination of applied film and integral adhesive made from separate layers of generically different chemistries that subsequently becomes a permanent dielectric coating. The coverlay is used to insulate/isolate the conductor layers on the outer surface of the flexible SPD. The coverlay is constructed of materials that can be flexed or formed in the intended use. The coverlay has access holes/windows to expose conductive surfaces and mounting holes. See IPC-4202, IPC-4203 and IPC-4204 for additional guidance. 4.7.2 Coverfilm The coverfilm is an applied film that subsequently becomes a permanent dielectric coating and is made from: Separate layers of generically similar chemistries, Homogeneous, single component, or Composite blend of two or more components. 4.7.3 Covercoat The covercoat is a liquid or semi-liquid coating that can be applied by a variety of methods including screening, spraying, dispensing, or dipping/curtain coating and subsequently becomes a permanent dielectric coating. 4.8 Other Printed Materials Additional special considerations may be required for printed materials with unique characteristics or functionality. For instance, reactive materials, ferroelectrics and liquid metals may demonstrate variable electrical, thermal, mechanical, optical and/or magnetic properties. Conjugated polymers can be semiconductive or conductive, and have electroluminescent properties. Functionalized materials (chemical sensors) and emissive materials can have colorimetric, fluorescent or other unique behaviors. IPC-2292 Working Draft Master April 2017 Printed devices, such as metamaterial structures, photovoltaic devices and MOSFETs will have unique characteristics that must be accounted for by the designer. 4.9 Placed Components Caution should be taken with placing components in flexible areas, unless specifically designed to meet requirements under the maximum flex specified in design. 4.10 Marking and Legend If marking is needed on the printed electronic, it shall be defined on the procurement documentation or master drawing. IPC-2292 Working Draft Master April 2017 5 MECHANICAL AND PHYSICAL PROPERTIES 5.1 Fabrication Requirements 5.1.1 Printed Flex Fabrication – Sheet Form The manufacturer should be consulted on the sheet sizes available and useable area on the sheet. Consideration should be given to the following: Part spacing and nesting (nonrectangular parts – see Figure 5-1). Coupons (Final, In-process, Impedance, Thermal Cycling (e.g., Interconnect Stress Test (IST)), etc.) Tooling holes Fiducials Palletization frame (step-and-repeat nesting on sheet preparation for hybrid scenarios) Printing edge clearance Sheet utilization considerations become more important as production quantities increase and cost per printed sheet becomes a driver compared to the overall set-up cost of low-quantity/prototype work. 5.1.2 Printed Flex Roll to Roll Fabrication The manufacturer should be consulted on web width and roll length, as the variations are determined by equipment and material thickness used in the application. 5.2 Product/Printed Flex Configuration Note: Nesting (non-rectangular shapes) should be considered as a more efficient utilization technique (see Figure 5-1). 5.2.1 Circuit Profile (Outline) The exterior outline of the proposed circuit should not waste raw material. If the circuit has peninsulas or fingers extending in many directions, material costs may be higher than necessary. Folds in the circuit may permit extensions to be manufactured near the main body of the circuit and provide a more compact, rectangular circuit outline for processing. Circuit profiles can be obtained using steel-rule dies, laser trim, routing or hard tooling. IPC-2292 Working Draft Master April 2017 Figure 5-1 Circuits Nested on a Panel Sheet 5.2.1.1 Relief Radii to Avoid Tearing The designer should consider mechanical properties of the substrate or base materials for applications which will have relief radii of the inside corners, to avoid tearing of the substrate or base materials. Larger radii will make a more reliable part and be more resistant to tearing (see Figure 5-2). To avoid tearing use radii or relief holes in areas that will be subjected to bending such as a I/O flex tail on a printed electronic substrate (see figure 5-2). Actual diameter is not critical but the smaller the diameter the more susceptible to tearing. This will also depend on substrate material and thickness. Figure 5-2 Avoid Tear With Relief Radii Additional material such as a thin laminate may be added before final cut to provide increased tear resistance (see Figure 5-3). Figure 5-3 Thin Material Added for Increased Tear Resistance IPC-2292 Working Draft Master April 2017 5.2.1.2 Hole to Edge Distance The minimum distance between exterior edges and the edge of interior holes and cutouts should be designed such that the final residual material is no less than 6 mm [0.25 in] from the exterior edges. Feature location, size tolerance and outline tooling tolerances should be considered for the designed distance. 5.2.1.3 Strain Relief Slits and slots should terminate in a 1 mm [0.0394 in] diameter or larger hole, as shown in Figure 5-2. This situation arises when adjacent portions of the printed flex must move separately. 5.2.3 Flexible Areas 5.2.3.1 Flex, Bend and Crease Area Considerations Factors to consider in determining the total number of printed layers required (along with other interrelated considerations) are: Quantity of printed layers in the bend or crease area(s) Thickness of both printed layers and layers used for lamination in the bend or crease area(s) Quantity of laminated layers in the bend or crease area(s) Quantity of nonlaminated layers in the bend or crease area(s) Line widths required for current-carrying capacity Spacing required for voltage isolation EMI shielding Impedance Voltage drop requirements Mechanically defined ‘‘real-estate’’ for routing the conductors (i.e., the width of the flexible portions) Conductors in crease area(s) o Repeated creases (i.e., during machine wash cycles, handling or use of finished product) can damage conductors. Bend radius Location of conductive vias relative to bend or crease area(s) SMT lands or components in the bend or crease area(s) 5.2.3.2 Bend Area Conductor Considerations The flexible printed flex should not be flexed or formed in an area where there is discontinuity in the dielectric, termination of dielectric, or any other stress-concentrating feature. The acceptability of this condition is determined by the thickness of materials, the radius of the bend, and the severity of the operating environment. A dynamic installation is more susceptible to conductor failure than a static environment but should always avoid a crease, if possible, in conductor area. Bends in conductor area are acceptable as long as bend radius is no less than 5X the thickness of substrate. For maximum dynamic and static flex life conductors in the bend area (see Figure 5-7) should adhere to the following considerations: Perpendicular to the bend IPC-2292 Working Draft Master April 2017 Evenly spaced across the bend area Maximized across the bend area Without dielectric or conductor breaks or abrupt end in the bend area Areas of flex should be properly coated or laminated to provide strain relief in the bend area Uniform in width The neutral axis, where possible, should be located at the center of the conductor in the construction of the laminate (see Figure 5-8 and Figure 5-9) Conductors in double-sided circuits should not be placed directly over each other, which produces an ‘‘I’’ beam effect. This condition may be necessary due to electrical considerations; however, mechanical installation requirements shall be considered (see Figure 5-8) The number of layers in a bend area should be kept to a minimum Conductive Vias in bend areas should be avoided Laminated polyester or other dielectric flex layers over printing can improve the lifetime of the component through repeated flexing. Figure 5-7 Conductors in Bend Areas Note to IPC designer: This is IPC-2223-5-8 Figure legend Note 1: Bend area. Note 2: Dynamic - preferred. Static – preferred. Note 3: Dynamic – not preferred. Static – acceptable. Note 4: Dynamic – non-conforming. Static – not preferred. A balanced construction can be achieved by using materials of equivalent modulus values and thickness on each side of the conductor. This is critical in dynamic flexible printed applications. Several design techniques are popular for approximating this condition, such as using laminated polyester flex layers coverlays and interdigitizing conductors front to back (see Figure 5-8 and Figure 5-9). 5.2.3.3 Calculation of Bend Radius The bend radii should be kept as large as possible. The minimum bend radius should be 10 times the overall thickness of the completed flexible circuitry. It is preferable that a flexible printed electronic be allowed to follow its own natural bend. Bends greater than 90° and containing a small radius should be avoided. IPC-2292 Working Draft Master April 2017 Figure 5-9 Neutral Axis Ideal Construction Note to IPC designer: This is IPC-2223-5-10 Key 1: Printed conductor under tension 2: Printed conductor under compression. 3: Neutral axis of substrate. 5.2.4 Forming Heat or cold formed bends or shapes are possible depending on the substrate’s properties. Forming can be used to add mechanical function (example tactile emboss) or aid in the assembly of a printed flex into a chassis. The bend does not need to hold its shape perfectly like sheet metal, rather it just needs to cause the flex to bend in a predetermined location during assembly. It is good design practice to minimize the amount of preform bending due to the memory characteristics of flex substrates. The formability and reliability of a circuit is dependent upon the thickness and ductility of the printed inks and laminates, as well as the substrate material and adhesive system. Three methods of permanently forming circuits are employed: cold forming, thermal forming, and forming through reliance on the properties and thicknesses of the printed conductors, dielectrics, laminates, adhesives and substrate. Thermal forming is generally only used with substrate/adhesive combinations from the same materials family (i.e., polyester, etc.). Preforming requires expensive manufacturing, tooling, and shipping containers. When preforming is required, it should be performed just prior to installation in the final unit. The addition of a strain-relief bar or some other means of support shall be provided if bending occurs close to an epoxy joint, printed via. Bend and/or crease line drawing requirements are as follows: Bend/crease lines should be shown on fabrication and assembly drawings. Bend/crease line dimensions shall be depicted as a reference. The assembly drawing should show the finished folded con- figuration as a reference only. Bend/crease lines should be depicted as center lines and described as ‘” bend line corresponds to center of arc formed when folded.” Preformed flexes may not stay at formed dimensions, even at room temperature. Elevated temperatures will hasten the process. This should be considered when forming flex to avoid objects. After relaxing, the flex may interfere with those objects. Any dimension on formed flexible features should be noted as a ‘‘reference’’ dimension, or very loosely toleranced. Any measurements should be taken in a restrained condition. IPC-2292 Working Draft Master April 2017 5.2.4.1 Bends or Folds (Greater than 90°) Folds should be kept uniform and designed to follow the surfaces of the pack- age. These types of folds are only recommended for single- sided flexes or double-sided flexes where there is no I-beaming of printed conductors in the fold area. Single- sided printed flex can be made to appear double- sided by folding the circuit. A forming tool with a known radius may be employed to control the bend radius and prevent conductor cracking. Resistance testing should be done to validate the process and verify that there is no cracking of the printed conductors. The folded portion of the circuit may be secured with an adhesive. A crease should be avoided, but if required, shall be formed only one time, it shall not be opened again, and it should be bonded in place to ensure that the fold will not be exercised. Keep in mind the bend allowances required in tight corners. Regular folds should not be allowed to ‘‘bind’’ against parts since such binding areas can be points of weakness under vibration (see Figure 5-10). A bend or fold greater than 90° is defined as one that results in an acute angle measured between two adjacent sections across the bend or fold. See 9.3.5 for details on land access openings. Figure 5-10 Irregular Folds Note to IPC designer: This is IPC-2223-5-12 Figure legend Note 1. Stress on solder joint. Note 2. Flexible circuit rubbing structure or adjacent component. Note 3: Acceptable. Note 4: Nonconforming. 5.2.5 Bend Radius One important factor that is vital to the success and longevity of a flexible printed electronic is the maximum bend radius that can be attained based on the dimensions of the materials used. The key dimension the designer must consider when determining bend radius is the overall measured thickness of the flexible printed electronic. This measurement consists of the thicknesses of: IPC-2292 Working Draft Master April 2017 Substrates (including laminated substrate layers) Adhesives Graphic layers (e.g., inks) Any other materials used in the full construction The designer must carefully consider the effects of these materials on the printed electrical traces, to ensure the completed printed electronic is completely functional and robust in its operation. A bend radius less than recommended minimum can lead to failure of the printed electronic and/or performance not meeting expectations. A useful guideline to estimate the bend radius of a flexible printed electronic is a radius that is six times the measured thickness of the completed flexible printed electronic component. This will ensure printed electrical traces will not undergo cracking or fracture due to impingement from the multiple layers used. It will also ensure the flexible printed electronic will not buckle or undergo deformation due to the layers’ inability to flex under a radius that is too minimal. Buckling or deformation can cause localized delamination due to excessive forces exerted on the circuit during bending. The designer should use this same bend radius design guideline for single-sided flexible printed electronics, which use only one substrate layer.6 ELECTRICAL PROPERTIES 6.1 Electrical Considerations 6.1.1 Electrical Performance When printed electronic assemblies are to be conformal coated, they shall be constructed, adequately masked or otherwise protected in such a manner that application of the conformal coating does not degrade the electrical performance of the assembly. High-speed printed electronics designs should consider the recommendations of IPC-2251. 6.1.2 Power Distribution Considerations A predominately important factor that should be considered in the design of a printed electronic is the power distribution system. A grounding scheme can be used as a part of the distribution system. It provides not only a DC power return, but also an AC reference for switched signals. The following items should be taken into consideration: Maintain low radio-frequency (RF) impedance throughout the DC power distribution system. An improperly designed power/ground scheme can result in RF emissions even if the circuit is not designed for RF operation. The use of planes for power/ground distribution is preferred. See 4.5.4 for specific implementation schemes. When planes are not used, route switching signal conductors adjacent to power or ground conductors to minimize the AC return path. The use of decoupling capacitors may reduce the RF emissions. Decouple the power distribution at the printed electronic connector using adequate decoupling capacitance. Evenly distribute individual power/ground decoupling capacitors throughout logic device printed electronic circuit areas. Minimize the impedance and radiation loop of the coupling capacitor by keeping capacitor leads as short as possible and locating them adjacent to critical circuits. Power conductors should be run as close as possible to ground conductors if planes are not used. Both power and ground conductors shall be maintained as wide as possible. See figure 6-1 for IPC-2292 Working Draft Master April 2017 recommendations. The power and ground conductors virtually become one conductor at high frequencies and should, therefore, be kept next to each other for maximum decoupling. Figure 6-1 Voltage/Ground Distribution Concepts In digital power distribution schemes, the ground and power distribution should be designed first, not last, as is typically done with some analog circuits. All interfacing, including power, should be routed to a single reference edge, or area. At the interconnection reference edge, all ground structures should be made as heavy as possible. 6.1.3 Circuit Type Considerations The following guidelines should be considered when designing printed electronics: Always determine correct polarity of the component, where applicable. IPC-2292 Working Draft Master April 2017 Transistor emitter/base and collector should be properly identified (ground transistor case where applicable). Keep lead length as short as possible and determine capacitive coupling problems between certain components. If different grounds are used, keep grounding busses as far apart from each other as possible As opposed to digital signals, analog design should have signal conductors considered first and ground conductor connections considered last. Keep heat-sensitive and heat-radiating components as far apart as possible (incorporate heat sinks whenever necessary). Staff note – 03-21-2017 – What is state information? Is this some sort of status of the circuit’s performance, or is this a typo? 6.1.3.1 Digital Circuits Integrated circuit devices use a variety of logic families. Each family has its own parameters regarding the speed of the digital transmission, as well as the temperature rise characteristics necessary to provide the performance. In general, a single printed electronic design usually uses the same logic family to facilitate a single set of design rules for conductor length for signal-driving restrictions. Some of the more common logic families are: Transistor-transistor logic (TTL) Metal oxide semiconductor (MOS) logic Complementary metal oxide semiconductor (CMOS) logic Emitter coupled logic (ECL) Gallium arsenide (GaAs) logic In certain high-speed applications, specific conductor routing rules may apply. A typical example is serial routing between signal source, loads and terminators. Rating branches (stubs) may also have specified criteria. Digital signals can be roughly placed into four classes of criticality. These classes are: 1) Noncritical signals – Those which are not sensitive to coupling between them. Examples are between lines of a data bus or between lines of an address bus where they are sampled long after they are settled. 2) Semicritical signals – Those where coupling is kept low enough to avoid false triggering (e.g., reset lines and level triggering strobe lines). 3) Critical signals – Those with waveforms that are required to be monotonic through the voltage thresholds of the receiving device. These are normally clocking signals. Any glitch while the wave form is in transition may cause a double-clocking of the circuit. A noncritical signal has a waveform that need not be monotonous and may even make multiple transitions between the voltage thresholds before it settles. It needs to settle before the receiving device acts upon the data (i.e., the data input to a flip-flop may be a noncritical signal, but the clock signal is most probably a critical signal). Asynchronous signals, although they may (or may not) be noncritical signals, should not be mixed with critical signals because there is a real possibility of the asynchronous signals inducing noise on the critical signals during the clock transitions. Clock signals that do not have a common master frequency should also not be routed together for IPC-2292 Working Draft Master April 2017 similar reasons. 4) Super-Critical signals – Those in applications such as clocks or strobes for A/D and D/A converters, signals in phase-locked loops, etc. In these types of applications, phase lock jitters and crosstalk, which cause errors, noise and timing jitters, will show up in the application’s output performance. It is only a question of the amount of disturbance within the required performance specification. This class of signal is essentially the same as an analog-coupling situation. To explain another way, it is completely linear (the total noise is the sum of the individual noise elements; no averaging or canceling out can be assumed). 6.1.3.2 Analog Circuits Analog circuits are usually made from integrated circuits and discrete devices. Standard discrete components (e.g., resistors, capacitors, diodes, transistors, etc.), power transformers, relays, coils and chokes are usually the types of discrete devices used for analog circuits. 6.2 Conductive Material Requirements The minimum width and thickness of conductors on the finished printed electronic shall be defined on the master drawing. The minimum width and thickness should be determined primarily based on the current-carrying capacity required and the maximum permissible conductor temperature rise. The designer should pay attention to the resistivity of conductive ink materials and the impact on circuit performance. Minimize conductor lengths or maximize conductor widths as needed to minimize total conductor resistance. The designer may also increase conductor thickness to minimize total conductor resistance where materials and process techniques allow. Consult material data sheets and printed electronic manufactures where heat rise considerations are necessary. 03-21-2017 – Staff note – I imported the table from IPC-2221. Can we revise it to be specific to IPC-2292, or should we just reference the IPC-2221 table? 6.3 Electrical Clearance Minimum spacing between conductors, conductive patterns and conductive materials (e.g., conductive markings or mounting hardware) shall be defined on the master drawing. The maximum voltage between adjacent conductors shall be considered when determining the minimum conductor spacing. See Table 6-1 for general guidelines. The designer should use caution when applying data from Table 61, because the data are based on a different material set. Use of conformal coatings should be considered where the potential for arching exists. Table 6-1 Electrical Conductor Spacing Voltage Between Conductors (DC or AC Peaks) 0-15 16-30 Minimum Spacing Bare Printed Board B1 1 Assembly B2 B3 B4 A5 A6 A7 0.05 mm [0.002 in] 0.1 mm [0.004 in] 0.1 mm [0.004 in] 0.05 mm [0.002 in] 0.13 mm [0.00512 in] 0.13 mm [0.00512 in] 0.13 mm [0.00512 in] 0.05 mm [0.002 in] 0.1 mm [0.004 in] 0.1 mm [0.004 in] 0.05 mm [0.002 in] 0.13 mm [0.00512 in] 0.25 mm [0.00984 in] 0.13 mm [0.00512 in] IPC-2292 Working Draft Master April 2017 31-50 0.1 mm [0.004 in] 0.64 mm [0.025 in] 0.64 mm [0.025 in] 0.13 mm [0.00512 in] 0.13 mm [0.00512 in] 0.4 mm [0.016 in] 0.13 mm [0.00512 in] 51-100 0.1 mm [0.004 in] 0.64 mm [0.025 in] 1.5 mm [0.0591 in] 0.13 mm [0.00512 in] 0.13 mm [0.00512 in] 0.5 mm [0.020 in] 0.13 mm [0.00512 in] 101-150 0.2 mm [0.0079 in] 0.64 mm [0.025 in] 3.2 mm [0.126 in] 0.4 mm [0.016 in] 0.4 mm [0.016 in] 0.8 mm [0.031 in] 0.4 mm [0.016 in] 151-170 0.2 mm [0.0079 in] 1.25 mm [0.0492 in] 3.2 mm [0.126 in] 0.4 mm [0.016 in] 0.4 mm [0.016 in] 0.8 mm [0.031 in] 0.4 mm [0.016 in] 171-250 0.2 mm [0.0079 in] 1.25 mm [0.0492 in] 6.4 mm [0.252 in] 0.4 mm [0.016 in] 0.4 mm [0.016 in] 0.8 mm [0.031 in] 0.4 mm [0.016 in] 251-300 0.2 mm [0.0079 in] 1.25 mm [0.0492 in] 12.5 mm [0.4921 in] 0.4 mm [0.016 in] 0.4 mm [0.016 in] 0.8 mm [0.031 in] 0.8 mm [0.031 in] 301-500 0.25 mm [0.00984 in] 2.5 mm [0.0984 in] 12.5 mm [0.4921 in] 0.8 mm [0.031 in] 0.8 mm [0.031 in] 1.5 mm [0.0591 in] 0.8 mm [0.031 in] 0.0025 mm/ volt 0.005 mm/ volt 0.025 mm/ volt 0.00305 mm/ volt 0.00305 mm/ volt 0.00305 mm/ volt 0.00305 mm/ volt 500 See para. 6.3 For calc. Minimum layer-to-layer conductive thickness (Z-axis) shall be defined on the master drawing. The designer should refer to substrate and dielectric material data sheets for electrical isolation and thickness specifications. When dielectric inks are used as insulators, the manufacturing method should be considered relative to the minimum thickness required for electrical isolation. Consult the manufacturer for actual thickness data based on processing characteristics. 03-21-2017 – Staff note – Is the highlighted sentence necessary? Do we need to make reference to PWB design in a PE design standard? 6.4 Impedance Controls Impedance requirements including nominal impedance and tolerances values shall be specified on the master drawing. The control of printed electronic conductor impedance will pose challenges to the designer of printed electronics. The designer should pay attention to conductor losses and geometry when designing for impedance control. The designer should also minimize conductor length between devices to the greatest extent possible. The designer should use caution when employing commercial impedance prediction software or calculators. The designer should be cognizant of the assumptions internal to the software tool. Printed electronic material parameters and geometries will be different than those used for standard PWBs. 6.5 Formed Components The formed component type shall be specified on the master drawing with specific parameters as described in 6.5.1 through 6.5.4: 6.5.1 Formed Resistors The following parameters shall be defined on the master drawing for each resistor as necessary: Nominal resistance Tolerance Power dissipation Resistor ink resistivity Geometry (width/length or number of squares) IPC-2292 Working Draft Master April 2017 6.5.2 Formed Capacitors The following parameters shall be defined on the master drawing: Nominal capacitance Tolerance Maximum voltage Geometry (including number of layers) Dielectric properties and thickness 6.5.3 Formed Inductors The following parameters shall be defined on the master drawing: Nominal inductance Tolerance Geometry 6.5.4 Formed Active Components The specific type and geometry of active components (including materials and layer structure) shall be defined on the master drawing. IPC-2292 Working Draft Master April 2017 7 THERMAL MANAGEMENT This section is intended as an outline for temperature control and heat dissipation. This section, coupled with appropriate thermal analysis can result in greatly reduced thermal stresses and improved reliability of the printed electronics. The primary objective of thermal management is to ensure that all printed circuit components, especially the integrated circuits, are maintained within both their functional and maximum allowable limits. There are steady state and transient problems that occur in thermal management. For steady state1 consideration, thermal management depends on knowing all of the energy sources that are input to the printed electronics package, as well as all of the heat transfer paths out of the package. For transient2 considerations, all of the steady state considerations are required, as well as knowing the events where energy input or power changes with time. The thermal capacitance of the printed electronics package is also taken into consideration for time dependent changes. For the printed circuit, the calculation of the energy into the system is determined by calculating the power dissipated in the conductor. The printed conductor material resistivity, the cross-sectional area of the printed conductor, and the conductor length must be known to calculate the conductor resistance. The temperature coefficient of resistance of the printed conductor material must be known, so that resistance at the operating temperature of the printed conductor application can be determined, see IPC-TM-650 2.5.4.1a3 for assistance. Using the known resistance at the maximum operating condition will allow the calculation of the conductor power dissipation. The conductor power dissipation is one of the inputs for the thermal analysis of the printed electronics. The cooling technique to be used in the printed electronic application should be known in order to ensure the proper printed electronic design. For commercial applications, direct-air cooling (i.e., where cooling air contacts the printed electronic) may be used. For rugged and hostile environmental usage, indirect cooling is most often used to cool the printed electronic. In this application, the printed electronic is mounted to a structure, that is air or liquid cooled. These designs should use appropriate metal heatsinks on the printed electronic. Appropriate bonding may be required. To ensure adequate design, thermal dissipation maps should be provided to aid analysis and thermal design of the printed electronic. When power densities of a few watts/square inch are confined in the printed electronic, properly defining hot spots, thermal paths and cooling techniques are essential. A combination of natural and active cooling methods may be necessary to maintain a proper steady state operating temperature. Footnotes: 1. Steady state refers to the electronics being in an active state with no time changing events 2. Transient refers to time dependent energy input, such as high current pulses. 3. IPC-TM-650 2.5.4.1a, Conductor Temperature Rise Due to Current Changes in Conductors 7.1 Cooling Mechanisms The dissipation of the heat generated within printed electronic equipment results from the interaction of the three basic modes of heat transfer: conduction, radiation and convection. These heat transfer modes can, and often do, act simultaneously. Thus, any thermal management approach should attempt to maximize their natural interaction. 7.1.1 Conduction The first mode of heat transfer to be encountered is conduction. Conduction takes place to a varying degree through all materials. The conduction of heat through a material is directly proportional to the thermal conductivity constant (K) of the material, the cross sectional area of the conductive path and IPC-2292 Working Draft Master April 2017 the temperature difference across the material. Conduction is inversely proportional to the length of the path and the thickness of the material (see Table 7-1). Table 7-1 Effects of Material Type on Construction Thermal Conductivity (K) Material Watts/m °C Gram-Calorie/cm °C c s Still Air 0.0276 0.000066 Epoxy 0.200 0.00047 Thermally Conductive Epoxy 0.787 0.0019 Aluminum Alloy 1100 222 0.530 Aluminum Alloy 3003 192 0.459 Aluminum Alloy 5052 139 0.331 Aluminum Alloy 6061 172 0.410 Aluminum Alloy 6063 192 0.459 Copper 401 0.464 Steel Low Carbon 46.9 0.112 7.1.2 Radiation Thermal radiation is the transfer of heat by electromagnetic radiation, primarily in the infrared (IR) wave- lengths. It is the only means of heat transfer between bodies that are separated by a vacuum, as in space environments. Heat transfer by radiation is a function of the surface of the ‘‘hot’’ body with respect to its emissivity, its effective surface area and the differential to the fourth power of the absolute temperatures involved. The emissivity is a derating factor for surfaces that are not ‘‘black bodies.‘‘ It is defined as the ratio of emissive power of a given body to that of a black body, for which emissivity is unity (1.0). The optical color of a body has little to do with it being a ‘‘thermal black body.‘‘ The emissivity of anodized aluminum is the same if it is black, red or blue. However, sur- face finish is important. A matte or dull surface will be more radiant than a bright or glossy surface (see Table 7-2). Table 7-2 Emissivity Ratings for Certain Materials Material and Finish Emissivity Aluminum Sheet - Polished 0.040 Aluminum Sheet - Rough 0.055 Anodized Aluminum - any color 0.80 Brass - Commercial 0.040 Copper - Commercial 0.030 Copper - Machined 0.072 Steel - Rolled Sheet 0.55 Steel - Oxided 0.667 Nickel Plate - Dull Finish 0.11 Silver 0.022 Tin Oil Paints - Any Color 0.043 0.92-0.96 IPC-2292 Working Draft Master Lacquer - Any Color April 2017 0.80-0.95 Devices, components, etc. close to one another will absorb each other’s radiant energy. If radiation is to be the principal means of heat transfer, ‘‘hot’’ spots should be kept clear of each other. 7.1.3 Convection The convection heat transfer mode is the most complex. It involves the transfer of heat by the mixing of fluids, usually air. The rate of heat flow by convection from a body to a fluid is a function of the surface area of the body, the temperature differential, the velocity of the fluid and certain properties of the fluid. The contact of any fluid with a hotter surface reduces the density of the fluid and causes it to rise. The circulation resulting from this phenomenon is known as ‘‘free’’ or ‘‘natural’’ convection. The air flow can be induced in this manner or by some external artificial device, such as a fan or blower. Heat transfer by forced convection can be as much as ten times more effective than natural convection. 7.1.4 Altitude Effects Convection and radiation are the principal means by which heat is transferred to the ambient air. At sea level, approximately 70% of the heat dissipated from electronic equipment might be through convection and 30% by radiation. As air becomes less dense, convective effects decrease. At 5200 m [17060.37 ft], the heat dissipated by convection may be less than half that of radiation. This needs to be considered when designing for airborne applications. 7.2 Heat Dissipation Considerations To remove heat from a printed electronic layer or from high thermal radiating component the designer should consider the use of: Thicker or wider conductors to decrease heat generation due to resistance Heatsinking to internal or external planes (usually copper or aluminum) Thermal vias through substrate or direct contact with substrate Thermal dielectrics Heatsinking through the substrate and highly conductive substrates Special heatsink fixtures Connection to frame techniques Liquid coolants and heatsink formation Heat pipes Heatsinking constraining substrates 8 COMPONENT AND ASSEMBLY ISSUES Mounting, inserting and attaching components play an important role in the design of flexible printed electronic design. The printed design impacts assembly, interconnect integrity, repairability and testing. Therefore, it is important that the design reflects appropriate tradeoffs that recognize these and other significant manufacturing and reliability considerations and that special mounting configurations be detailed within the printed electronic design documentation. The designer must consider the ordering of printed materials and insertable/placeable components in the design process to ensure interconnection is possible. IPC-2292 Working Draft Master April 2017 The designer must also consider interconnect strategy, because some interconnects will impact the order of printed interconnects as well as the methods required to reach interconnects of different elevations. Order of operation will have an influence on overall inspection and test strategy and may require interim inspections and tests. All components shall be selected so as to withstand the regional flexure, vibration, mechanical shock, humidity, temperature cycling, and other environmental conditions the design will be required to endure during installation and subsequently through its entire lifetime usage. The following are requirements the designer must consider and detail on the assembly drawing in specific notes or illustrations. As a minimum, component mounting and attachment shall be based on the following considerations, as applicable: Electrical performance and electrical clearance requirements of the circuit design Environmental end-use requirements Installation and operational flexure Selection of active and passive electronic components and associated hardware Size and weight Minimizing heat-generation and heat-dissipation problems Manufacturing, processing and handling requirements Contractual requirements Serviceability requirements Equipment usage and useful life Automatic insertion and placement requirements, when these methods of assembly are to be used Test and inspection methods to be employed before, during and after assembly Field repair and maintenance considerations Stress relief Adhesive requirements Because of the wide range of substrates materials, the design should be reviewed for thermal management with respect to component assembly methods and techniques. 8.1 Lands for SMT Components Many SMT components are susceptible to damage from flexure. The designer should consider using typical SMT components only in supported areas of flexible printed electronic. The selection of the design and positioning of the land geometry in relation to the part may significantly impact the attachment joint. The designer must understand the capabilities and limitations of the manufacturing and assembly operations (see IPC-7351). Special consideration should be taken for coverlay/dielectric openings to compensate for attachment slump or spread. 8.2 Constraints on Mounting to Flexible Sections Designs shall not place a component in an area of continuous flexing or in an area that will be flexed, folded or flexed as part of a flex-to-install, without considering flexural damage. Leads mounted through flexible material should be fully clinched. If unclinched leads are required, supporting hardware, encapsulants or stiffeners should be designed as a part of the flexible printed electronic to ensure no flexure-related stresses are exerted on the attachment joints. IPC-2292 Working Draft Master April 2017 8.3 General Placement Requirements 8.3.1 Automatic Assembly When automatic component insertion/placement and attachment is employed, there are several electronic design parameters that shall be taken into account that are not applicable when manual assembly techniques are used. 8.3.1.1 Printed Substrate Size The size of the substrate to be automatically assembled can vary substantially. Therefore, manufacturer’s equipment specifications should be evaluated with respect to the finished printed electronic requirements. 8.3.1.2 Component Placement Automatic assembly considerations for SMT components include pick-and-place machines used to place/position components. SMT component design restrictions shall maintain appropriate clearances for the automatic pick-and-place equipment to position the parts in their proper orientation and allow sufficient clearances for the placement heads (see IPC-SM-780). Clearances should be provided to allow for inspection of component interconnects wherever possible (see IPC-7351). Through-hole components require specific consideration to providing the allowable clearances for the insertion and clinching of leads of the components. See IPC-2221 and IPC-CM-770 for specific details. The variations in the actual placement of the component in addition to the tolerances on the component’s envelope (body and leads) will cause movement of the component body from the intended nominal mounting location. This misregistration shall be accounted for such that worst-case placement of components shall not reduce their spacing to adjacent conductive elements by more than the minimum required electrical spacing. If a component is bonded to the surface of the printed assembly utilizing an adhesive (structural or thermally conductive), the placement of the component shall consider the area of adhesive coverage such that the adhesive may be applied without flowing onto or obscuring any of the terminal areas. Part attachment processes shall be specified which control the quantity and type of bonding material such that the parts are removable without damage to the printed assembly. The adhesive used shall be compatible with the substrate, component and any other parts or materials in contact with the adhesive. For some adhesives, contact with adjacent components may not be acceptable. Contact on attachment terminations or stress relief areas of adjacent components are other areas that are dependent on the material. Other considerations and concerns which affect part placement include: Thermal concerns Functional partitioning Electrical concerns Packing density Pick-and-place machine limitations Wave soldering holder concerns Vibration concerns Part interference concerns IPC-2292 Working Draft Master April 2017 Ease of manufacture Consider placing parts on a placement grid whenever possible. The placement grid facilitates not only parts placement but also standard bed-of-nails testing of the printed assembly. If bed-of-nails testing is to be used, test fixturing becomes much more difficult when components are placed off-grid. Considerations for part mounting: Functions of the type of component Mounting technology selected for the printed assembly Component lead-bending requirements Lead stress relief method component Component placement (mounted over surfaces without exposed circuitry, over protected surfaces or over circuitry) Component compatibility with printed conductors and attachments Additional requirements are dependent upon the thermal requirements (operating temperature environment, maximum junction temperature requirements, and the component’s dissipated power) and the mechanical support requirements (based on the weight of the component). Mounting methods for components of the printed assembly shall be selected so the final assembly meets applicable vibration, mechanical shock, humidity and other environmental conditions. The components shall be mounted such that the operating temperature of the component does not reduce the component’s life below required design limits. The selected component mounting technique shall ensure that the maximum allowable temperature of the printed material is not exceeded under the printed electronic’s operating co n di tio ns . The designer shall address component heatsink considerations and printed electronic heatsink requirements in parts placement. 8.3.2 Orientation The design shall ensure the orientation (or polarization) of the component has been adequately specified and coordinated with assembly equipment orientation requirements. Techniques may include special symbols, or special land configurations to identify such characteristics as a lead of an integrated circuit package (generally pin 1), positive lead of a capacitor or cathode lead of a diode. 8.3.3 Accessibility Electronic components should be located and spaced so the attachment lands for each component are not obscured by any other component or permanently installed parts. Each component should be capable of being removed from the assembly without having to remove any other component. These requirements do not apply to assemblies manufactured with no intent to repair (throw-away assemblies). Inspection, testing and rework/removal must also be considered for components that require embedding or encapsulation as part of the assembly process. The designer should also consider a test strategy for components that will not be accessible. Components that are inaccessible after completion of the printed assembly may require an interim test or inspection strategy to mitigate scrap potential. 8.3.4 Design Envelope The projection of the component, other than connectors, should not extend over the edge of the printed assembly or interfere with printed assembly component mounting. Components that protrude beyond the substrates can be particularly susceptible to handling damage. IPC-2292 Working Draft Master April 2017 Unless otherwise detailed on the assembly drawing, the printed assembly edge is regarded as the extreme perimeter of the assembly, beyond which no portion of the component, other than the connector, extends. The designer shall prescribe the perimeter with due regard for maximum part body dimensions and the mounting provisions dictated by the printed assembly documentation. 8.3.5 Flush Mounting Over Conductive Areas Conductive areas, excluding soldered lands, under the parts shall be protected against moisture entrapment by one of the following methods: Application of conformal coating using material in accordance with IPC-CC-830 (usually specified on the assembly drawing) Application of cured dielectric coating Application of an encapsulant dielectric Other insulation (e.g., Kapton™ tape) Metal-cased components shall be mounted so they are insulated from adjacent electrically conductive elements. Insulation materials shall be compatible with the substrate and other printed materials. 8.3.6 Clearances The minimum clearance between component leads or components with metal cases and any other conductive path shall be maintained based on material and deposition technique. Parts and components shall be mounted so they do not obstruct solder flow onto the topside termination areas of through hole metallization. 8.3.7 Physical Support Depending on weight and heat generation characteristics, components weighing < 5 grams per lead which dissipate < 1 watt and are not clamped or otherwise supported shall be mounted with the component body in intimate contact with the printed substrate if practical, unless otherwise specified. 8.3.7.1 Filleting See IPC-2221. 8.3.9 Stress Relief When designing for stress relief, lands and terminals shall be located by design so components can be mounted or provided with stress-relief bends in such a manner that leads cannot overstress the part/lead interface when subjected to the anticipated environments of temperature, vibration and shock. See IPC-2221. 8.4 General Attachment Requirements 8.4.1 Thermal Processing Considerations The designer shall ensure components are capable of withstanding sintering, curing and soldering temperatures used in the printing, post processing and assembly process. Other maximum temperature excursions must be considered for impact on components. This can include plating surfaces previously printed with a seed layer for conductivity. When design restrictions mandate mounting components incapable of withstanding required processing temperatures, such components shall be mounted and attached to the assembly as a separate operation after this processing. IPC-2292 Working Draft Master April 2017 8.4.2 Fastening Hardware The installed location and installation orientation for fastening hardware shall be prescribed on the assembly drawing for such devices as rivets, machine screws, washers, inserts, nuts and bracketry. Specifications and precautions of tightening torques shall be provided wherever general assembly practice might be inadequate or detrimental to the assembly’s structure or functioning. The use of such hardware shall be in accordance with the clearance requirements of this section. 8.4.3 Stiffeners Stiffeners are designed into the printed assembly to provide rigidity to the assembly and to prevent flexing of the printed materials and components, which could cause cracking during mechanical stress due to expansion/contraction or flexure. Stiffeners may be attached to the printed assembly by various fastening methods (e.g., solder, bonding, nuts and bolts). Adequate physical and electrical clearance should be provided between stiffeners, conductors and components. Nonconductive stiffeners should be incorporated where adequate clearance from conductors cannot be provided. 8.4.4 Wire Assembly It may be necessary to include point-to-point wiring as a part of the design. Such wiring shall be considered as part of the printed assembly process and treated as components. Their use shall be documented on the printed assembly drawing and planned for in the build strategy. Wires shall be permanently fixed to the printed assembly at intervals not to exceed 25 mm [0.984 in]. Wires < 25 mm [0.984 in] in length may be uninsulated, provided their paths do not pass over conductive areas and they do not violate spacing requirements. Insulation, when required on wires, shall be compatible with the use of any printed materials and coatings applied after assembly. Bus wire consists of a single strand of wire that is of sufficient cross-section to be compatible with the electrical requirements. This wire may be bare, sleeved or come with an insulated coating. This bus wire may be applied to the surface of the printed assembly, embedded in channels or covered by other printed dielectrics. When using nonsealed wire insulation, consider the assembly cleaning process. Insulated stranded wire consisting of multiple strands of wire purchased with an insulating material (e.g., polymer coating) may also be used. Designs using wires shall adhere to the following rules: Minimum electrical clearances shall be maintained for embedded wires. The thickness of the dielectric between the wire and other conductive elements must be of a tolerance to meet minimum electrical spacing. Bend radii for wires should conform to that of normal component bend requirements (see XXXX) Sleeving shall be of sufficient length to ensure its slippage at either end of the wire will not result in a gap between the insulation and solder connection or wire bend that violates minimum electrical clearance distances. Also, the sleeving chosen shall be able to withstand the wire to printed assembly attachment operations and subsequent processing (e.g., additional layer printing and curing, coating, plating, etc.). 8.4.5 Bus Bar Bus bars are usually in the form of preformed components that are part of the printed assembly and serve the function of providing most, if not all, of the power and ground distribution over the printed assembly. Their use is primarily to minimize the use of printed circuitry for power and ground IPC-2292 Working Draft Master April 2017 distribution and/or to provide a degree of power and ground distribution not cost-effectively provided by printing. The number of conductor levels in the bus bar, the type and number of their terminals, the size and finish of their conductors and the dielectric strength of their insulation all depend on the application. However, these parameters should be clearly defined on the procurement document for these parts. 8.4.6 Component Selection Considerations See IPC-2221 for more specifics on component usage and selection. Component Sizes: Generally, the largest component that can be placed with vision alignment is 1,300 mm2 [51.181 in2], measured to the outside of the leads. Large packages exaggerate the effects of the thermal mismatch between the component and substrate. Normally, the minimum size leadless component that can be placed with automatic equipment is 1.5 mm [0.0591 in] nominal length by 0.75 mm [0.0295 in] nominal width. Smaller components require high placement accuracy. Vacuum pickup with standard equipment is also difficult. Typically, fine-pitch devices could be between 250 mm2 and 775 mm2 case size for automatic placement without vision. Avoid extremely small passive components. Footprints should be large enough to permit reliable printing of attachment and conductive materials and placement of the component without smearing materials to adjacent conductive areas. Component Thickness: Leadless passive components should have an aspect ratio greater > 1 and < 3. High-aspect-ratio parts tend to fracture during soldering temperature excursions. Square devices (aspect ratio = 1) are difficult to orient. Polarity Markings: Special orientation symbols should be incorporated into the design to allow for ease of inspection of the assembled surface-mounted part. Techniques may include special symbols or special land configurations to identify such characteristics as pin 1 of an integrated-circuit package. Special orientation symbols shall be provided for Class 3 product. Reliability/Mounting Concerns: Flexure and expansion/contraction of the substrate shall be considered when selecting SMT devices. Localized stiffening, die thinning, bonding and encapsulation can be used to decrease the impact of substrate flex and stretch. Bare die may also be attached directly to the printed assembly. Flexure and expansion/contraction of the substrate must also be considered for the bare die. In addition to the stress-reduction methods discussed above, die-attach material selection is critical for reducing stresses imparted on the die. Interconnection Requirements: Components leads and terminations may either be attached to the conductive areas created through printing prior to assembly, or connections may be printed to the devices after assembly. The process for completing the connection (soldering, binding, sintering and curing) must be considered for impact to the components being assembled and the printed assembly itself. Temperature excursions may dictate the order of assembly or printing and must be considered in the design process. Printed connections to elevated component terminations require special considerations. Printed interconnects often require ramp materials to be added to change elevations in printing level to avoid stresses on the connection through operational and environmental cycling. Cavities and clearances can be used to create level surfaces for interconnects, but the tolerances on both component thicknesses and cavity height variation must be considered. See Figure 8-1. Inspection Requirements: If X-ray or other inspection methods will be used, components should be designed to avoid image obstruction of other components. Embedded Devices: Necessary thermal conduction shall be considered, in addition to the electrical connections, when embedding devices in the printed assembly. IPC-2292 Working Draft Master April 2017 See IPC-2221 for more specifics on SMT component usage. Figure 8-1 Examples of Ramps 9 HOLES/INTERCONNECTIONS 9.1 Printed Land Requirements All printed lands for subsequent SMD components shall be maximized wherever feasible, consistent with good design practice and electrical clearance requirements. 9.2 Holes 9.2.1 Unsupported Holes These types of holes pass through the entire printed board thickness. They may be used for tooling, mounting or component attachment. Since unsupported holes are a critical element for alignment of printed board assemblies, they typically are listed as datums in fabrication drawings. 9.2.1.1 Registration Tooling Holes This type of hole is a physical feature in the form of a hole, or slot, on a printed sheet. a) Registration during printing. b) Registration during lamination of subsequent layers. c) Functional test. The designer is responsible for indicating the tooling holes that stay with the printed sheet. The printed sheet manufacturer is responsible for determining the tooling holes needed for printed board fabrication. IPC-2292 Working Draft Master April 2017 9.2.1.2 Mounting Holes These are holes that are used for the support of a printed flex or for the mechanical attachment of components to the printed conductors. 9.2.2 Printed Through-Holes This type of hole has conductor on both sides of the printed sheet and the conductor fills the hole to make electrical connection to both sides of the sheet. 10 DOCUMENTATION The printed assembly documentation package consists of the printed assembly model, artwork and material callout for each layer to be added, parts lists, and schematic/logic diagram. The documentation package should be provided as electronic data. All electronic data should meet the requirements of the IPC-2500 series of standards. Other documentation may include numerical control data for drilling, routing, hole filling, multi-tiered layer printing, libraries, test, artwork, material cure schedules, cross sectional drawing, and special tooling. There are design and documentation features/requirements that apply to the basic layout, the artwork, the substrate itself, and the end-item assembly; all should be taken into consideration during the design of the printed assembly. Therefore, it is important to understand the relationships they have with one another as shown in Figure. The documentation shall meet the requirements of IPC-2610. In order to provide the best documentation package possible, it is important to review IPC-2610 and identify all the criteria that are affected by the design process, such as: Parts information Nonstandard parts information Master drawing Artwork master production Master pattern drawing Material cure schedules 10.1 Special Tooling During the formal design review prior to layout, special tooling that can be generated by the design area in the form of artwork or numerical control data shall be considered. This tooling may be needed by fabrication, assembly, or testing. Examples of such tooling are: Via land masters to assist in determining the location of the vias during printing. Artwork overlays to provide aids such as artwork origins, spotter locations for throughholes to be filled, printed assembly coordinate zero, printed assembly profile, test coupon profile, or profile of multi-layer interconnects. Artwork for protective layers. Artwork overlays that can be used in assembly to assist with component assembly. Numerical data for auto-placement equipment at assembly. Layer stencil or dispense area data. Recommended order of cure operations IPC-2292 Working Draft Master April 2017 10.2 Layout 10.2.1 Viewing Appendix B shows several typical layout views. Distinguishing characteristics shall be used to differentiate between conductors on different layers of the printed assembly. 10.2.2 Accuracy and Scale The accuracy and scale of the model, drawings, and layers shall be sufficient to eliminate inaccuracies when the layout is being interpreted during the printed assembly processes. 10.2.3 Model and Drawing Notes The model and drawings should be completed with the addition of appropriate notations, marking requirements, and revision/status-level definition. This information should be structured to assure complete understanding by all who view the model. Notes are especially important for the engineering review cycle, the program generation effort, and when the models/drawings are used by someone other than the originator. 10.2.4 Automated-Layout Techniques All the information listed in 10.2.1 through 10.2.3 is applicable to automated layout, model and artwork generation however, they should also match the design, printing, and assembly system being employed. Much of the equipment available today comes with its own process development software but will accept common standard formats. When automated systems are required to communicate with each other, it is recommended that standard files be used for this technique (.STL, .DXF, and others). These formats have been developed to serve as the standard format to facilitate the interchange of information between automated systems including the printing, slicing, and placement automation software. Archiving of data should be in accordance with those documents. Delivery of computergenerated data as a part of a documentation package should meet these requirements With automated techniques, the data base should detail all the information that will be needed to produce the printed electronic. This includes all notes, printed materials requirements, printed electronic thickness, etc. A check plot may be employed to verify that the data base matches the requirements. 10.3 Deviation Requirements Any deviation from this standard or drawing shall have been recorded on the master drawing or a customer-approved deviations list. 10.4 Phototool Considerations The same design pattern configuration and nominal dimensions may be used for preparing the phototool for stencil or screen applications. 10.4.1 Artwork Master Files An electronic data file or alternative physical media, which defines the master image for each layer, that shall be provided as part of the master drawing set. IPC-2292 Working Draft Master April 2017 10.4.2 Coating Phototools Coating phototools provide a special design pattern using larger shapes to establish the coating clearance around the required non-coated areas. There may be other factors, such as fiducials, mounting holes and substrate edges which may require clearances. 11 QUALITY ASSURANCE Quality assurance shall be considered in all aspects of the printed electronic design. Quality assurance evaluations relating to design shall consist of the following unless otherwise stated: Material Conformance and Process Control Inspection and Acceptance In addition, the supplier shall comply with IPC-9191 when providing product meeting or exceeding requirements specified herein. This section defines the allowable methods (options) of assuring that the product meets customer specifications. 11.1 Material Quality Assurance Material inspections normally consist of certification by the manufacturer supported by verifying data based on statistical sampling that all materials which become a part of the finished product are in accordance with the master drawing, material specifications, and/or procurement documentation. Printed Electronic Base Materials Material requirements for Printed Electronics Functional Base Materials are defined in accordance with IPC 4921. Printed Electronic Conductive Materials Material requirements for Printed Electronics Conductive Materials are defined in accordance with IPC 4591. Printed Components Printed component suggested performance criteria and testing methods are defined in accordance with IPC/JCPA-6901. In addition, performance criteria and test methods for adhesives per IPC-4202/IPC-4203/IPC-FC-234 and materials per IPC-4204 and IPC-4203 may be used where individual components are specified. 11.2 Statistical Process Control (SPC) SPC utilizes systematic statistical techniques to analyze a process or its outputs. The purpose of these analyses is to take appropriate actions to achieve and maintain a state of statistical control and to assess and improve process capability. The primary goal of SPC is to continually reduce variation in processes, products, or services in order to provide product meeting or exceeding real or implied customer requirements. Implementation of SPC shall be in accordance with IPC-9191.Depending on the progress made in implementing SPC on a particular product, an individual supplier may demonstrate compliance to specification with any of the following: Quality Conformance Evaluations End-Product Control In-Situ Monitoring Product Control Process Parameter Control An individual supplier may choose to use a combination of the four assurance techniques listed above to prove compliance. For example, a product with 15 characteristics may meet specifications by quality IPC-2292 Working Draft Master April 2017 conformance evaluations on two characteristics, in-process product evaluations on five characteristics and process parameter control for five characteristics. The three remaining characteristics meet the specification by a combination of in-process control and quality conformance evaluations. Evidence of compliance to the specification at the level of SPC implementation claimed is auditable by the customer or appointed third party. Requirements are dynamic in nature and are based on what is accepted in the worldwide market. Requirements may be stated as a reduction of variation around a target value, as opposed to just meeting the specification, drawing, etc. Conformance evaluations are performed on production printed electronics and/or conformance coupons. 11.3 Build and Manufacturing Controls Build (Plans, Software, Recipe, etc.) and manufacturing (Parameter, Feedstock, Thermal, etc.) controls shall be under configuration control in accordance with ANSI/EIA-649. Configuration management principles provide a positive impact on product quality, cost, and schedule by ensuring consistency of a product's performance, functional and physical attributes with its requirements, design, and operational information. 11.4 Conformance Test Coupons Coupons required for conformance evaluation shall be as defined herein. Additional conformance coupons may be added by the manufacturer. Conformance coupons shall be traceable to the production part. Quality assurance provisions often require the use of specific test procedures or evaluations to determine if a particular product meets the requirements of the customer or specifications. Some of the evaluations are done visually, others are done through destructive and nondestructive testing. Some quality evaluations are performed on test coupons because the test is destructive or the nature of the test requires a specific design which may not exist on the printed electronic. Test coupons are used in these types of tests as representatives of the printed electronics fabricated at the same time. A test coupon is a suitable sample for the destructive testing since it has been subjected to the same processes as the printed electronic during the build; however, the design and location of the test coupons are critical in order to ensure that the coupons are truly representative of the printed electronic. In process tests may be used in lieu of post process coupon testing to confirm process performance. 11.4.1 Individual Coupon Design Individual test coupons are designed to evaluate specific individual characteristics and the printed electronics they represent. When coupons are used to establish process control parameters, they shall consistently use a single configuration which reflects the process. Process characteristics and general printed electronic characteristics should be matched (ex. Line length, annular ring, printed vias, etc.). Coupons should be used for mechanical, electrical, and environmental tests such as; bending, flexibility, endurance, resistance, tensile, peeling and adhesion tests. 11.4.2 Coupon Quantity and Location The conformance coupon shall be a part of every build used to produce printed electronics when required by the procurement documentation or applicable performance specification. Coupons of custom configuration may be designed to accomplish specific user/supplier agreements. The custom coupons should incorporate features on the same dimensional plane to ensure compatibility with other standard coupons and the applicable performance specification. IPC-2292 Working Draft Master April 2017 All applicable configurations of test coupons shall be defined on the master artwork, the master drawing or added to the build artwork by the manufacturer to accommodate requirements of the performance specification. The fabricator may position the coupons within the process verification coupon zone and/or the available printed electronic real estate zone in order to optimize build area, tooling and material utilization. The fabricator should designate coupon regions to span in all 3 dimensions. For each build, test coupons shall be designed and oriented to represent the dimensions of the printed electronic part in the X-direction, Y-direction, and the entire length of the Z-direction. 11.4.3 Process Control Test Coupon Process control test coupons are used at strategic points in the process flow to evaluate a specific process or set of processes. The designs of the process control test coupons are at the option of the printed electronic fabricator. Each design is specific to the processes for which the fabricator intends to evaluate. Process control evaluations are established through a systematic path for implementing statistical process control. This includes those items shown in Figure 11-1. If the contract permits the use of process control coupons in lieu of conformance coupons, the design of the coupon shall be agreed to between the user and manufacturer. The design of existing test coupons can serve as a guide for the design of process control test coupons. In general, the design of the coupon is consistent with the process to be evaluated rather than an attempt to represent a printed electronic design. Figure 11-1 Systematic Path for Implementation of Statistical Process Control (SPC) IPC-2292 Working Draft Master April 2017 11.4.4 Tolerances and Reporting Data Tolerances for the fabrication of test coupons shall be the same as those for the printed electronic. Reporting Data for Test Specimens Prepared by Additive Manufacturing should be in accordance with ASTM F2971. 11.4.5 Coupon Identification Conformance coupons shall provide space for: Printed electronic part number and revision letter Traceability identification Lot date code Manufacturer’s identification, (ex, Commercial and Government Entity (CAGE)), logo, etc. 11.5 Responsibility for Inspection Unless otherwise specified in the purchase order, the supplier is responsible for the performance of all inspection requirements as specified herein. Except as otherwise specified in the purchase order, the supplier may use their own or any other facility suitable for the performance of the inspection requirements herein, unless disapproved by the procuring authority. The procuring authority reserves the right to perform any of the inspections set forth in the standard where such inspections are deemed necessary to assure supplies and service are performed to the prescribed requirements. 11.6 Test Equipment and Inspection Facilities Test and measuring equipment and inspection facilities of sufficient accuracy, quality and quantity to permit performance of the required inspection shall be established and maintained by the supplier. The establishment and maintenance of a calibration system to control the accuracy of the measuring and test equipment shall be in accordance with ANSI/ NCSL Z 540.1, or alternative statistically sound calibration procedures. 11.7 Preparation of Samples Unless otherwise specified herein, samples shall be prepared in accordance with standard in-house procedures. If a method is required, it shall be AABUS. 11.8 Standard Laboratory Conditions Unless otherwise specified in the appropriate test method, laboratory conditions shall be established and documented by the supplier. 11.9 Tolerances Unless otherwise specified, all laboratory equipment/conditions shall have tolerances of ±5%. 11.10 Qualification Inspection Qualification testing shall be performed on the test specimens that are produced with equipment and procedures normally used in production. The supplier shall supply upon request data certifying the printed electronics base material meets the requirements of this standard using the test methods described herein. Qualification testing samples may be combined for those IPC-2292 Working Draft Master April 2017 11.11 Failures If one or more specimens fail, the sample shall be considered to have failed. In the event of failure of any inspection, information concerning the failure and corrective action taken shall be furnished to the user. 11.12 User Sampling Plan Use of sample-based inspection shall be done only as part of a documented process control system per 11.2. 11.13 Noncompliance of Material If a sample fails to pass inspection, the supplier shall take corrective action on the materials or processes, as warranted. The supplier shall also take corrective action on all units of product that can be corrected, which were manufactured under essentially the same conditions, with essentially the same materials, process, etc. Acceptance of the product shall be discontinued until corrective action acceptable to the procuring authority has been taken. If rework of the noncompliance is possible, the supplier shall propose the appropriate rework methods to the procuring authority and the implementation shall be AABUS. After corrective action has been taken, inspection shall be repeated on additional sample units (all inspection or the inspection that the original sample failed, at the option of the procuring authority). In the event of failure of any inspection, information concerning the failure and corrective action taken shall be furnished to the procuring authority. 11.14 Reduction of Quality Conformance Testing The primary goal of SPC is not the reduction of quality conformance testing. The primary goal of SPC is to continually reduce variation in processes, products, or services in order to provide product meeting or exceeding real or implied customer requirements. However, as a result of the understanding and control of highly capable process and product parameters, quality conformance testing may be reduced in an orderly fashion to an audit function. Once the criteria have been met, the reduction of end product testing may be accomplished (ex. In-Situ Product Monitoring). 11.15 Inspection Methodology 11.15.1 Process Verification Inspection Process verification inspection shall consist of the following: Surveillance of the build and manufacturing controls are being properly applied. Surveillance of the operation to determine that practices, methods, procedures and a written inspection plan are being properly applied. Inspection to measure the quality of the product. 11.15.2 Visual Inspection The assembly shall be evaluated in accordance with the established process control plan, see 11.3, by 100% visual inspection and/or by 3D Measurement Technology if AABUS. Inspection are to be performed after all processes have been completed. IPC-2292 Working Draft Master April 2017 11.15.3 Magnification Aids Magnification power for visual inspection shall be 1.75X and limited to 4X maximum. If the presence of a defect cannot be determined at the inspection power, the item is acceptable. The maximum magnification power is intended for use only after a defect has been determined but is not completely identifiable at the inspection power. The tolerance for magnification aids is ± 15% of the selected magnification power. Magnification aids should be maintained and calibrated as appropriate, see IPC-OI645. Supplemental lighting may be necessary to assist in visual assessment. 11.15.4 Acceptance Test Activities Acceptance and test activities are integral to process control and may be in accordance with IPC-TM-650 and/or AABUS. Many AM technologies can produce more than one device or component simultaneously on different locations in the build volume. These devices or components can be copies of a single design or different designs. This poses a unique challenge in ensuring repeatability and consistency within a build cycle and across lots. Some acceptance activities for individual devices or components can be performed through nondestructive evaluation (NDE). Specifically, NDE techniques can be used for the verification of geometry, microstructure, and some performance characteristics. Techniques include, but are not limited to: Ultrasound Computed tomography (CT) or micro-CT X-ray (in cases where the geometry is simple) Confocal microscopy Hyperspectral imaging Penetrant inspection In-situ monitoring 11.15.4.1 Other Nondestructive Tests Nondestructive tests, procedures, techniques, equipment, or materials (e.g., Acoustic Emission, Electromagnetic or Eddy Current, Leak, Neutron Radiographic, etc.) not specifically addressed in this document may be used in conjunction with those stated on drawing or in the contract. When one or more of these inspection methods are indicated, an approved standard shall be determined by the Engineering Authority. IPC-2292 Working Draft Master April 2017 Appendix A – Sample Design Constructions 1.2.1 Single Layer Single Side This construction will have a printed conductor element on a base substrate which can be a bare substrate or have a patterned conductive element. Figure 1-1 shows the printed conductor on both the bare substrate and connecting with the patterned conductor. Actions: Need Alan to draw second picture without the patterned conductor. Richard will create proposed naming conventions to replace “layer” in the figures and tables. Figure 1-1 One Additive Print, Single Side T1 Printed Conductor Note: remove 2 from figure. 1.2.2 Single Layer Single Side with External Insulator Figure 1-2 Single Layer Single Side with External Insulator Layer # 1 2 3 4 Layer Definition Dielectric Conductor Patterned Conductor Substrate 1.2.3 Single Layer, Double Sided Optional - not printed IPC-2292 Working Draft Master Figure 1-3 Single Layer, Double Sided Layer # 1 Layer Definition Conductor 2 3 Patterned Conductor Substrate 4 5 Patterned Conductor Conductor Optional - not printed Optional - not printed 1.1.4 Single Layer, Double Side With Interconnected Sides Figure 1-4 Single Layer, Double Side With Interconnected Sides Layer # 1 Layer Definition Conductor April 2017 IPC-2292 Working Draft Master 2 3 4 Patterned Conductor Substrate Conductive Via 5 6 Patterned Conductor Conductor Optional - not printed Optional - not printed 1.2.5 Single Layer, Double Side With External Insulator Figure 1-5 Single Layer, Double Side with External Insulator Layer # Layer Definition 1 Dielectric 2 Conductor 3 Patterned Conductor 4 Substrate 5 Patterned Conductor 6 Conductor 7 Dielectric April 2017 IPC-2292 Working Draft Master April 2017 1.2.6 Single Layer, Double Side With External Insulator and Interconnected Sides Figure 1-6 Single Layer, Double Side with External Insulator and Interconnected Sides Layer # 1 2 Layer Definition Dielectric Conductor 3 4 5 Patterned Conductor Substrate Conductive Via 6 7 8 Patterned Conductor Conductor Dielectric 1.2.7 Double Layer, Single Sided Figure 1-7 Double Layer, Single Sided Optional - not printed Optional - not printed IPC-2292 Working Draft Master Layer # 1 2 3 Layer Definition Conductor Dielectric Conductor 4 5 Patterned Conductor Substrate Optional - not printed 1.2.8 Double Layer, Double Sided Figure 1-8 Double Layer, Double Sided Layer # Layer Definition 1 Conductor 2 Dielectric 3 Conductor 4 5 Patterned Conductor Substrate 6 7 8 9 Patterned Conductor Conductor Dielectric Conductor Optional - not printed Optional - not printed April 2017 IPC-2292 Working Draft Master 1.2.9 Double Layer, Double Sided With Interconnected Sides Figure 1-9 Double Layer, Double Sided With Interconnected Sides Layer # Layer Definition 1 Conductor 2 Dielectric 3 Conductor Optional - not 4 Patterned Conductor printed 5 Substrate 6 Conductive Via Optional - not 7 Patterned Conductor printed 8 Conductor 9 Dielectric 10 Conductor April 2017 IPC-2292 Working Draft Master 1.2.10 Double Layer, Single Sided With External Insulator Figure 1-10 Double Layer, Single Sided With External Insulator Layer Layer # Definition 1 Dielectric 2 Conductor 3 Dielectric 4 Conductor Optional - not 5 Patterned Conductor printed 6 Substrate 1.2.11 Double Layer, Double Sided With External Insulator Figure 1-11 Double Layer, Double Sided With External Insulator April 2017 IPC-2292 Working Draft Master Layer # 1 2 3 4 Layer Definition Dielectric Conductor Dielectric Conductor 5 6 Patterned Conductor Substrate 7 8 9 10 11 Patterned Conductor Conductor Dielectric Conductor Dielectric April 2017 Optional - not printed Optional - not printed 1.2.12 Double Layer, Double Sided With External Insulator and Interconnected Sides Notes: Show connection between conductor layers through dielectric. Build new cross-section that has multiple prints on substrate, multiple substrate prints, etc. Richard to come up with naming conventions by next meeting. Alan to draw one new view to include all possible via connections with multiple depths and a conductor from layer 2 to layer 6. Figure 1-12 Double Layer, Double Sided with External Insulator and Interconnected Sides Figure Legend 1 2 3 4 Dielectric Conductor Dielectric Conductor IPC-2292 Working Draft Master 5 6 7 Patterned Conductor Substrate Conductive Via 8 9 10 11 12 Patterned Conductor Conductor Dielectric Conductor Dielectric Optional - not additive printed Optional - not printed April 2017 IPC-2292 Working Draft Master Appendix A – Typical Layout Views for Printed Electronic Designs Note for review stage: Any references to product or company names will be removed before publication. Review team is invited to submit other layout views for inclusion in this appendix. April 2017 IPC-2292 Working Draft Master April 2017 IPC-2292 Working Draft Master April 2017 IPC-2292 Working Draft Master April 2017