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DESIGN AND FREQUENCY RESPONSE OF DIGITAL PHASE LOCKED LOOP (DPLL) USING SIMULINK Shashank Mishra Department of Electronics and communication Engineering Madan Mohan Malaviya University of Technology, Gorakhpur,India [email protected] Abstract—Design and simulation of Digital PLL has been illustrated in this paper. The Digital PLL is given signal of 400 MHz to 900 MHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the Digital PLL blocks are designed and simulated using Simulink. It is verified that Digital PLL is stable with a phase margin of 91.1 degree which satisfy the transfer function correctness. Keywords- DPLL, Phase frequency detector (PFD), Voltage controlled oscillator (VCO), Loop filter, Simulink. Introduction The phase-locked loop (PLL) constitutes an important “Mixed-Signal” device used in transceivers, communication systems etc. The PLL recovers clock from digital data signals, recovers the carrier from satellite transmission signals, performs frequency and phase modulation and demodulation and synthesize exact frequencies for receiver tuning. The best-known application of PLLs is clock recovery in communication, frequency synthesis, tracking filter, and phase modulation. Other applications include disk drive control, harmonic compensation, and motor control. The digital PLL (DPLL) is a type of PLLs used to synchronize digital signals. While DPLLs input and outputs are typically digital (square wave), they do have internal functions, which are dependent on analog signals. Thus they are basically known as classical DPLLs. The digital phase locked loop (DPLL) is a closed loop control system that has the ability to generate a feedback signal whose phase and frequency are aligned to the phase and frequency of the reference signal at locked condition [1]-[3]. The charge pump phase locked loop (CPPLL) is widely used for its frequency sensitive error signal, as it can aid acquisition when the loop is out of lock [1].It consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF) and a voltage controlled oscillator (VCO) in the forward path and a frequency divider (FD) in the reverse path. When the DPLL is in lock, there is a small phase difference between the two input signals of the phase frequency detector [2]. According to that error signal, the CP either increases or decreases the amount of charge to the LF. This amount of charge either speeds up or slows down the VCO and shifts the Dr.R.K.Chauhan Department of Electronics and communication Engineering Madan Mohan Malaviya University of Technology, Gorakhpur,India [email protected] VCO from its free running frequency and keeps the loop in lock [3]. . PFD (Phase-Frequency Detector) The Simulink model of the conventional sequential tri-states D flip-flop based PFD is shown in the Figure 1. A PFD with three states is widely used because of its wide linear range and ability to capture phase and frequency [1]. The reference signal and the feedback signal are given to the two input clock of the D flip-flop. The UP signal is created if the reference signal is faster than the feedback signal and DOWN signal is created if the reference signal is slower than the feedback signal. The UP and DOWN signals have no output signal when the reference and feedback signals are closed. This instant is known as dead zone condition. This problem can be avoided by using a delayed reset signal after the NAND gate as shown in the Figure 1. This delay in the reset path allows for both the UP and DOWN signals to activate the charge pump making the charge delivered to the loop filter proportional to the difference in duty cycle of these command signals [2]. Fig 1 Building Block of PFD Charge Pump (CP) The charge pump current drives the PFD output. It converts the output digital PFD signal into analog signal. The Simulink model of the charge pump circuit is shown in the Figure 2 [4]. Basically, the charge pump consists of a current source, a current sink and two switches. However, the charge pump is usually followed by a passive loop filter that integrates the charge pump output current to a VCO control voltage. Thus, the charge pump output voltage is always equal to the VCO control voltage. The charge pump either sources or sinks current according to UP and DOWN signal. This amount of current is converted into controlled voltage by the loop filter for tuning the VCO [3]. To avoid current mismatching, the source and sink current values should be same. The control voltage increases when the reference signal leads the feedback signal and decreases when reference signal lags the feedback signal. Fig 4 VCO simulation output at locking position Loop Filter The loop filter is most important functional block as it evaluates the performance of DPLL. The filtering operation of the error voltage coming from the PFD is performed by loop filter. Basically a loop filter is a 2nd order low pass filter having two poles and one zero which is responsible to give sufficient phase margin and a stable DPLL operation. Fig 2 Building block of charge pump circuit Voltage-Controlled Oscillator (VCO) The VCO produces a digital pulse train whose frequency is proportional to the voltage across capacitor C1 of the LPF. Generally the VCO is designed using CMOS technology. But in this paper, the behavioral VCO model has been implemented using Simulink which is shown in the Figure 4. The VCO is designed by considering the basic mathematical formulas and design specification. The design specification is given in the Table 1. The simulation result of the VCO at locking position is shown in the Figure 4.The output frequency of VCO is adjusted by means of controlled voltage VCTRL .such that FVCO=F0+KVCO*VCTRL where, F0 is free running frequency and KVCO is the sensitivity/gain of VCO. VCO basically generates a frequency with respect to the input voltage given by the formula. KVCO f max f min Vmax Vmin Table 2 Parameters Frequency Range Step Size Voltage Range Specifications 400-900 MHz 5 MHz 0-5 V Fig 5 Second order loop filter The transfer function of the 2nd order loop filter is given by F (s) VCTRL ( s ) 1 1 R || I CP ( s ) C1.s C 2.s Where VCTRL :is the voltage across the loop filter and ICP is the current coming from the charge pump circuit. F (s) K F ( s wz ) s s ( 1) wP R.C 2 C1 C 2 1 wz is a zero & R.C1 1 wp is a pole. R.C 2 Where K F The phase margin (PM) of the loop at unity gain is given by p ( wC ) tan 1 ( wC w ) tan 1 ( C ) wZ wP By differentiating this with respect to wC and equating to zero ,they maximum phase margin can be achieved which is equal to wC wZ .wP . Results and Discussion The DPLL has been simulated using SIMULINK .Table 1 shows the DPLL parameter values used for simulation process. The bode diagram of closed loop DPLL are shown in Figure 5.The result shows that Digital PLL is stable with a phase margin of 91.1 degree which satisfy the transfer function correctness. Fig 5 Bode plot of closed loop DPLL Conclusion In this paper, a DPLL is designed using SIMULINK under the frequency range of 400-900 MHz.The simulation result shows that the Digital PLL is stable with a phase margin of 91.1 degree which satisfy the transfer function correctness. The Digital PLL behavior has been studied inn broad sense and the performance has been evaluated using MATLAB. References [1]. W.F. Egan, 1981, Frequency Synthesis by Phase Locked Loop, Wiley, New York. [2]. R.E Best., 2003, Phase Locked Loop Design, Simulation and Application, McGraw-Hill, New York. Table2 Parameter Output Frequency Reference Frequency Loop Bandwidth Phase Margin Voltage Range Charge Pump Current VCO sensitivity Series Resistance Series Capacitance Parallel Capacitance Value 400-900 MHz 5 MHz 0.25 MHz 91.1 degree 0-5 V 500uA 100 MHz/V 290Ω 20pF 4pF [3]. Dan H. Wolaver, 1991, Phase-Locked Loop Circuit Design, Prentice Hall, New Jersey. [4] Govind Singh Patel and Sanjay Sharma, 2011, International Journal of the Physical Sciences, Vol. 6, pp. 2618-2632. [5] B. Razavi, 1998, RF Microelectronics, Prentice Hall, NewYork. [6]. G. Reehal, 1998, A Digital Frequency Synthesizer Using Phase Locked Loop Technique, Master Thesis, The Ohio State University, USA. [7] F. Gardner,1980, Charge pump phase-lock loops, IEEE Trans. Communication., Vol. 28, pp. 1849-1858. [8]. R.Jacob Baker, Harry W. Li, David E. Boyce, “CMOS Circuit Design, Layout, and Simulation.” IEEE Press, 2003. [9] “Synchronization in Digital Communications volume-1 Phase-, Frequency-Locked Loops, and Amplitude Control” by Heinrich Myer, John Wiley & Sons Inc.,1990