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Phase Frequency Detector (PFD) is one of the PLL blocks. The main concept of PFD is
comparing two input frequencies in terms of both phase and frequency [1]. In a PLL the two
frequencies are reference frequency (Fref) and the voltage controlled oscillator (VCO)
output after division by N (Fvco). The output is a pulse proportional to the phase difference
between the inputs and it drives the charge pump to either increase the control voltage of
the VCO or decrease it or keep it without change.
Basically three types phase frequency detectors are simulated over here, named as, simple
phase frequency detector, DCVSL phase frequency detectors, current mode logic phase
frequency detector.
Nominated power Supply
3.3 V
Power Dissipation
0.6mW, 1.6mw, 6.5mw
Process Technology
0.35 um CMOS technology
Here we have designed three types of phase frequency detectors and analysed their
different parameters at same input frequency and same input phase difference. In simple
phase frequency detector, simple NAND gates are used using CMOS technology. In DCVSL
PFD Differential cascode voltage switch (DCVS) logic is used which has potential advantages
over conventional NAND/ NOR logic in terms of circuit delay, layout density and logic
flexibility and in current mode logic, D latch is designed by using CML technology and it is
being used in PFD using DFF.
Different kinds of PFD have been designed with their corresponding results.
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