Download PART B UNIT I (i). State and prove Demorgan`s law (6) (EI May 2007

PART B
UNIT I
1. (i). State and prove Demorgan’s law (6)
(EI May 2007 & 2011)
(ii) Obtain the minimal SOP form for the following 6 variable switching function.(10)
F(x1,x2,x3,x4,x5,x6) =∑ m(2,3,6,7,10,14,18,19,22,23,27,37,42,43,45,46,58,59)
2. Minimise the boolean function using Quine-McCluskey method.
(EI May 2007)
F(x1,x2,x3,x4,x5) =∑ m(0,2,4,6,7,8,10,11,12,13,14,16,18,19,29,30).
3. Simplify the following Boolean equation.
i.
XY+X’Z+YZ
ii. (X+Y)(X’+Z)(Y+Z)
iii. XY’Z+XYZ
iv.
X’Y+XY’+XY
v.
A+AB
vi.
Xy+Xy’
vii.
X+X’Y
(EI Nov 2007)
4. Simplify a four variable function with a map for the following Boolean function.
i.
F(W,X,Y,Z)= ∑m(0,1,2,4,5,6,8,9,12,13,14)
(EI Nov 2007)
ii.
F(A,B,C,D)= ∑ m(0,1,2,4,5,10,11,13,15)
5. Find the minimum sum of products expression using K—map for the function F
∑m('7,9,10,11,12,13,14,15) and realize the minimized function using only NAND
gates.
(EC May 2007)
6. Simplify using Quine—McClusky method F =∑m(0,1,2,3,10,11,12,13,14,15).
7. Realize F(W,X,Y,Z) = S(1,4,6,7,8,9,10,11,15) using 4- to -1 Mux.
(EC Nov 2007)
8. Find the minimal sum of product form for the following switching function.
f(x1,x2,x3,x4,x5) = S m(2, 3, 6, 7, 11, 12, 13, 14, 15, 23, 28 29, 30, 31)
9. Simplify the following Boolean expressions
(i) (x1 + x2) (x1’x3’ + x3) (x2’ + x1x3)’. (6)
(EC May 2007)
(ii) Find the minimal sum of product expression for the following switching function.
f(x1,x2,x3,x4,x5) = ∑m (1, 2, 3, 6, 8, 9, 14, 17, 24, 25, 26, 27, 30, 31) + d(4,5).
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10. Simply the four variable switching function
F(A,B.C.D ) = ∑m (3,5,6,8,9,12,13,14)+ d(0,2,7).
(EC Nov 2007)
11. (i) Convert the following binary number to Decimal, Hexadecimal and Octal form.
(11011011.100101)2
(EI April 2010)
(ii) Encode the binary word 1011 into seven bit even parity Hamming code.
12 (i) Add the following hexadecimal numbers.
(4FB )16 , (75D)16 , (A12)16 and (C39)16
(EI April 2010)
(ii) Minimize the expression:
Y = A’B(CD)’ + A’BC’D + AB(CD)’ + AB’C’D + ABC’D + A’B’CD’
13. Simplify the following using Quine McCluskey method
(EI April 2011)
∑m (0,2,3,4,7,8,11,12,13)+ d(5,6). Realize the reduced function using only NAND
gates (16)
14. Simplify the following using K-map π M (0,1,3,6,8,9,11,15) (6marks) (EI April 2011)
15.(i) Perform the excess-3 addition of 8 and 6.(4 mark)
(ii) convert (11001011.01101)2 into decimal.(4 mark) (EI May/june 2013)
(iii)convert gray code 101011 into its binary equivalent.(4)
(iv) convert the expression A+BC in standard product of sum form.(4)
16. Reduce the function f(A,B,C,D)=πM(0,2,3,8,9,12,13,15) using K-Map and
Quine McClusely method . (EI May/june 2013)(16)
17.(i) convert the function f(A,B,C)=(A+B’+C)(A’+B+C’) into standard sum of
Product form. (EI Nov/Dec 2013) (5)
(ii)The hamming code 101101101 is received .correct it if any errors.
There are four parity bits and odd parity is used. (5)
(iii) Convert the following
1.(61.3)2
2.(37.29)2
3.(1011011)2 to gray code (6)
18. Determine the essential prime implicate of the following function and verify the kmap f=Ʃm(3,4,5,7,9,13,14,15) + Ʃd(0,1)(16) (EI Nov/Dec 2013)
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UNIT II
1. Design a decoder which displays the output of a decade counter on a seven segment
display?
(EI May 2007)
2. (i). Design a fulladder using only NAND gates.
(EI May 2007)
(ii).Draw a 32 x 1 Multiplexer using four 8 x 1 multiplexers and 2 to 4 decoder.
3. Illustrate the design procedure for a BCD to seven segment decoder.
(EI Nov 2007)
4. (i) Draw the logic diagram for a 2 to 4 line decoder.
(ii) Draw the logic diagram for a 4 to 1 Multiplexer.
(EI Nov 2007)
5. Design a 4 bit comparator using logic gates.
6. (i) Explain the Full subtractor. (6)
(EI May 2009)
(ii) Explain the 4 bit Adder - Subtractor using parallel load. How the detection of
overflow is verified? (10).
7. (i) Explain the function of demultiplexer and Parity checker. (8)
(ii) Describe the Binary to Gray code converter.
(EI May 2009)
8. (i) Implement the Boolean function F(x,y,z)= ~(1,2,6,7) using Multiplexer.
(EI May 2009)
9. (i) Design a Full Adder and realize it using only NOR gates.
(EI May’10)
(ii) Design a 2-bit Magnitude comparator to compare two 2-bit numbers.
10. (i) Design a 4-bit Binary to Gray Code Converter.
(EI May’10)
(ii) Implement the following function using suitable multiplexer. F(A,B,C,D)=
∑ (0,1,3,5,6,7,10,12,14)
11. Design the following circuits (16)
(i) Full adder
(ii) Magnitude comparator
(EI April 2011)
12. Design the following circuits
(i) Subtractor
(EI April 2011)
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13.(i) Implement the following Boolean function using suitable multiplexer
F(A,B,C)= Ʃm(1,3,5,6) (8)
(ii) Design full subtractor using half subtractor(8) (EI May/june 2013)
14. (i) Design a code converters for BCD to gray code converters (10)
(ii)Explain how the demultiplexer used as decoder.(6) (EI May/june 2013)
15.(i) Compare serial and parallel adder (6)
(ii)Implement following multiple output function using decoder and logic gates.
f1(A,B,C)= Ʃm(1,4,5,7)
f1(A,B,C)= πM(2,3,6,7) (EI Nov/Dec 2013)
16.(i)Construct a binary to BCD code converter using full address.(10)
(ii)Design a combinational logic circuit with 3 input variables that will produce
a logic 1 output when more than input variable are logic1. (EI Nov/Dec 2013)
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UNIT III
1.
Explain the working of a 4 bit binary Ripple counter.
(EI May 2007)
2.
(i) Draw the minimal state table for a synchronous sequential circuit having a
single input and single output. The output is to be zero unless an input sequence
0010 is received
(EI May 2007)
(ii). Define the following terms:
(1) State Equivalence
(2) Compatible states
3. Design a 4 bit synchronous counter using JK-FlipFlop
(EI Nov 2007)
4. Design a 3 bit counter to count the following sequence using JK Flip-Flop
0,1,2,4,5,6,0
5.
(i)What
is the characteristic equation of a D flip-flop?
(EC Nov 2007)
(ii)Using JK flip-flops, design a parallel counter which counts in the sequence
101,110,001,010,000,111,101,
6. Design a synchronous counter which counts in the sequence 0, 2, 6, 1, 7, 5, 0 ....
using D FFS. Draw the logic diagram and state diagram.
(EC May 2007)
7. Draw the circuit and explain the working operation of JK MS flip-flop.
(EC Nov 2007)
8. Design a negative edge triggered T flip flop. The circuit has two inputs, T(toggle)
and C(clock) and output Q and Q. The output state is complemented if T=1 and
the clock C changes from 1 to 0. Otherwise under any other input condition, the
output Q remains unchanged
(EC May 2006)
9. Explain the various steps in the analysis of synchronous sequential circuits
with suitable example.
10. (i) Explain the function of a universal shift register.
(EC Nov 2007)
(EI May 2009)
(ii) Explain the function of Ring counter
11. (i) Compare Synchronous and Asynchronous sequential circuits. (4) (EI May’10)
(ii) Design and explain the operation of a four bit synchronous Binary Counter. (12)
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12. Design a sequential circuit for a state diagram shown in the following figure. Use
state assignment rules for assigning states and compare the required
combinational circuit with straight binary assignment.
(EI May’10)
13. Discuss the working of a serial in parallel out 4 bit shift register with an example
and a timing diagram.
(EI May’11)
14. Explain the working of :
(EI May’11)
(i)
Up down counter
(ii)
Johnson counter
15. (i) Explain the Johnson counter (4 bit) with neat timing diagram. (10)
(ii).Realize SR flip-flop using D flip-flop (6) (EI May/June 2013)
16. Design a 4 bit up/down ripple counter with a control for up/down counting.
(EIMay/June 2013)
17. (i) Draw and explain the working of 4 bit up/down synchronous counter.(12)
(ii).Give the excitation table for T flip flop (4) (EI Nov/Dec 2013)
18. (i)Design a synchronous counter with states 0,1,2,3,4,5,0,1,2,3,4,5,…. using JK
flip flop (12)
(ii) Explain the concept of Bidirectional shift register(4) (EI Nov/Dec 2013)
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UNIT IV
1. Design an asynchronous sequential circuit that has 2 inputs X1 and X2 and one output
Z. when X1=0, Output Z=0. The first change in X2 that occurs while X1 is 1 will cause
Output Z to be 1. The Output Z will remain 1 until X1 returns to 0.
(EI May 2007)
2. Illustrate the Design procedure for Asynchronous sequential circuit with an example.
(EI Nov 2007)
3. i. Explain the principle of eliminating race condition in an Asynchronous sequential
circuit.
(EI Nov 2007)
ii. Write the steps involved in the analysis of Asynchronous sequential circuit.
4. (i) Explain how hazard free realisation can be obtained for a Boolean
function.
(iii)
(EC May 2007)
Discuss a method used for race free assignments with example.
5. (i) Write short notes on races and cycles that occur in fundamental mode circuits.
(ii) What is an essential hazard? Explain with example. (6)
(EC May 2007)
(ii) Implement the switching function f(x1 x2 x3) = x1 x2' + x2 x3 by a static hazard
free 2 level AND-OR gate network
(EC Nov 2007).
6. (i) Explain the primitive flow table and the reduction method. (8)
(ii) Discuss about Races and Cycles.
(EI May 2009)
7. Discuss in detail the Hazards and Hazard elimination.
8. An asynchronous sequential circuit is described by the following excitation and
output function.
(EI May’10)
Y=X1X2+(X1+X2)Y
Z=Y
(i) Draw the logic diagram of the circuit. (4)
(ii) Derive the transition table and output map. (8)
(iv)
Describe the behaviour of the circuit.
12. An asynchronous sequential circuit has two internal states and one output. The
excitation and output function describing the circuit are as follows.
(EI May’10)
Y1= x1x2+x1y2+x2y1
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Y2=x2+x1y1y2+x1y1
Z=x2+y1
(i) Draw the logic diagram of the circuit. (4)
(ii) Derive the transition table and the output map. (8)
(iii) Describe the behavior of the circuit. (4)
13. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one
output Z. When X1=0, the output is 0. The first change in X2 that occurs while X1 is 1
will cause the output Z to be 1. He output Z will remain 1 until X1 returns to 0.
(EI Nov’11)/ (EIMay/June 2013)
14. Design a pulse model circuit having two inputs x1 and x2 and one output z. The circuit
should produce an output pulse to coincide with the last input pulse in the sequence
x1,x2,x3.No other input sequence should produce an output pulse. (EI May/June 2013)
15. (i) Design a T flip flop from logic gates (16) (EI May/June 2013
16. (i)An asynchronous sequential circuit is described by the following excitation and
output function.
Y=x1x2+(x1+x2)y
Z=y
1. Draw the logical diagram of the circuit
2. Derive the transition table and output map.
3. Describe the behavior of the circuit
(10) (EI Nov/Dec 2013)
(ii)Write notes on shared row state assignment and
one hot state assignment (6) (EI Nov/Dec 2013)
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UNIT V
1. (i) Explain about memory decoding.
(EI May 2007)
(iii)Write a short note on FPGA.
2. (i) Explain the working of 2 input CMOS NAND gate
(EI May 2007)
(ii) Compare the performance of various logic families.
3. Write short notes on FPGA and EPROM
(EI Nov 2007)
4. i. Write about detailed comparisons of TTL, ECL and CMOS.
(EI Nov 2007)
ii. Draw and explain the circuit diagram of CMOS with NAND gates. (6)
5. Implement binary to excess 3 code converter using ROM.
(EC Nov 2007)
6. Design a PLA circuit for F1 = ∑m(2,4,7), F2 = ∑m(1,6,7)
(EC Nov 2007)
7. Implement binary to excess 3 code converter using ROM.
(EC Nov 2007)
8. Design a BCD to Excess-3 code converter with (i) PLA (ii) PAL devices.
9. Design a PLA circuit for F1 = ∑m(2,4,7), F2 = ∑m(1,6,7)
(EC Nov 2007).
10. Implement the given functions using PROM and PAL
(EC Nov 2007)
F1 = ∑m(0,1,3,5,7,9)
F2 = ∑m(1,2,4,7,8,10,11).
12. (i) Explain the working of a totem pole two input TTL NAND gate and analyze its
merits and drawbacks if any. (10)
(EC May 2007).
(ii) Define the terms: fan-out, noise margin, propagation delay. (6)
13. Explain the following characteristics of CMOS
(EI May’10)
(i) Operating speed
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(ii) Voltage levels and noise margin
(iii) Fan-out
(iv) Power dissipation
(v) Propagation delay
(vi) Latch up
(vii) Unused inputs
(viii) Static-charge susceptibility.
14. With an example, explain the following programmable logic devices. (EI May’10)
(i) PROM
(ii) PAL
(iii) PLA.
19. (i) Explain the working of three input TTL NAND totem pole output gate (12)
(ii)Write notes on PLA (4)
(EI May’11)
20. Explain the two input NOR gate and AND gate using transistor logic with neat
sketch. (16)
(EI Nov’11)
21. (i)Compare PROM,PLA and PAL (8)
(ii).Design a switching circuit that converts a 4-bit binary into a 4 bit gray code using
ROM array. (8)
22.(i) Explain the operation of ECL,NOR/OR gate with neat sketch (10)
(EIMay/June2013)
(ii) Write the characteristics of ECL family (6) (EI May/June 2013)
23.(i) Design a BCD to excess-3 code converter and implement using suitable PLA(10)
(ii) Give the classification of the semiconductor memory (6) (EI Nov/Dec 2013)
24. Draw and explain the circuit for tri-state TTL inverter (10)
Give the characteristics of ECl family. (6) (EI Nov/Dec 2013)
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