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TOP-DOWN TECHNIQUES (LITHOGRAPHY) FOR MAKING QUANTUM WIRES
Limin Ji, Lingyun Miao
ECE Dept., University of Rochester
NY, USA 14621
I. Introduction
This paper will mainly focus on the fabrication techniques of the quantum wire. To be specific, the
techniques introduced here are all top-down methods. Before the details of the techniques, there are
several basic questions that have to be discussed at the beginning. The first question is what is
nanotechnology?
Fig 1. A parallel-shaft speed reducer gear which is one of the
largest nanomechanical devices ever modeled in atomic detail. [1]
As it is defined in the encyclopedia, Nanotechnology is “a field of applied science and technology
covering a broad range of topics”. The major work is the control of matter on a scale smaller than 100
nanometers, by using the devices on the same length scale. This is a huge area, which includes
colloidal science, chemistry, applied physics, material science, mechanical engineering and electrical
engineering.
The stimulus for nanotechnology is due to the recovered interest in colloidal science and invention of
nano-scale analytical tools such as the atomic force microscope (AFM) and the scanning tunneling
microscope (STM). Also, the occurrence of refined processes, such as electron beam lithography and
molecular beam epitaxy, realize the deliberate manipulation of nanostructures and thus make the
observation of novel phenomena possible. It has already applied in modern use, like the design of
computer chip layouts based on surface science.
The history of nanotechnology is pretty young. The concept was first appeared in “There’s Plenty of
Room at the Bottom”, a talk given by physicist Richard Feynman at an American Physical Society
meeting at Caltech on December 29, 1959 [2]. “ Feynman described a process by which the ability to
manipulate individual atoms and molecules might be developed, using one set of precise tools to build
and operate another proportionally smaller set, so on down to the needed scale”. In 1974, Professor
Norio Taniguchi from Tokyo Science University defined the term “nanotechnology in a paper with
title “On the Basic Concept of ‘Nano-Technology”. He defined the term as “mainly consists of the
processing of, separation, consolidation, and deformation of materials by one atom or one molecule”.
In 1980s’, Dr. K. Eric Drexler completed the definition of nanotechnology through his speeches and
books by elevating the technological significance of nano-scale phenomena and devices. Here comes
the second question, why does nanotechnology so important?
First of all, nanotechnology is essential to the technology involved in developing the next generation
of electronics; besides, it have already done much for science. The famous Moore’s law predicted that
computer power will double every 18 months. However, it will probably end between 2010 and 2020
[3]. Since electronics is a $200 billion/year industry, it is crucial “where it will go and how the
Moore’s Law curve can be prolonged” [3]. Nanotechnology might be the solution. As it is predicted
by the Semiconductor Industry Association, dimension of the extending current technology will be
reduced to 50*50 nm till 2010. One example is the Pentium chip. It now contains 40 million
transistors and will increase up to 1.5 billion in ten years. Its dimension will reduce to 10*10 cm with
a clock speed of 10 GHz and power consumption 175 watts. By then, lithography will be reaching the
physical limits. A possible future way is making transistors from individual molecules and then be
‘sprinkled’ onto a pre-prepared surface [3]. Now we face the third question, how far has it gone so far?
Mihail Roco from U.S. National nanotechnology Initiative stated four generations of nanotechnology
as shown below:
Fig. 2. Four generations of nanotechnology. [1]
As Roco’s statement, we just entered the third generation of nanotechnology, which are the systems of
nanosystems. In the current generation, nanotechnology will have dramatic impact on almost all
industries and all areas of society. It is also predicted that nanotechnology would be able to provide
better built, longer lasting, cleaner, safer and smarter products for the home, for communications, for
medicine, for transportation, for agriculture and for industry in the near future. Quantum Wire, which
is one of the basic products, plays a key role in this area. In next section, we will focus back to the
topic, the quantum wire and its fabrication technologies. Some background information about the
quantum wire will be provided.
II. Background
In Science and Technology Dictionary, Quantum Wire (QWR) is defined as “a strip of conducting
material about 10 nanometers or less in width and thickness that displays quantum-mechanical effects
such as the Aharanov-Bohm effect and universal conductance fluctuations”. The basic difference
between quantum wire and the classical wire is that quantum information cannot be copied; instead, it
must be “transported-destroying the information at the source and re-creating it at the destination” [4].
Inside quantum wire, “electrons are confined to a narrow one dimensional channel with motion
perpendicular to the channel quantum mechanically frozen out” [5]. Modern semiconductor
technologies could be applied here to fabricate the wires, like electron beam lithography and cleaved
edge overgrowth. Further more, carbon nanotubes are “self assembled” quantum wires, which has
fascinating electronic properties, light weight, small diameter, low chemical reactivity and high tensile
strength. The main drawback is the cost. Fig. 3 shows an illustration of carbon nanotube and Fig. 4 is
the actual image.
Fig. 3. Illustration of carbon nanotube from www.spacedaily.com/news/nanotech-05zn.html.
Fig. 4. A carbon nanotube between two electrodes from http://www.mb.tn.tudelft.nl.
There are two approaches to produce quantum wire structures, top-down and bottom-up. Roughly
speaking, the former could be regarded as modern analogues of ancient methods which develop
features down to the sub-100 nm scale. The realization of this type based on the invention of electronbeam writing and advanced lithographic techniques that adopt extreme ultraviolet or hard X-ray
radiation [6]. On the contrary, bottom-up methods begin with atoms or molecules to build up
nanostructures, in some cases through smart use of self-organization. Fig. 5 shows the difference of
those two approaches. In the rest of this section, we will shortly introduce bottom-up methods and
then focus on three different types of top-down methods. The specific techniques will be explained in
the third part, the main part of this paper.
Fig. 5 Two approaches to control matter at the nanoscale. [6]
For the bottom-up methods, they compile atoms and molecules into the smallest nano-structures with
typical dimensions of 2 to 10 nm through carefully controlled chemical reactions, which makes this
kind of methods less expensive as the lithographical methods [6]. Sometimes, self-assembling of
atoms and molecules is applied to achieve complex structures. However, it is restricted to relatively
simple systems. In order to get complex systems, hierarchical self-assembly is applied where “the
products of one self-assembly step is a base for the next one” [7]. In addition, biologically inspired
self-assembly is playing an important role in nanotechnology. For example, the formation of peptide
nanotubes uses biological self-assembling of cylindrical octapeptides as ion channels. Also, the
regular and natural nanochannel formation of zeolites could be applied to study dynamical behavior of
water adsorbed in bikitaite or for the synthesis of novel materials [7]. In conclusion, the bottom-up
methods mainly use naturally formed and rather well-defined structures. As a result, they could not
generate designed, interconnected patterns as the produced nanostructures are randomly positioned.
Therefore, top-down techniques are required in the manufacturing of longer, better controlled and
interconnected structures.
Top-down technologies could be divided into three categories based on the analogy with
micromachining: bulk-/film-machining, surface-machining and mold-machining.
In bulk-/film-machining, two ways are applied to make the channel; one is etching trenches in the
substrate wafer and the other is doing in the film deposited on the substrate. Usually standard
photolithography is applied here and then wet or dry etching is processed on the substrate “in the case
of substrate etching and usually chemical etching of the film in the alternative approach” [7]. To close
the formed structure, another wafer is bonded on top of the structured substrate or film as shown in
Fig. 6.
Fig. 6 Bulk-/film-machining [7]
In surface-machining, first step is putting a bottom layer on the wafer then depositing the sacrificial
layer and its patterning. After that, the top layer is deposited on top of the sacrificial layer and
patterned (often with irrigation holes, which provide the access to the sacrificial layer. Finally, the
nanochannel is formed by removing, i.e., etching the sacrificial layer leaving the bottom and the top
layer to form the walls of the nanochannel. The bottom layer, used to form the channel of one material
(the same material as the top layer), is not always required. Isotropic sacrificial etching is crucial in
nanotechnology because the nanostructures are very sensitive. Dry etching is preferred here since “the
nanostructures can be damaged during wet etching by the drag forces during wafer handling and the
possibility of sticking of nanostructures during drying” [7]. Furthermore, advantages of this method
are presented by the uniformity of the channel height and insensitivity to particles, which would
disrupt bonding.
Fig. 7 Surface-machining [7]
In mold-machining, the mold in the inverse shape of the desired structure is formed first by being
filled with a structural material. Then the mold can be etched or removed leaving the desired structure
behind. It is usually achieved by soft lithography. In soft lithography, photolithography or electronbeam lithography (EBL) is used to produce a pattern in a layer of photoresist on the surface of the
silicon wafer to make the mold. Then the mold will be covered by a liquid precursor to polydimenthylsiloxane (PDMS) and cured into the rubbery solid. The PDMS stamp is then peeled off the
master and further used in different ways to make nanostructures. The process is shown in Fig. 8 as
below.
Fig. 8 Mold-machining with soft lithography [7]
There are several other ways to classify those lithography methods but we have no space to discuss
them all. However, we did selected 4 typical technologies to discuss in the following sections with
very detailed information, beginning with the introduction of lithography history in section three.
III. Lithography Techniques Overview
Generally speaking, lithography can be any technique which can be used to print on a
smooth surface. There have been quite a lot of techniques falling into this category since
the original invention by Alois Senefelder in 1798. However, unless specially specified,
today it usually refers to photolithography, a micro-fabrication technique used to make
Ultra Large Scale Integrated (ULSI) circuits and micro-electro-mechanical systems
(MEMS).
Photolithography generally uses a pre-fabricated photomask or reticle as a master from
which the final pattern is derived. It has been widely regarded as the cornerstone of
modern semiconductor industry. However, traditional photolithography meets its
resolution limit and other difficulties when the semiconductor pattern feature size
approaches the nanometer region. There are two endeavors dedicated to solve this
problem. First, considerable research has been done to save this most commercially
advanced lithography technology by extending its resolution into sub-100 nm range.
Second, other lithography techniques have been proposed and developed over the last
decade. As a consequence, a large number of promising microlithographic and
nanolithographic technologies exist or are emerging, including electron beam lithography
(EBL), nanoimprint lithography (NIL), interferometric lithography (IL), X-ray
lithography, extreme ultraviolet lithography (EUVL), and scanning probe lithography
(SPL). Some of these techniques have been used successfully in small-scale commercial
and important research applications. Some, for example EBL, are even capable of much
higher patterning resolution (sometime as small as a few nanometers).
In this documentation, we will first discuss several tricks implemented in traditional
photolithography to make this “old” technique suitable for semiconductor quantum wire
fabrication. Then EBL, NIL, and SPL are selected to be reviewed because of their
representative properties and the length limit of this article.
IV. Traditional Photolithography with Smart Tricks
V-groove heterostructure patterning
As early as in 1987 a heterostructure patterning technique was reported [8], which
resulted in near-ideal quantum wire interfaces suitable for stimulated emission from 2-D
quantum-confined carriers at room temperature [9]. In this method, V-grooves are first
formed on a (100) GaAs substrate. These V-grooves are oriented along the [01 ¯1]
direction using conventional photolithography and wet chemical etching. Multiple-layer
heterostructure is grown on the patterned substrate (Fig.9 (a)). Since the AlGaAs cladding
layers grow to form a very sharp corner between two {111} crystal planes. The active
GaAs quantum well (QW) grows faster along the [100] direction, which results in the
formation of a crescent-shaped QW at the bottom of the groove (Fig.9 (b)). The lateral
tapering in the thickness of the QW crescent provides lateral variation in the effective
band gap due to the increase in the carrier confinement energy with decreasing QW
thickness [8]. This results in a 2D potential well which confines the electrons and holes to
a quasi-1D quantum wire [9].
Fig.9 Cross section of GaAs/AlGaAs quantum wire heterostructure.
(a) Schematic illustration, (b) dark-field TEM (After Ref. [9])
Quantum wire lasers fabricated using this technique have been demonstrated successfully
(Fig.10) [10]. However, this fabrication method has limited application because of the
non-planar nature of the processing.
Fig.10 Light vs. current characteristics of a quantum
wire laser with 350 μm cavity length (After Ref. [10])
Double patterning
One of the most common types of double patterning is double-exposure patterning. This
technique uses the precise control (at the order of nanometers) of the actual mask position
by piezoelectric elements implemented in advanced steppers [11]. It can be employed to
efficiently reduce the minimum feature sizes in periodic structures. In this method, the
photoresist is exposed a first time with a reduced exposure dose (about 60-80 % of single
exposure). Then, the photomask is shifted a certain defined amount (20-30 nm) and the
sample is exposed a second time with the same reduced dose. Such a process is only
possible if the stepper can have a nanometric control of its reticle movement.
Accordingly, the resist feature size is, to first order, determined by the overlap of the
masked regions and arbitrarily small resist feature sizes can be produced by this method.
Such technique described above is only suitable to fabricate periodic quantum wires since
the whole mask is shifted during the photolithography process. However, this idea can be
extended to product any features by using two different photomasks, while the overlap of
these two is identical to the patterns. The added cost is an additional photomask. This
technique allows manufacturability of minimum pitch features in a layout but it cannot
improve the minimum resolution limit.
There are several other types of double patterning: spacer mask, heterogeneous mask, and
intermediate pattern accumulation. It is expected that with appropriate iterations of
double patterning techniques multiple patterning may be achieved.
There are several concerns about double patterning. First, the tool throughput is reduced
by two, since the same pattern will require two passes to get printed in full. Second,
overlay error is a more significant concern, since the positioning of a second feature
relative to a first determines the spacing size. A third concern is increased cost due to
higher consumption of materials and tool time, as well as new processes required for
double patterning. However, double patterning can actually allow for some mask cost
reduction (no need for phase-shift masks or EUV multilayers) as well as capital
expenditure reduction (tool re-use). Due to this ability to use coarse patterns to define
finer patterns, it offers an immediate opportunity to achieve features below 30 nm
without the need to address the technical challenges of expensive current or nextgeneration lithography technologies.
Immersion lithography
Immersion lithography is a photolithography resolution enhancement technique that
replaces the usual air gap between the final lens and the wafer surface with a liquid
medium that has a refractive index greater than one. The resolution is reduced by a factor
equal to the refractive index of the liquid. Current immersion lithography tools use highly
purified water for this liquid, achieving feature sizes below 45 nanometers. The optical
mechanism behind this technology is described below.
The two fundamental relationships describing a lithography imaging system, resolution
(RES) and depth of focus (DOF), are given by [12]
RES = k1 λ / NA
(1)
DOF = k2 λ / (NA)2
(2)
and
Where λ is the wavelength of the radiation used for imaging and NA is the numerical
aperture of the lens. The parameters k1 and k2 are empirically determined and correspond
to those values that yield the desired critical dimension (CD) control within an acceptable
IC manufacturing process window. Values for k1 and k2 of 0.6 and greater have been
used in high volume manufacturing. However, a given lithographic technology can be
extended further for smaller values for k1 by optimizing the IC fabrication process at the
cost of tighter process control. Setting k1 and k2 equal to 0.5 corresponds to the theoretical
values (Rayleigh criteria) for resolution and DOF.
According to equation (1), minimum feature sizes can be increased by decreasing the
wavelength, and increasing the numerical aperture (the ability of the reduction lens
system to capture enough diffraction orders from the illuminated mask). Current state-ofthe-art photolithography tools use deep ultraviolet (DUV) light with wavelengths of 248
and 193 nm, which allow minimum feature sizes down to 50 nm. By inserting a liquid
medium that has a refractive index greater than one, NA can be increased resulting in
enhanced resolution. However, the depth of focus restricts the thickness of the photoresist
and the depth of the topography on the wafer. According to equation (2), reduced NA
leads to reduced DOF. To maintain suitable DOF, parameter k2 must be tuned
accordingly to compensate for DOF.
Experiments with cesium sulfate, which mixes readily with water, show that it can
produce a liquid with a refraction index of 1.6. Combined with a high NA of 1.05 and a
193 nm DUV, such a property could allow an immersion-based linewidth as small as 30
nm.
According to the news in 2007, many companies, including IBM, UMC, Toshiba, and TI
are ramping for the 45 nm node using immersion lithography. AMD will be using
immersion lithography for its 45 nm node technology in 2008. For the 32 nm node in
2009, Intel will be using immersion lithography as well. Since typically a new technology
will need to be used over two to three nodes to spread out the cost of ownership, it is
likely that it will be extended to the 16 nm node in 2015.
Enhancements necessary to extend immersion lithography beyond the 32 nm node are
currently being investigated. Such enhancements include the use of higher refractiveindex materials in the final lens, immersion fluid, and photoresist, in order to improve the
resolution with single patterning. Currently, the most promising high-index lens material
is lutetium aluminum garnet, with a refractive index of 2.14. High-index immersion
fluids are approaching refractive index values of 1.7. These new developments allow the
optical resolution to approach ~30 nm. However, it is expected that at some point below
40 nm, current photoresists will limit further scaling [13]. Hence, new photoresists will
need to be developed for sub-40 nm applications.
As discussed in the previous section, double patterning has received interest recently
since it can potentially increase the half-pitch resolution by a factor of 2. By combining
double patterning and immersion lithography, it is possible to reach linewidth beyond 30
nm, potentially to 16 nm. In 2006, features less than 30 nm were demonstrated by IBM
using this technique [14].
V. Electron Bean Lithography (EBL)
Electron beam lithography as it is usually practiced is a form of maskless lithography, in
that no mask is required to generate the final pattern. Instead the final pattern is created
directly from a digital representation on a computer, by controlling an electron beam as it
scans across a resist-coated substrate.
A typical EBL system consists of the following parts: 1) an electron gun or electron
source that supplies the electrons; 2) an electron column that 'shapes' and focuses the
electron beam; 3) a mechanical stage that positions the wafer under the electron beam; 4)
a wafer handling system that automatically feeds wafers to the system and unloads them
after processing; and 5) a computer system that controls the equipment.
The primary advantage of this technique is that it is one of the ways to beat the
diffraction limit of light and make features on the order of 10 nm or smaller. These
smallest features are generally isolated features. Nested feature resolution is harder to
control. For most resists, it is difficult to go below 25 nm lines and spaces, and a limit of
20 nm has been found [15].
The electron Beam widths may be on the order of nanometers as of the year 2005.
However, the practical resolution limit is determined not by the beam size but by forward
scattering in the photoresist and secondary electron travel in the photoresist [16]. The
forward scattering can be decreased by using higher energy electrons or thinner
photoresist, but the generation of secondary electrons is inevitable. The travel distance of
secondary electrons is not a fundamentally derived physical value, but a statistical
parameter often determined from many experiments or Monte Carlo simulations down to
< 1 eV. This is necessary since the energy distribution of secondary electrons peaks well
below 10 eV [17]. Hence, the resolution limit is not usually cited as a well-fixed number
as with an optical diffraction-limited system [16]. Repeatability and control at the
practical resolution limit often require considerations not related to image formation, such
as photoresist development and intermolecular forces.
In addition to secondary electrons, primary electrons from the incident beam with
sufficient energy to penetrate the photoresist can be multiply scattered over large
distances from underlying films and/or the substrate. This leads to exposure of areas at a
significant distance from the desired exposure location. These electrons are called
backscattered electrons and have the same effect as long-range flare in optical projection
systems. Backscattering limits the resolution and contrast of EBL [18, 19]. A large
enough dose of backscattered electrons can even lead to complete removal of photoresist
in the desired pattern area.
Although EBL is capable for quantum wires fabrication, the use of electron beams is
costly and slow and therefore impractical for large-scale manufacturing. The beam must
be scanned across the surface to be patterned (pattern generation is serial). This makes for
very slow pattern generation compared with a parallel technique like photolithography
(the current standard) in which the entire surface is patterned at once. As an example, to
pattern a single layer of semiconductor containing 60 devices (each device consists of
many layers) it would take an electron beam system approximately two hours; compared
with less than two minutes for an optical system.
However, EBL is commercially important, primarily for its use in the manufacture of
photomasks to be used with conventional photolithography. When it is more costeffective to avoid the use of masks (in the case of low volume production or prototyping),
electron-beam direct writing is also used.
VI. Nanoimprint Lithography (NIL)
Nanoimprint lithography is a novel method of fabricating nanometer scale patterns. It is a
simple process with low cost, high throughput and high resolution. It creates patterns by
mechanical deformation of imprint resist and subsequent processes. The imprint resist is
typically a monomer or polymer formulation that is cured by heat or UV light during the
imprinting. Adhesion between the resist and the template is controlled to allow proper
release. At this point, nanoimprint lithography has been added to the International
Technology Roadmap for Semiconductors (ITRS) for the 32 nm node.
There are many different types of Nanoimprint Lithography, but two of them are most
important: Thermoplastic Nanoimprint lithography (T-NIL) and Photo Nanoimprint
Lithography (P-NIL).
T-NIL is the earliest nanoimprint lithography developed by Professor Stephen Y. Chou's
group, the original inventors of NIL [20]. In a standard T-NIL process, a thin layer of
imprint resist (thermoplastic polymer) is spin coated onto the sample substrate. Then the
mold, which has predefined topological patterns, is brought into contact with the sample
and they are pressed together under certain pressure. When heated up above the glass
transition temperature of the polymer, the pattern on the mold is pressed into the melt
polymer film. After being cooled down, the mold is separated from the sample and the
pattern resist is left on the substrate. A pattern transfer process (Reactive Ion Etching,
normally) can be used to transfer the pattern in the resist to the underneath substrate
(Fig.1).
Fig.11 Thermoplastic Nanoimprint lithography (T-NIL). (After Ref. [7])
In P-NIL, a photo (UV) curable liquid resist is applied to the sample substrate and the
mold is normally made of transparent material like fused silica. After the mold and the
substrate are pressed together, the resist is cured in UV light and becomes solid. After
mold separation, a similar pattern transfer process can be used to transfer the pattern in
resist onto the underneath material.
Nanoimprint can be performed in a way similar to the step and repeat optical lithography.
The imprint field (mold) is typically much smaller than the full wafer nanoimprint field.
The mold is repeatedly imprinted to the substrate with certain step size. This scheme is
good for nanoimprint mold creation. It is currently limited by the throughput, alignment
and street width issues.
A key benefit of NIL is its sheer simplicity. The single greatest cost associated with chip
fabrication is photolithography tool used to print the circuit patterns. As we have seen
before, photolithography requires high powered excimer lasers and immense stacks of
precision ground lens elements to achieve nanometer scale resolution. There is no need
for complex optics or high-energy radiation sources with a nanoimprint tool. There is no
need for finely tailored photoresists designed for both resolution and sensitivity at a given
wavelength. The simplified requirements of the technology lead to its low cost.
The key concerns for NIL are overlay, defects, and template patterning. Due to the direct
contact involved, the potential for error in overlay and potential for defects are magnified
compared to cases where the image is projected from a distance. These can be mitigated
with the use of effective step-and-imprint and template cleaning strategies, respectively.
The current overlay 3 sigma capability is 10 nm (source). As with immersion lithography,
defect control is expected to improve as the technology matures. The template patterning
can currently be performed by electron beam lithography or focused ion beam patterning;
however at the smallest resolution, the throughput is very slow. As a result, optical
patterning tools will be more helpful if they have sufficient resolution. Optical patterning
tools are already in use for the manufacturing of photomasks. Contact lithography or
interference lithography may also be used. In the end, resolution will not be a critical
factor in template generation, as a fine-resolution template (e.g., dense collection of
trenches) can be formed using multiple coarse-resolution templates (e.g. a set of loosely
spaced protrusions). This would lighten the burden of template generation and inspection.
A key characteristic of nanoimprint lithography is the residual layer following the imprint
process. It is preferable to have thick enough residual layers to support alignment and
throughput and low defects [21]. However, this renders the nanoimprint lithography step
less critical for critical dimension (CD) control than the etch step used to remove the
residual layer. Hence, it is important to consider the residual layer removal an integrated
part of the overall nanoimprint patterning process. In a sense, the residual layer etch is
similar to the develop process in conventional photolithography. It has been proposed to
combine contact lithography and nanoimprint lithography techniques in one step in order
to eliminate the residual layer [22].
NIL has also certain limitations in replicating large-scale (in micrometers range or larger)
and nanoscale patterns simultaneously. A novel lithographic technique that integrates
photolithography into the NIL patterning process is reported [23], successfully
overcoming the NIL limitations. This technique employs a hybrid mask-mold that has
large metal pads embedded in a transparent NIL mold. This hybrid mold allows the
patterning of large-scale and sub-micron feature size structures in one step. Therefore this
technique has a future in fabrication of a wide range of nanoscale electronics, photonics
and biological devices where patterns of various sizes are needed.
In summary, NIL is a simple pattern transfer process that is neither limited by diffraction
nor scattering effects nor secondary electrons, and does not require any sophisticated
radiation chemistry. It is also a potentially simple and inexpensive technique for many
applications including quantum wires fabrication. However, a lingering barrier to
nanometer-scale patterning is the current reliance on other lithography techniques to
generate the template. It is possible that self-assembled structures will provide the
ultimate solution for templates of periodic patterns at scales of 10 nm and less [24].
VII. Scanning-probe-microscopy (SPM) based Lithography
SPM-based lithography is a suitable technique for the high accuracy and resolution
provided by scanning microscope systems. Processes such as resist exposure [25],
mechanical modification [26], thermo-mechanical writing [27], and mask patterning [28]
have been realized on a variety of substrates. These field-assisted techniques, i.e. the
local oxidation induced by SPM probes, seem to be quite promising to achieve a fine
patterning resolution [29, 30]. Through local oxidation of metals, metal masks can be
easily fabricated, which can be used to pattern a variety of substrates.
The general feature of SPM induced local oxidation is the formation of a protruding
oxide when a negatively biased probe is moved in the near proximity of the sample
surface in ambient air. A water layer provided by the environment acts as the electrolyte
in an anodization process where OH - ions diffuse into the material. There are available
scanning-probe techniques such as Atomic Force Microscopy (AFM) and Scanning
Tunneling Microscopy (STM) for this purpose.
An AFM-based technique is reported to fabricate Si/SiGe quantum wires with sub-100
nm patterning capabilities [31]. The authors used an AFM in the contact-mode operating
in air without a local humidity control: the field-assisted oxidation was made in a clean
room with a relative humidity of about 60%. Commercial n+ doped silicon probes are
used for both processing and imaging. The Si tip suffers oxidation itself and results in an
increase in the line width and a decreasing anodization efficiency. It was found that a 15nm Cr/Au coating is effective in improving the oxidation efficiency. Moreover, the lower
voltages required as compared with the uncoated probes ensures that the probe lifetime is
increased. A large number of lines with a total length of several millimeters can be
patterned without relevant changes in the process.
The local oxidation is basically controlled by two parameters: the translation rate and the
applied voltage. In Ref. [31] they are about 1 μm/s and in the range -5 to -12V,
respectively. In fact, the oxidation depth and the line width can be affected by several
other parameters (humidity, tip shape, characteristics of the substrate, and cleanliness of
the surface). There is much work to be done in order to control these parameters
optimally.
Aluminium is commonly used as the masking metal because of its good anodization
efficiency and compatibility with MOS technique. Aluminium films can be deposited by
DC sputtering technique. Samples must be cleaned by removing the surface oxide. A well
known Al2O3 etching solution (CrO3 :H3PO4 :H2O) can be used at 40 °C for 1 min [32].
Fig.12 Topography of aluminium oxide lines (a) before and (b) after oxide removal together
with a section profile (c). Lines are patterned with increasing voltage applied. (After Ref.[31])
Fig.12 shows both the topographic view and the profile of the aluminium patterns
obtained. The aluminium film thickness is 9 nm. The translation rate is 1μm/s and the
applied voltage ranges from -5 to -8V. Commercial silicon probes with apex curvature
radius of about 10 nm are used. The whole Al thickness could be oxidized at an applied
voltage of -7V under these experimental conditions [31].
By using this technique, aluminium-based masks for pattern transfer can be fabricated as
illustrated in Fig.13. It can be seen that both “positive” (Fig.2(a,b)) and “negative”
(Fig.2(a,d)) masks can be obtained by selectively removing the oxidized area and
aluminium, respectively.
Fig.13 Schematic of the mask fabrication and etching to produce quantum
wires. (a) Starting from a patterned aluminium film a (b) “positive” or (d)
“negative” mask is produced by selective wet etching. Reactive ion etching
(c, e) is used to transfer the mask pattern onto the substrate. (After Ref.[31])
As an example, quantum wires fabricated on Si/SiGe are shown in Fig.14. The 45 nm
Si/SiGe bilayer is etched using Reactive Ion Etching (RIE) with an SF6 :O2 30:10 sccm
mixture at a pressure of 40 mTorr and a power density of 0.1 W/cm2 [31]. The “positive”
mask consisted of Al lines can transfer patterns into the substrate with a minimum line
width of about 60 nm (Fig.3 (a)). The “negative” mask consisted of Al2O3 lines can
transfer patterns into the substrate with line widths down to 90 nm (Fig.3 (b)).
Fig.14 Topography of wires fabricated using the (a) “positive” and (b) “negative” mask on a SiGe
substrate. A minimum width down to (a) 60 nm and (b) 90 nm, respectively, is obtained. (After Ref.[31])
However, it is noticeable that a not perfect homogeneity of the line width exists in Fig.3
(a). This is mainly due to the granular composition of the aluminium film, which could
represent a limit for the resolution of this fabrication technique. Patterns transferred by
“negative” masks have a more uniform width (Fig.3 (b)), but the minimum line width is
30 nm wider.
Nonetheless, SPM-based lithography is a flexible and accurate quantum wire fabrication
technique for research such as investigation of one-dimensional transport properties in
wire-based devices. Future work needs to be done to further optimize this technique.
Recently, scanning probe techniques have been proposed for ultimate resolution through
direct modifications of semiconductors, i.e. by moving individual nanoparticles or even
atoms or molecules and arranging them in patterns [33, 34]. Rings and wires built in this
way can be of one atom width. But these techniques are too slow for mass volume
fabrication [35]. Even for research purpose, they are not as versatile as SPM-based
lithography unless ultimate resolution is required.
VIII. Future Work
As it is already mentioned in the last part of Introduction, we are currently at the beginning of the 3rd
generation of nanotechnologies. There is still much work to be done in this generation, like featuring
nanosystems with thousands of interacting components [1]. We believe that these lithography
technology features, combined with the ability to “produce high-density structures in a fast and
parallel fashion”, are basic requirements for any technology which wants to fit the quest for further
miniaturization in tomorrow’s microelectronics industry and elsewhere [6]. Later in the 4th generation,
we could probably welcome the first integrated nanosystems with functions much like a mammalian
cell with hierarchical systems within systems [1]. For example, the combination of top-down and
bottom-up technologies would possibly bring fantastic revolution in nanotechnology world, like the
incorporation of nanostructures into more complex organized architectures and their effective
interfacing to the macroscopic world, which is vital for any applications. This general approach should
also result in new materials and devices that might find use beyond the applications traditionally
targeted by miniaturization efforts, particularly when it is guided by new insights into the physics of
small systems or combined with chemical and biological bottom-up methods [6].
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