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Design and Simulation of a High Bandwidth Current-toVoltage Buffer for Analog Sampling
Andrew Floren
Abstract- The buffer is a simple current to
voltage buffer designed in a 0.13um CMOS
process. It is intended to sit between a microchannel plate and a switched capacitor array
for analog sampling. It has differential inputs
and a single-ended output; in unity gain
configuration it achieves a -3dB cutoff at 1.65
GHz in pre-layout simulation when driving a
350 fF load.
I. Introduction
In order to achieve high precision particle time
of flight data without resorting to generally
expensive and power hungry flash ADCs,
switched capacitor arrays are becoming popular
for sampling analog signals at very high
bandwidths [1-4]. There is a growing interest in
using micro-channel plate photo-multipliers
(MCPs) for large area systems with very fast
time-of-flight [5-7]. These devices are
intrinsically very fast, with rise times on the
order of 100 ps or less [8]. From detailed
simulations, it seems possible to get resolutions
of a few picoseconds with pulse-shape
sampling [9]. In this note I describe an input
buffer design for a sampling ASIC intended for
fast timing, with a proposed sampling rate up to
40 GHz. The analog band-width of the input
buffer to the sampling chip is one of the
determining factors of the system time
resolution [9].
The ASIC, of which this buffer is a part of,
will be affixed directly to a MCP. The output
from the MCP is the input to the buffer which in
turn drives a switched capacitor array. The
switched capacitor array works by opening and
closing capacitors in a successive chain in order
to sample the input signal at some fixed time
interval. This interval is generated using an
inverter chain directly on the chip. Then the
capacitors can be digitized at much slower
speeds and transmitted from the chip for further
processing.
We are building on the experience of existing
ASICs [1-4], and are following a very similar
design, but with a higher sampling frequency.
Consequently we need a higher analog
bandwidth on the input. Our simulations have
shown that the input bandwidth is very tightly
correlated with the timing resolution of the ASIC
as a whole and continues to bring valuable
returns even over 1.5 GHz [9] for MCP signals.
Vin
Vout
Current
Amplifier
Voltage
Buffer
Fig. 1
II. Architecture
A. Current Amplifier
The input of the buffer feeds a current
amplifier in a negative-feedback unity-gain
configuration. The current amplifier has the
advantage that it decouples the -3 dB cutoff of
the buffer from the buffer’s gain configuration,
so if necessary the gain can be increased with
relatively little impact on the bandwidth of the
buffer. The disadvantages are a limited common
mode range without proper biasing and a low
input resistance.
Because the input is a current amplifier, the
buffer necessarily has a low input resistance, on
the order of 200 Ohms. Generally, a 50 Ohm
terminating resistor is placed at the input to a
high input resistance voltage buffer such that the
resistance seen from the MCP is 50 Ohms.
However in our case we want as much of the
current from the MCP to pass through the buffer
as possible; to achieve this, the sizes of the input
transistors are scaled such that the input
resistance is as close to 50 Ohms as possible.
Then a small resistor, around 67 Ohms, should
be placed between the differential lines in order
to tune the input resistance to exactly 50 Ohms.
While the common mode range of +-0.5 V is
not huge, it is large enough for the typical signals
of 10’s of mV we observe with present MCPs
operated in the range for good timing. If a
greater input voltage range is required it should
be possible to increase this number by increasing
the negative supply of the buffer and applying a
corresponding negative bias voltage to the input.
iout
-
+
III. Simulation Results
Schematics were designed and SPICE
simulations were run in Cadence [10] using the
models supplied in an IBM design kit provided
by CERN [11]. The capacitor array will use
capacitors of approximately 70 fF and due to
pulse width four of them will be open at any
given time, thus for testing purposes a capacitive
load of 350 fF was used.
Vss
Fig. 2
The self-biased cascode current-mirror
implementation of the current amplifier helps to
further decrease the input resistance of the
amplifier as well as increasing the output
resistance. This in turn increases the common
mode rejection ratio of the differential inputs.
Vdd
Fig. 4
Vin
Vout
Vss
Fig. 3
B. Voltage Buffer
The current amplifier feeds a voltage buffer
which is the output of the buffer as a whole. This
voltage buffer is an extremely simple class A
gain stage designed to reduce the output
resistance and increase the current driving
capability of the buffer. These parameters could
be further improved by using a more
sophisticated voltage buffer, however in the
interests of achieving as high a bandwidth as
possible the fewer transistors at the output of the
buffer the better.
Fig. 5
Figure 4 shows the AC response in dB and
figure 5 shows the phase. The gain is not quite
unity, and the -3 dB cutoff occurs around
1.65 GHz. There is very little peaking in the
curve which should contribute to improved
resolution. Possible instability due to phase does
not occur until well over 10 GHz so it should not
be a factor if the buffer were ever used in a nonunity-gain configuration.
Charge injection is apparent here but that can be
accounted for with a constant offset during the
reconstruction.
Fig. 8
Fig. 6
Figure 6 shows the transient analysis of the
buffer for a typical signal from the MCP. The top
signal is created from recorded data from an
MCP and the lower signal is the simulated buffer
output. The buffer is inverting, however this
should have no impact on the timing resolution,
and the sign can easily be reversed during
digitization.
Fig.7
The switched capacitor array has also been
simulated and Figure 7 shows the transient
analysis of one of the capacitors in the array.
Figure 8 shows the result of reconstructing the
signal in Matlab [12] after sampling the transient
analysis of the capacitor array during the
appropriate periods of stability. Some of the high
frequency elements have been cut out as
expected but the shape of the pulse has been very
well retained.
IV. Outlook
The initial design goal of 1 GHz analog
bandwidth has been exceeded. However all of
these
simulations
are
pre-layout
and
unfortunately this means bandwidth can only
decrease as parasitic capacitances drag it down.
Additional simulation has also shown that
even over 1.5 GHz improving the analog
bandwidth still yields significant gains in timing
resolution. A clever layout scheme may
minimize the bandwidth loss but there is no way
to avoid this loss altogether. It is possible to
improve the bandwidth by either reducing the
size of the sampling capacitors or reducing the
pulse width such that less than 4 capacitors are
open simultaneously. Both of these changes will
adversely affect sampling resolution in their own
right and the relationships must be explored to
find the optimum balance between them.
Also, because the input resistance of the buffer
cannot be made exactly 50 Ohms a resistor
placed across differential lines will be necessary
to tune it; a significant amount of power from the
input signal will be dissipated across this resistor
which will necessarily reduce the signal to noise
ratio of the final output.
While the current design may be sufficient
there is still room for improvement in both the
input bandwidth and input resistance.
[11]
Acknowledgements
[12]
The author would like to thank Henry Frisch,
Jean Francois Genat and Fukun Tang for their
help and advice during the design of this buffer.
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Cadence Design Systems, Inc., 2655
Seely Avenue, San Jose, CA, USA. The
schematics and simulation settings are
available from the author.
The IBM 130nm CMOS design kit
cmrf8sf has been provided by CERN
MathWorks, 3 Apple hill Drive, Natick,
MA, USA. The MATLAB source is
available from the author.