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Integrated CMOS 18V 240μA Charge Pump with Passive Level Shifters Vratislav MICHAL, Denis COTTIN, Nicolas MARTY and Patrik ARNO STMicroelectronics, 12 rue Jules Horowitz, Grenoble, France [email protected] Motivation – High power density Structures with low voltage vs. high voltage capacitors VIN VIN VIN 4VIN VIN VIN VIN -VIN D1 VIN CMID D1 VIN VIN VIN ① ⓫ D2 D2 D1 D1 VIN ② CMID wikipedia D2 D2 4VIN VIN Dickson charge pump with linear MOSFET in parallel with diodewired MOSFET. 4-stage (x5 multiplier) ⓬ Small area Complicated switches driving X well-known active switches structures low-denisty capacitors 2 Preferred architecture: dual phase voltage multiplier Output power is delivered by one of complementary inputs VIN Only small output capacitor (high-voltage) Small CMID filters the voltage spikes in the active structure First node delivered by the DC input voltage VIN VIN D1 VIN VIN -VIN CMID VIN D1 VIN ① D2 D2 D1 2VIN D1 ② CMID D2 D2 3VIN VIN COUT VIN ⓫ VIN ⓬ 3 Active level shifter solution Very high output voltage reached in ref [*] Active switches driving rely on the floating active level shifters High-voltage floating level shifters are difficult to design [*] A. Emiraet al. “All-pMOS 50-V charge pump using low voltage capacitors,” IEEE Tran. on ind. Electronics, Vol. 60, No. 10, 2013 4 Single cell - Diodes replacement by the active switches Complementary gate signals generated by the structure Steady-state reached by the transistor diodes Pelliconi cell 5 Final structure: Passive level shifter Passive level shifters helps the fast propagation of the driving signals Act as HP bypass for driving signal and LP link for DC voltage Fast driving signals prevent energy loss in the charge-pump structure FEEDFORWARD capacitor considerably increase the output power CAUX(1) CAUX(2) ① CAUX(2) ② ④ CAUX(3) ③ Fast edges ~5pF INΦA_AUX ~5pF R ~5pF VIN C1 INΦA ~15kΩ ~30pF C2 ~182pF ~15kΩ CFEEDFORWARD è AC FEEDFORWARD è 2·VDD_INT ~5pF ~15kΩ ~15kΩ C1 ‒ C3: 5V MIM capacitor C3 ~101pF ~34pF CFEEDFORWARD: 20V MOM capacitor 0 sub. diode ⓫ ⓭ ⓬ ⓮ sub. diode M1 CLK: 10MHz 2·VDD_INT = VIN M2 M3 M4 5·VIN QIN VOUT 18V QIN 2·VDD_INT VIN INΦB ~5pF ~5pF ② ① ③ ~101pF ~182pF 0 ~10pF ④ DC nodes: M1 : VIN M2 : 2·VIN M3 : 3·VIN M4 : 4·VIN ~34pF è AC FEEDFORWARD è R ~5pF ~5pF ~15kΩ ~30pF ~15kΩ ~15kΩ ~15kΩ INΦB_AUX Note: M1 can be external DC voltage Fast edges ~5pF ⓫ ~5pF ⓬ ~5pF ⓭ ~5pF ⓮ 6 Final structure: simulation ΦA, IOUT = 240µA VOUT 18V Internal nodes of Fig. 4 charge pump (upper phase). Lower phase is identical with 180° phase shift. The solid lines correspond to the floating nodes ① to ④ , whereas the dashed lines to the DC middle nodes M1-4. ④ ② ① M4 M3 M2 M1 ΦA, IOUT = 240µA INΦA Simulation of the internal nodes of the charge pump (upper phase) without passive level shifter (R = 0). zones of cross-conduction VOUT 18V crossconduction ④ time (s) ③ voltage (V) voltage (V) ③ M4 M3 ② M2 ① M1 INΦA time (s) 7 Capacitor Area Optimization Capacitor are dominant silicon area contributor. Capacitor distribution is not uniform across CP stages. Approximate analytical solution known in the literature. It is impossible to cover all parasitic elements in the analytical capacitor area distribution. [*] A. Emiraet al. “All-pMOS 50-V charge pump using low voltage capacitors,” IEEE Tran. on ind. Electronics, Vol. 60, No. 10, 2013 8 Capacitor Area Optimization (cont’d) Optimization target: higher output current for given capacitor area CTOT Set of equation can be written: CTANK C1 C1 C2 C2 C3 CTOT CTANK C1 C2 C3 Leading to the capacitor parameters: CTANK C2 CTOT CTOT , C1 1 1 1 1 CTOT CTOT , C3 1 1 1 1 These equations can be inserted in the capacitor value property 9 Capacitor Area Optimization results Optimization is parametric simulation, accounting for all dominant parameters of the charge pump: Target: higher output voltage for given output current: α = 1.7, β = 1.5 and γ = 2. The CP was connected in the open-loop with G_CTRL = 1V. Simulation done in the worst-case corner (CMIN, slow, 120°C with load current 260μA) 10 18V Output voltage control Output voltage control is provided via charge control of the main (input) tank capacitor. Tank capacitor is used in the input voltage doubler. Fast (low power) driver power driver +VDD_INT +VDD_INT A Q8 CMD_PMOS CLK A Q7 OUT_AUX B tnovl Q6 (~1ns) 2·VDD_INT OUT B CTANK HV MOS 0 (1) GND VDD Q4 CONTROL IN (~ 1V) Charging control G_CTRL Q5 VC(1) IC_CHARGING QCONTROLL Q TCLK 2 +VDD G_CONTROLL GND 2 W 0COX VG _ CTRL VT L 11 Conclusion - Results S N STI P-well N-well gate D N Bulk (iso) iso P N STI Isolated P-well STI sub STI N-well N ISO Psubstrate P STI Phase 1 UV photography 160nm CMOS P-well Epi P Phase 2 Epitaxial isolation trench 1.5µm High-voltage isolated NMOS with >20V breakdown voltage VDD_INT CLK CP_Φ(A) G_CTRL OUT_18V VREF 1.1V G_CTRL soft-start CP_Φ(B) CLK VDD_INT Feedback control loop 10pF/HV VBAT 2.42 – 4.8V VDD_INT 2.4V VOUT 18V Imax 280μA Fsw 10MHz COUT 10pF Iq 4.2 mA POUT/A 12.4 mW/mm2 Obtained features 12