Download Final Report for ECE 445, Senior Design, Spring 2015

High Speed Integrator for Multiple Photon Detection
By
Nathan Peterson
Jameel Showail
Anderson West
Final Report for ECE 445, Senior Design, Spring 2015
TA: Benjamin Cahill
6 May 2015
Team #36
Abstract
A new cryogenic photo detector is unique in its ability to intercept and detect multiple
photons simultaneously. The project strives to create a reliable means of quantifying the number
of incident photons. Each photon causes an analog signal roughly the same magnitude in voltage
and they can add to each other so that two photons can be represented by a narrow pulse with a
high voltage, or a wide pulse with a low peak voltage. However, the area of the signal will be the
same for both pulses. The solution is to create a fast integrating circuit to measure the total
charge and determine the number of incident photons. A two op-amp integration circuit and a
multiple op-amp analog to digital converter (ADC) design was created, which was scalable and
successfully simulated, but experienced difficulties when manufacturing the device.
ii
Table of Contents
1.0 INTRODUCTION
1.1 Statement of Purpose ....................................................................................................................... 1
1.2 Objectives ......................................................................................................................................... 1
1.2.1 Goals and Benefits ................................................................................................................... 1
1.2.2 Functions and Features ............................................................................................................ 2
2.0 DESIGN
2.1 Block Diagrams ................................................................................................................................ 3
2.2 Module Descriptions ....................................................................................................................... 3
2.2.1 Laser source .............................................................................................................................. 3
2.2.2 Single photon detector ............................................................................................................. 3
2.2.3 Integrator Circuit ...................................................................................................................... 4
2.2.4 ADC ........................................................................................................................................... 6
2.2.5 EMI Shielded Enclosure .......................................................................................................... 7
2.3 PCB Fabrication .............................................................................................................................. 9
2.3.1 PCB Design Considerations ................................................................................................... 9
2.3.2 Eagle Integrator Circuit PCB Design .................................................................................... 9
2.3.3 Eagle ADC Circuit PCB Design .......................................................................................... 10
3.0 DESIGN
3.1 Power Regulators ........................................................................................................................... 11
3.1.1 Stable and Correct Output Voltage ............................................................................................ 11
3.2 Integrator ......................................................................................................................................... 11
3.2.1 The Buffer Accurately Follows Input and Measures Proper Voltage .............................. 11
3.2.2 The Integrator Responds to Input ......................................................................................... 11
3.3 ADC ................................................................................................................................................. 12
3.3.1 Op Amps Switch at Threshold Voltage ............................................................................... 12
3.3.2 ADC Responds at Desired Frequency ................................................................................. 12
3.4 EMI Shielded Enclosure ............................................................................................................... 13
3.4.1 Resistivity ................................................................................................................................ 13
3.5 Scalable Design ............................................................................................................................. 13
3.6 Obstacles ......................................................................................................................................... 13
3.6.1 PCB Revisions ........................................................................................................................ 13
4.0 COST AND SCHEDULE
4.1 Cost Analysis .................................................................................................................................. 15
4.1.1 Labor ........................................................................................................................................ 15
4.1.2 Parts .......................................................................................................................................... 15
4.1.3 Grand Total ............................................................................................................................. 16
5.0 CONCLUSION
5.1 Accomplishments........................................................................................................................... 17
5.2 Uncertainties ................................................................................................................................... 17
5.3 Ethical Considerations................................................................................................................... 17
5.4 Future Work .................................................................................................................................... 18
References ................................................................................................................................................ 19
Appendix A: Professor Kwiat’s Challenge Information ............................................................... 20
Appendix B: Requirements and Verification Tables ..................................................................... 21
iii
1.0
Introduction
1.1
Statement of Purpose
For researchers performing quantum experiments, like Professor Kwiat from UIUC, it is
often necessary to measure not only the presence or absence of a photon, but also the total
amount of photon detections during a given interval. However, such a device, presents
challenges because of the time scales that come with photon interactions. Simultaneous or close
to simultaneous photon detections are often hard to distinguish from a single interaction. The
solution is to integrate the total charge coming off the detector as that characteristic will scale
linearly with each additional photon. Integrators that can measure such small pulse widths at
such a high frequency are not sold in industry. As a result, it is difficult to obtain accurate
research data. The high speed integrator will be able to accurately detect the number of photons
during a given time interval and allow quantum researchers to measure more accurate data. This
project was chosen to work on cutting edge technology, to solve a documented problem, and
gain real world project experience.
1.2
Objectives
1.2.1 Goals and Benefits

Achieve a data detection speed of at least 100 MHz

Achieve fault tolerance

Increase research data accuracy and the robustness of data sets

Prove useful where photon detection is beneficial in other industries such as nuclear,
medicine, and sensing as can be seen in Figure 1.
Figure 1: Photon Technology Industry Map [1]
Due to the intended laser’s maximum capabilities, this project’s goal frequency reaches a
peak frequency of 100 MHz. This high frequency increases data collection rates and the
usefulness of this product. A fault tolerant system can be handled with greater confidence in a
lab setting and thus is more convenient and reliable to use. As with most aspects of physics, the
uses of single photon detection can reach into a diverse array of fields.
1.2.2 Functions and Features

Measure pulse widths at a minimum of 1 nanosecond

Measure voltages at a minimum of 150 mV

Measure frequencies between 1 kHz to 10 MHz

Dark currents must be less than 1% of total signal

Accurately detect zero, one, or more than one photon detections during a given time
interval

Create a “black box” system with no user setup required besides entering necessary
givens

Construct and test the efficacy of an electromagnetic interference (EMI) shielded
enclosure

Effectively assimilate with other lab equipment

Scalable design allows improved components if/when better components are made
available
The specifications for pulse width and magnitude are pulled directly from Single Photon
Analyzer (Appendix A on page 20) which was received directly from Professor Kwiat.
In addition, the goal frequency as stated in section 1.2.1 is 100 MHz which was also
taken from the documentation on Appendix A. However, Kwiat and the senior design team
acknowledges that the components used are current generation Op-Amps which have come out
within the last year or two. Part of the goals of this design project is to push the device’s
envelope in order to determine its upper threshold of operational frequency. The PCB and
circuitry are designed looking forward, so that if and when better performing components come
to market they can be incorporated into the design. Finally, the project will be designed to easily
be integrated into the existing lab equipment as a “black box” for ease of use.
2
2.0
Design
The design group had two viable choices for making the project. One option involved
using multiple analog to digital converters and delaying the triggers, so as to effectively sample
at a higher rate than the ADCs would be able to do individually. The option that was ultimately
pursued involved using analog op-amps as the integration circuit with a high speed buffer opamp to supply current. This was chosen for simplicity, and because new op-amps released in the
last year are able to have slew rates high enough to accommodate the 1 ns pulse times being
measured.
2.1
Block Diagrams
Figure 2: Design Block Diagram
2.2
Module Descriptions
2.2.1 Laser source
The detection method intended is designed with a specific laser in mind, used for testing
in the physics department here at UIUC. It is designed to run off of the shared trigger along with
the integrator and analog to digital converter.
2.2.2 Single photon detector
The single photon detector operates via avalanche photodiodes [2] and outputs a pulse
with a peak of 150 mV for roughly 8 ns if one photon is detected (see Single Photon Analyzer in
Appendix A on page 20). When multiple photons are detected, the pulse width and the amplitude
3
increase. However, depending on how close a photon follows another photon incident on the
detector, this increase can vary drastically. Nevertheless, the total charge will be double
regardless of the peak amplitude of the two photon detection.
2.2.3 Integrator Circuit
The integrator circuit operates around a current generation op-amp with a frequency
response sufficient to observe the integrations of a single photon, according to the simulation. It
takes the analog signal from the single photon detector, integrates the signal, and outputs a
voltage to the ADC.
The circuit is designed around the OPA1S2384 op-amp chip by Texas Instruments (TI). It
features a built in buffer and internal switch which was assimilated into the trigger system. The
motivation for including the buffer is because the detector cannot drive a large current draw and
the integrating op-amp requires too much input current to operate. This information was
provided by Professor Cheng at UIUC. Furthermore, it exhibits a higher slew rate of 150 V/s
for fast response times, a wide bandwidth of 250 MHz, and demonstrates a fast settling time.
This product comprises everything needed for the circuit in one chip. Design recommendations
in the datasheet [3] were followed to select the 25  resistor and 10 pF capacitor. Below the
schematic for the integrating circuit can be found in Figure 3.
Figure 3: Integrator Op-Amp Schematic
In addition, the op-amp is powered with 2.5 V via a positive (TPS799) and negative
(TPS723) linear regulator. Both these linear regulators were selected to have low noise and high
stability, because the integrator op-amps are sensitive to their power sources. The 10 nF and 2.2
F capacitors were selected based on the datasheets [4][5] given by TI.
The simulation for this circuit can be seen below in Figure 4.
4
Figure 4: Op-Amp Integrator Output Waveform Simulation
Here, the red input pulses represent the analog pulse of a photon hitting the photon detector, and
the green line is the output integration. As can be seen, the step like waveform integrates the
charge of each pulse. Furthermore, the step size should be approximately the same for a 150 mV
pulse for 2 ns and a 300 mV pulse for 1 ns. This can be seen below in Figure 5 from left to right,
respectively.
Figure 5: Op-Amp Charge Integration Comparison
5
As can be seen, each of the two have the approximately the same step size, which is to be
expected.
2.2.4 ADC
The ADC is composed of two parts, a voltage input supply and a series of parallel
comparators [6]. Its purpose is to take the charge measurement obtained by the integrator circuit,
determine how many photons were actually observed, and output it as a digital signal. It is
imperative that this device is tunable, meaning the cutoffs for how many photons there are, can
be adjusted in the lab. To accomplish this, the multiple voltage supplies for the op-amps are user
tunable and will supply reference levels for the comparators. As a result, this setup provides
binning capabilities as comparators are activated at user selected voltage levels. Given the analog
signal input from the output of the integrator circuit above, the comparators will then output a 1
or 0 for a digital output if that threshold had been exceeded. Figure 6 below gives a schematic,
followed by Figure 7 for its simulation.
Figure 6: ADC Schematic
6
Figure 7: ADC Waveform Simulation
By probing the outputs of the three op-amps, the above simulation proves successful. At each of
the tuned voltage levels, here set to -.2 V, -.4 V, and -.6 V, one can see each comparator output 1,
in turn, as the dc sweep reaches each of these threshold levels, signifying 1, 2, or 3 and above
photon detections, respectfully.
2.2.5 EMI Shielded Enclosure
The Hammond shielded enclosure consists of two solid pieces of diecast aluminum alloy
that are grounded and essentially operates as a faraday cage. While its main use is to block
interference for the circuit, it also provides physical security for the electronics and a plug and
play, “black box” design for simplicity and ease of use. A mesh was considered but becomes
more permeable at higher frequencies. The pieces are fitted so as to avoid large gaps in the seams
and fasten together via four machine screws. Holes for incoming and outgoing wires will be as
small as possible. The box has three male BNC ports for the input, output, and trigger, as well as
three female banana ports for positive voltage, negative voltage, and ground. The internal PCB
will be elevated off the metal enclosure by non-conductive spacers. A visual diagram of the
enclosure can be seen below in Figure 8.
7
Figure 8: EMI Enclosure Diagram [7]
To calculate the frequency of the signals this device can block, the equation for signal
penetration depth [8] can be used
δp = .5 * δe = .5 * √(2 * ρ / ((2π * f) * μr * μ0))
(1)
where δe is the skin effect, ρ is the resistivity of the box and approximated to 4.5e-8 Ω-m, μr is
relative magnetic permeability of the box found to be 1.000022, and μ0 is the permeability of free
space equal to 4*π*10^-7 H/m. By setting the penetration depth the the minimum thickness of
the box as shown above in the diagram, the minimum frequency the enclosure can block is
136.44 Hz.
While the box can block signals going out and coming into the enclosure, further
consideration is needed for signals that become trapped in the box as a resonant cavity. To find
these frequencies, the following equation [9] can be applied
f(m,n) = 1/(2π)*c*√((n*π/a^2)+(m*π/b^2))
(2)
where c is the speed of light, a is width of the box equal to .0985 m, b is the length of the box
equal to .115 m, and m and n are integers. While m and n go to infinity, a few calculated resonant
frequencies calculated for f(m,n) are f(1,0) = .7359 GHz, f(0,1) = .9456 GHz, and f(1,1) = 1.198 GHz.
These frequencies are too large to directly conflict with this data, but once these frequencies are
calculated, they can be recognized as noise and potentially filtered out.
8
2.3 PCB Fabrication
2.3.1 PCB Design Considerations
Due to the small signals and high frequency, proper PCB design becomes critical for signal
integrity. The following are design guidelines used for PCB signal reliability advocated from
Texas Instruments [10].







To minimize the effects on crosstalk on adjacent traces, keep them at least 2 times the
trace width apart.
However, make traces reasonably wide.
A complete ground plane in high-speed design is essential
Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To
minimize any impedance change, the best routing would be a round bend.
Separate high-speed signals (e.g., clock signals) from low-speed signals and digital from
analog signals; again, placement is important.
To minimize crosstalk not only between two signals on one layer but also between
adjacent layers, route them with 90° to each other.
Minimize the use of vias. The designer has to be careful when using them. They add
additional inductance and capacitance, and reflections occur due to the change in the
characteristic impedance. Vias also increase the trace length.
Signal speed and propagation delay were found to be negligible for this small PCB,
especially compared to the long input 50  coaxial cable. The realistic signal speed, V, can be
calculated through the simple equation of
V = c / sqrt(ԐR)
(3)
where c is the speed of light in a vacuum at 3x10^8 m/s and ԐR is the effective rate which is
characteristic of the material. Assuming ԐR = 4.6 (FR4) then the speed is still 139875790 m/s and
over the span of a few linear inches on the traces, the change of time is completely negligible.
2.3.2 Eagle Integrator Circuit PCB Design
Based off the integrator schematic and PCB design considerations, the following PCB
was created via Eagle software and fabricated at the ECE Service Shop at UIUC.
9
Figure 9: Integrator PCB Design
2.3.3 Eagle ADC Circuit PCB design
In the same fashion, the ADC was made by the same supplier.
Figure 10: ADC PCB Design
10
3. Design Verification
Overall, while the circuit didn’t work in its entirety, many of the individual functions
were still tested and confirmed. Further detail into the requirements and verifications can be
found in the table in Appendix B on page 21.
3.1 Power Regulators
The circuit was supplied with voltages between ±2.0 V to 3.0 V from a dc power supply
and the output of the regulators was probed and measured on an oscilloscope.
3.1.1 Stable and Correct Output Voltage
The linear regulators were needed to maintain a stable ±2.5 V supply power to the
integrating op amp. The output was measured at ±2.49 V with a noise and variation barely
noticeable with the oscilloscope display resolution maxed out at 2 mV per division.
3.2 Integrator
Due to time restraints and lack of experience with small scale soldering, the integrating op-amp
was not able to work completely during the demonstration. Nonetheless, the circuit was shown to briefly
work and later was found to operate up until the buffer. The integrator was powered by ±2.5 V,
connected to ground, and supplied a 150 mV square input waveform from the function generator,
a trigger via a second waveform generator set to a 100 kHz square wave with an amplitude of 2.5
V. These signals were monitored with an oscilloscope.
3.2.1 The Buffer Accurately Follows Input and Measures Proper Voltage
The buffer was probed via the oscilloscope and observed to follow high frequency inputs
perfectly. It was easily able to measure voltages of 150 mV. The buffer was capable of properly
following the input signal from 1 kHz up to the maximum frequency of the function generator of
30 MHz.
3.2.2 The Integrator Responds to Input
The integrator was observed to briefly operate properly. After reheating the PCB to fix a
suspected soldering problem, the integrator circuit outputted the waveform below in Figure 11.
11
Figure 11: Output Waveform From Integrator Circuit
In the figure above, the green is the output and the yellow is the trigger. After the op amp sets up,
the output steps down in response to the input.
3.3 ADC
While the ADC circuit worked completely in testing, it was accidentally overpowered
and burned two of the op-amps just prior to demonstration. Nonetheless, the remaining op-amp
was used to demonstrate its effectiveness. The ADC was powered by a 5V power supply, the opamp reference voltage was set to 1 V, and the output of the ADC was monitored with an
oscilloscope.
3.3.1 Op Amps Switch at Threshold Voltage
The op amps were observed to switch very accurately at the set threshold voltages. It very
quickly switched from low to high voltage, corresponding to if the signal is below or above the
threshold voltage respectively.
3.3.2 ADC Responds at Desired Frequency
The op amps were observed to respond accurately with high frequency inputs. Professor
Kwiat only needs the ADC to accurately work at 1 MHz. While the photons come in quickly,
they have a longer period between excitations. The ADC responded accurately to input
frequencies up to 3 MHz.
12
3.4 EMI Shielded Enclosure
3.4.1 Resistivity
The box is a very good conductor, as the resistance across the box was measured far
below 1 Ω. The fact that it is a good conductor means that it will act well as a faraday cage.
The box was properly outfitted with the correct BNC and banana ports to seamlessly
integrate into Professor Kwiat’s existing lab setup. Once the circuit works in its entirety, it will
operate as a “black box” system.
3.5 Scalable Design
Due to the nature of the design, the device is highly scalable. If more photons wish to be
detected, simply adding additional op-amps in parallel will expand its range. If higher
frequencies wish to be analyzed, a new integrating chip can be swapped out for the current one,
just as soon as the technological advances in integrator chips come to fruition.
3.6 Obstacles
Ultimately, these failures largely trace back to PCB design and soldering. It was realized
the Eagle PCB was designed to be machine soldered and the team had little to no experience
with small scale surface mount soldering. Experts in the ECE Service Shop were consulted and
PCB design revision parameters were organized.
3.6.1 PCB Revisions
The revisions include:
1.
Bigger heat sink traces
2.
Extend traces (about as wide as the chip width)
3.
Lengthen semicircular trace
4.
Make a loop for adjacent connections
5.
Extend ground traces
6.
Convert mounting holes to vias
As a result, a new PCB was designed with these parameters and can be compared to the original
PCB design below in Figure 12.
13
Figure 12: Old PCB Design (Left) Vs. New PCB Design (Right)
14
4.0
Cost and Schedule
4.1
Cost Analysis
4.1.1 Labor
Table 1: Labor Breakdown
Total Hours
Invested
Total = Hourly Rate * 2.5 * Total Hours
Invested
Nathan Peterson $40
256
$25,600.00
Anders West
$40
256
$25,600.00
Jameel Showail
$40
256
$25,600.00
Total
$120
768
$76,800.00
Name
Hourly
Rate
4.1.2 Parts
Table 2: Parts Lists and Prices
Item
Quantity Cost
Texas Instruments OPA1S2384IDRCR-250-MHz, CMOS
Transimpedance Amplifier (TIA) with Integrated Switch and Buffer
1
$2.75
TPS79925QDDCRQ1 200mA, Low Quiescent Current, Ultra-Low
Noise, High PSRR Low Dropout Linear Regulator
1
$0.28
TPS72325 200mA Low-Noise, High-PSRR Negative Output LowDropout Linear Regulators
1
$1.05
Texas Instruments OPA690IDBVT, Wideband, Voltage Feedback
Operational Amplifier With Disable
3
$1.63 per
unit
5VDC Wallwart
1
$4.95
Hammond 1590BBS Enclosure
1
$10.09
Total
$24.01
15
4.1.3 Grand Total Cost
Table 3: Finalized Total Cost
Section
Total
Labor
$76,800.00
Parts
$24.01
Grand Total
$76,824.01
16
5. Conclusion
5.1 Accomplishments
Overall, while it didn’t work in its entirety, the design is still considered a viable solution to
Professor Kwiat’s problem. The simplistic plug and play box was identical to what Professor Kwiat
requested. The power has banana plug ports and the signals have BNC ports. This enables simple
integration with the rest of the equipment in the lab. The buffer component was capable of following
the input signal properly. This is a good sign as it suggests that if the second op amp was connected
correctly then it would be capable of responding to the same frequencies. Further, it was demonstrated
that the ADC could quickly and accurately respond to signals even faster than the output of the
integrator would be.
5.2 Uncertainties
It is still not completely certain that the design will work well in practice as it could not be
extensively tested. However, the brief time that the entire system was working was a very promising
indication. Unfortunately, due to time constraints only two somewhat functional PCBs were able to be
fabricated, but both failed due to soldering problems during testing as mentioned in Section 3.
5.3 Ethical Considerations
A consideration of the 10 point IEEE Code of Ethics [11] is shown below:
1. to accept responsibility in making decisions consistent with the safety, health, and welfare
of the public, and to disclose promptly factors that might endanger the public or the
environment;
The purpose of this project is to create a device to advance research pertaining to fields
benefiting mankind. Furthermore the device will be made so as to be safe for operation by all
users.
3. to be honest and realistic in stating claims or estimates based on available data;
Point number three is essentially the essence of the project. Not only is honest data reported, but
the device is used to help others in accurately reporting their own data.
5. to improve the understanding of technology; its appropriate application, and potential
consequences;
6. to maintain and improve our technical competence and to undertake technological tasks
for others only if qualified by training or experience, or after full disclosure of pertinent
limitations;
Points 5 and 6 follow point 3. The device created will allow for better research data and further
the quest for heightened learning and understanding of the universe.
17
7. to seek, accept, and offer honest criticism of technical work, to acknowledge and correct
errors, and to credit properly the contributions of others;
As this is new cutting edge technology, the work being done must be original. Plagiarism will
not be tolerated. Moreover, since it is cutting edge, criticism will be pursued and accepted as
well help from those who qualified to do so.
9. to avoid injuring others, their property, reputation, or employment by false or malicious
action;
People’s reputations will be relying on these results from the integrator. As a result, falsified data
will not be reported in these experiments bolstering accuracy claims that cannot be backed up.
10. to assist colleagues and co-workers in their professional development and to support
them in following this code of ethics.
As men of learning, the pursuit of knowledge is beneficial to all and it is an honor to assist
anyone in their lofty endeavors.
5.4 Future work
As mentioned before, while the project could not quite be tested to completion, the
testing and simulations that were performed prove promising. All research and files will be made
available to Professor Kwiat for his further use. It is recommended that these designs be sent out
to be machine assembled to eliminate small scale soldering problems and uncertainties. It is
greatly hoped that another group will continue on with this research.
18
References
[1] "Metrology of single-photon sources and detectors: a review," Christopher Chunnilall, et
al.Opt. Eng. 53(8), 081910 (Jul 10, 2014). doi:10.1117/1.OE.53.8.081910].
[2] Zielnicki, Kevin. "PURE SOURCES AND EFFICIENT DETECTORS FOR OPTICAL
QUANTUM INFORMATION PROCESSING." (n.d.): n. pag. University of Illinois at
Urbana-Champaign, 2014. Web.
<http://research.physics.illinois.edu/QI/Photonics/theses/zielnicki-thesis.pdf>.
[3] “OPA1S2384 250-MHz, CMOS Transimpedance Amplifier (TIA) with Integrated Switch
and Buffer.” Available: http://www.ti.com/lit/ds/symlink/opa1s2384.pdf. Web
[4] “TPS799 200-mA, Low-Quiescent Current, Ultralow Noise, High-PSRR Low-Dropout
Linear Regulator.” Available: http://www.ti.com/lit/ds/symlink/tps799.pdf. Web
[5] “TPS723xx 200mA Low-Noise, High-PSRR Negative Output Low-Dropout Linear
Regulators.” Available: http://www.ti.com/lit/ds/symlink/tps723.pdf. Web
[6] “OPA690 Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable.”
Available: http://www.ti.com/lit/ds/symlink/opa690.pdf. Web
[7] “Hammond 1590BBS.” Available: http://www.hammondmfg.com/pdf/1590BBS.pdf. Web
[8] "The Skin Effect." (n.d.): n. pag. University of Colorado, Boulder. Web.
<http://ecee.colorado.edu/~ecen3400/Chapter%2020%20-%20The%20Skin%20Effect.pdf>.
[9] Kudeki, Erhan. "Rectangular Cavities." United States, Champaign. Web.
<https://courses.engr.illinois.edu/ece350/secure/notes/fall10/350lect28.pdf>.
[10] [Scaa082*], Texas Instruments Incorporated. High Speed Layout Guidelines(n.d.): n. pag.
Texas Instruments, Nov. 2006. Web. Feb. 2015.
<http://www.ti.com/lit/an/scaa082/scaa082.pdf>.
[11] "IEEE IEEE Code of Ethics." IEEE. IEEE, 2015. Web. 17 Feb. 2015.
<http://www.ieee.org/about/corporate/governance/p7-8.html>.
19
Appendix A: Professor Kwiat’s Challenge Information
20
Appendix B: Requirements and Verification Tables
Module
Requirement
Verification
Points
Integrator
1. Measure frequencies
between 1 kHz to 10 MHz
and measure wave
characteristics of 150 mV
1. Variable integration time with our
ideal integration time of 10-20ns
well within thresholds.
a. Set up box with 5V dc
wallwart power input, output
to oscilloscope, and input
from dc power supply at 150
mV.
b. Connect trigger to function
generator
c. Vary the frequency of the
function generator so that the
integration time is from 5ns to
25 ns.
d. Check output on oscilloscope
to confirm that it acts linearly
with frequency
30
2. Dark currents must be less
than 1% of total signal
2. Determine 0V noise characteristics
for the device to determine
measurement accuracy
a. Connect output to
oscilloscope and 5V wallwart
to power input
b. Ground input
c. Run integration
d. Observe results on
oscilloscope
e. Calculate statistical noise of
the device
5
3.
3. Demonstrate integration with
30
small signals on the order of 510ns in singles or multiples.
a. Set up box with 5V dc
wallwart power input, output
to oscilloscope, and input
from a pulse generator at 150
mV with a width of 5 ns.
b. Adjust pulse generator
frequency so that one and then
Accurately detect zero, one,
or more than one photon
detections during a given
time interval and measure
pulse widths of a minimum
of 1 ns
21
two pulses will fall within our
integration range.
c. Observe output on
oscilloscope and confirm
there is a difference between
one and two pulse width
integrations
4. Determine trigger tolerances
within our device and the
surrounding signals
a. Set up box with 5V dc
wallwart power input, output
to oscilloscope, and input
from a function generator at
150 mV and 30 MHz.
b. Install Kwiat’s delay circuit
on trigger signal input.
c. Record data while adjusting
the delay so that the delay
ranges from one half of a a
period lagging to one half a
period leading.
Analog to
Digital
Converter
15
1. Must operate at the same
1. Test for voltage range values for
15
speed as the integrator (100
0, 1, and 2 photon output
MHz) and hold the data until
a. Connect power and input
it can be accessed by the
cables from function
user. Variable binning is for
generator to DAC circuit.
outside requirements.
b. Set the frequency to 100
Trigger controlled.
MHz on the function
generator.
c. Set the voltage of the
function generator to 50 mV
and apply signal to the DAC.
d. Observe the output of the
DAC circuit using an
oscilloscope and record
whether signal results in 0, 1,
or 2 photons being detected
e. Repeat steps 3-4, increasing
the voltage by 10mV each
time until the upper threshold
of 2 photons is acquired.
22
EMI
Shielded
Enclosure
1. Construct and test the
efficacy of an EMI shielded
enclosure
1. Measure no input signal shield
effectiveness
a. Apply 5V power from the
wallwart and output to the
oscilloscope with the circuit
on the lab bench.
b. Observe the output
waveform of the
oscilloscope.
c. Place circuit inside the
enclosure and seal the box.
d. Observe the output
waveform on the
oscilloscope.
e. Compare results.
2. Measure test input signal shield
effectiveness
a. Apply 10MHz, 150 mV
pulse input signal from the
function generator, output
to the oscilloscope, and 5V
power from the wallwart
b. Observe the output
waveform of the
oscilloscope.
c. Place circuit inside the
enclosure and seal the box.
d. Observe the output
waveform on the
oscilloscope.
e. Compare results.
23
10