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THz Seminar, UCSB, February 17, 2011 THz & nmTransistors: Scaling Laws & State Density Limits. Mark Rodwell University of California, Santa Barbara Ohmic Contacts: A. Baraskar, A. C. Gossard UCSB HBT V. Jain, E. Lobisser, A. Baraskar, J. Rode, H.W. Chiang, B. J. Thibeault, UCSB M. Urteaga, M. Seo, Z. Griffith, J. Hacker, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company III-V MOSFETs A. Carter, J. Law, G. J. Burek, Y. Hwang, B. J. Thibeault, B. Mitchell, S. Stemmer, A. C. Gossard, C. Palmstrom, UCSB E. Kim, P. C. McIntyre Stanford University High-Current FET Channels: P. Asbeck: University of California, San Diego W. Frensley: University of Texas, Dallas S. Steiger, A. Paul, S. Lee, Y. Tan, G. Hegde, G. Klimeck, Purdue University T. Boykin University of Alabama, Huntsville [email protected] 805-893-3244, 805-893-5705 fax DC to daylight; far-infrared Integated Circuits IR today→ lasers & bolometers → generate & detect Far-infrared ICs: classical device physics, classical circuit design L1 L2 Q7 Q9 Q8 L3 L4 DIVOUT Q10 Q3,4 Q5,6 R6 R7 Q11 L5 RFIN R3 R5 VEF L6 Q1 C4 Q2 R4 R2 C3 C1 R1 C2 VEE It's all about the interfaces: ...wire resistance,... ...& charge density. contact and gate dielectrics... ...heat,... band structure and density of states ! Recent Results (UCSB and Teledyne) ...just to get the experimental stuff out of the way.... UCSB : THz Bipolar Transistor • 30nm emitter, 30nm base, 100nm collector • Lifted-off Pt/Ti/Pd/Au base contacts • Run 1: Optical lithography for base: fτ / fmax = 460 / 850 GHz • Run 2: E-beam lithography for base: fτ / fmax ~ 480 / 1000 GHz f 32 max U Gain (dB) 24 16 H = 0.8, 1.0, 1.2 THz f = 480 GHz 21 Aje = 0.22 x 2.7 m 2 Ic = 12.1 mA 8 Je = 20.4 mA/m2 P = 33.5 mW/m2 Vcb = 0.7 V 0 109 1010 1011 Frequency (Hz) 1012 (slides removed on unpublished 600 GHz IC results) III-V MOSFETs with Source/Drain Regrowth d I (mA/um) 1 V = -1, 0, 1, 2, 3 V gs 0.8 ~300nm L , 0.6 g 5.5nm Al O 2 3 0.4 0.2 0 0 0.5 1 1.5 V (Volts) ds 27 nm InGaAs MOSFET Transistor Scaling Laws Simple Device Physics: Resistance bulk resistance R bulk T A contact resistance -perpendicular R contact A contact resistance - parallel R contact A W' sheet 3L Good approximation for contact widths less than 2 transfer lengths. Simple Device Physics: Depletion Layers capacitance A C T transit time T 2v space-charge limited current I max 2v 2 Vapplied Vdepletion 2 A T V C I C where T I max Vapplied Vdepletion 2 Simple Device Physics: Thermal Resistance Exact Carslaw & Jaeger 1959 Long, Narrow Stripe HBT Emitter, FET Gate 1 1 L Rth ln Kth L W Kth L cylindrica l heat flow spherical heat flow near junction far from junction Square ( L by L ) IC on heat sink 1 L Rth sinh 1 Kth L W 1 W sinh 1 KthW L Rth 1 1 4 Kth L Kth L planar heat flow spherical heat flow near surface far from surface Simple Device Physics: Fringing Capacitance C W 1.5 L T parallel - plate fringing wiring capacitance C/L VLSI power-delay limits slowly - varying function C of W / G and W / G L 1 2 (1 to 3) FET parasitic capacitances C parasitic / L ~ FET scaling constraints Electron Plasma Resonance: Not a Dominant Limit T 1 Lkinetic A q2nm* T 1 Rbulk A q2nm* m dielectric relaxation frequency scattering frequency 1 Rbulk 1 / 2 f scattering f dielectric 2 Lkinetic Cdisplacement Rbulk n - InGaAs 1 2 Cdisplacement 7 10 / cm 19 3 T plasma frequency 1 / 2 f plasma LkineticCdisplacement 1 2 m 800 THz 7 THz 74 THz 80 THz 12 THz 31 THz 3.5 1019 / cm 3 p - InGaAs A Transistor Design: State Density Effects 1-D E-K 2-D 3-D E f k 2f / m k f m1/ 2 E1f / 2 v f k f / m E1f / 2 / m1/ 2 velocity density n k 1f (mE f )1/ 2 capacitance Q m1/ 2 E f 1/ 2 E f Q m1 E 0f E f Q m3 / 2 E1f / 2 E f current J nv f m0 E1f J m1/ 2 E 3f / 2 J m1E 2f conductivity J m0 E 0f m0 n 0 E f J m1/ 2 E1f / 2 m0 n1/ 2 E f J m1 E1f m0 n 2 / 3 E f n k 2f (m E f )1 n k 3f (mE f )3 / 2 Transistor Design: State Density Effects 1-D E-K 2-D 3-D E f k 2f / m k f m1/ 2 E1f / 2 v f k f / m E1f / 2 / m1/ 2 velocity density n k 1f m1/ 2 E1f / 2 n k 2f m1E1f n k 3f m3 / 2 E 3f / 2 capacitance Q m1/ 2 E f 1/ 2 E f Q m1 E 0f E f Q m3 / 2 E1f / 2 E f current J nv f m0 E1f J m1/ 2 E 3f / 2 J m1E 2f conductivity J m0 E 0f m0 n 0 E f J m1/ 2 E1f / 2 m0 n1/ 2 E f J m1 E1f m0 n 2 / 3 E f Transistor Design: State Density Effects 1-D 2-D 3-D E-K velocity density "capacitance" 1 Q/l 2m*qV f current q I Ef conductivity q2 sheet q 2 m* Vf 2 2 23 / 2 qm * E 3f / 2 1/ 2 J sheet ( E f and V f E f /q both measured relative to Ec ) 3 2 2 J qm * E 2f 4 2 3 q2 3 c 8 2/3 n2 / 3 FET Design g m Cg ch (v / Lg ) gate width W g Cgd Cgs, f Wg Cg ch LgWg Tox / ox Twell / 2 well (2 2 / q 2 ) / gm * voltage division ratio between 1 v the above three capacitors m * RDS Lg /(Wg v ) RS RD contact LS/DWg FET Design: Scaling g m Cg ch (v / Lg ) gate width W g Cgd Cgs, f Wg Cg ch LgWg Tox / ox Twell / 2 well (2 2 / q 2 ) / gm * voltage division ratio between 1 v the above three capacitors m * RDS Lg /(Wg v ) RS RD contact LS/DWg Bipolar Transistor Design We Tb b T 2Dn 2 b Wbc Tc c Tc 2v sat Ccb Ac /Tc I c ,max vsat Ae (Vce,operating Vce,punch-through) / T 2 c P T LE Le 1 ln We Rex contact/Ae We Wbc contact Rbb sheet 12 Le 6 Le Acontacts emitter length LE Bipolar Transistor Design: Scaling We Tb b T 2Dn 2 b Wbc Tc c Tc 2v sat Ccb Ac /Tc I c ,max vsat Ae (Vce,operating Vce,punch-through) / T 2 c P T LE Le 1 ln We Rex contact/Ae We Wbc contact Rbb sheet 12 Le 6 Le Acontacts emitter length LE Changes required to double transistor bandwidth We emitter length LE HBT parameter emitter & collector junction widths current density (mA/m2) current density (mA/m) collector depletion thickness base thickness emitter & base contact resistivities change decrease 4:1 increase 4:1 constant decrease 2:1 decrease 1.4:1 decrease 4:1 nearly constant junction temperature → linewidths vary as (1 / bandwidth) 2 LG gate width WG constant voltage, constant velocity scaling FET parameter gate length current density (mA/m), gm (mS/m) channel 2DEG electron density gate-channel capacitance density dielectric equivalent thickness channel thickness channel density of states source & drain contact resistivities change decrease 2:1 increase 2:1 increase 2:1 increase 2:1 decrease 2:1 decrease 2:1 increase 2:1 decrease 4:1 fringing capacitance does not scale → linewidths scale as (1 / bandwidth ) THz & nm Transistors: it's all about the interfaces Metal-semiconductor interfaces (Ohmic contacts): very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density THz & nm Transistors: it's all about heat Transistor Self-heating IC power density wire length 1 circuit bandwidth IC area 1 circuit bandwidth 2 P L T ~ ln K th L W PIC T K th L THz & nm Transistors: it's all about state density Density of states limit to contact resistivity 8 1 c 2 2 / 3 0.1 m 2 n q 3 for n carrier concentration 7 1019 / cm 3 . 2/3 Density of states limit to current in 3-D transistors (HBTs) mA m* E f Ec mA E f Ec 65 g J 80,000 2 2 m m 1 eV m 0 . 1 eV 0 for an InP emitter (m * / m0 0.08) 2 2 Density of states limit to current in 2-D transistors (FETs) 1/ 2 E f Ec 1 eV for an InGaAs channel (m* /m0 0.04) mA m* g I d / Wg 84 m m0 3/ 2 mA E f Ec 17 m 1 eV 3/ 2 Bipolar Transistor Technology UCSB 128 nm InP HBT Process V. Jain E. Lobisser J. Rode H.W. Chan Other Serious Scaling Challenges J(mA/um^2) Transonductance drops due to degenerate injection 10 2 10 1 10 0 10 -1 10 -2 10 -3 Rodwell Lundstrom Jain. Fermi-Dirac Boltzmann Equivalent series resistance approximation -0.3 -0.2 -0.1 V - 0 0.1 0.2 be Highly degenerate limit J Even zero-barrier Ohmic contacts have resistance qm * ( E f Ec ) 2 4 2 3 mA E f Ec 65 2 m 0.1 eV 2 for InP emitter (m* /m0 0.08). Barrier quantum reflection makes this worse. Zero - barrier contact resistivity : 8 1 1 c 2 2 2 / 3 T n q 3 n carrier concentration 2/3 T transmission coefficien t c 0.1 m 2 at n 7 1019 / cm 3 . Ohmic Contacts Conventional ex-situ contacts are a mess THz transistor bandwidths: very low-resistivity contacts are required textbook contact with surface oxide with metal penetration Interface barrier → resistance Further intermixing during high-current operation → degradation Benefits of refractory base contacts 15 nm Pd/Ti diffusion 100 nm InGaAs grown in MBE 30 nm Mo After 250°C anneal, Pd/Ti/Pd/Au diffuses 15nm into semiconductor deposited Pd thickness: 2.5nm base now 30 nm thick: observed to degrade with thinner bases Refractory Mo contacts do not diffuse measurably Refractory, non-diffusive metal contacts for thin base semiconductor A.. Baraskar Ohmic Contacts: to N type InAs -6 Theory : zero - barrier, state - limited transport Theory, R = 0 2 Contact Resistivity (cm ) 10 qn( E )v( E ) F ( E )dE at interface Theory, R = 0.54 F ( E ) Fermi - Dirac distribution, -7 10 n density, v velocity Experimental zero barrier implies 100% tunneling probability R interface quantum reflection -8 10 For metal - InGaAs interface, R 54% . Landauer limit At T 0, R 0, this becomes (Landauer) -9 10 16 10 17 18 19 20 10 10 10 10 -3 Electron concentration (cm ) 8 c 2 q 3 2/3 1 ne2 / 3 1 If tunneling dominates : C exp n InAs data is consistent with zero - interface barrier, interface reflection . InAs data is the lowest reported for III - V contacts Ohmic Contacts: to N type InGaAs -6 Theory (R = 0.44) 2 Contact Resistivity (cm ) 10 Theory : State - limited conductance Experimental (tunneling limited) with 100% tunneling probability -7 10 Data suggests : Theory (R = 0) tunneling dominates contact resistance, except at the highest measured doping. -8 10 Landauer limit 1 n C ,tunneling exp -9 10 16 10 17 18 19 20 10 10 10 10 -3 Electron concentration (cm ) InGaAs contacts are sufficient for 64 nm node. Increased doping should rapidly reduce C . Ohmic Contacts: Ptype to InGaAs -6 Theory : State - limited conductance 2 Contact Resistivity (cm ) 10 with 100% tunneling probability -7 10 Data again suggests : -8 10 Theory Experimental: Ir contacts Experimental: W contacts Experimental: Mo contacts Landauer -9 10 -10 10 tunneling dominates contact resistance, except at the highest measured doping. 17 10 18 19 1 n C ,tunneling exp 20 10 10 10 -3 Hole Concentration (cm ) InGaAs contacts are sufficient for 64 nm node. Increased doping should rapidly reduce C . THz III-V FETs / HEMTs and nm III-V MOSFETs 10 nm / 3 THz III-V FETs: Challenges & Solutions To double the bandwidth: gate dielectric: decrease EOT 2:1 S/D access regions: decrease resistivity 2:1 channel: keep same velocity, but thin channel 2:1 increase density of states 2:1 Thin, high current density III-V FET channels InGaAs, InAs FETs THz & VLSI need high current low m*→ high velocities FET scaling for speed requires increased charge density low m* →low charge density Density of states bottleneck (Fischetti TED 2001, Solomon & Laux IEDM 2001) → For < 0.6 nm EOT, silicon beats III-Vs Open the bottle ! low transport mass → high vcarrier multiple valleys or anistropic valleys → high DOS Use the L valleys. Semiconductor Capacitances Must Also Scale (Vgs Vth ) cox (unidirecti onal motion) cdepth / Tinversion ( E f Ewell ) / q cdos q2 gm* / 22 channel charge qns cdos(V f Vwell ) q( E f Ewell ) ( gm* / 22 ) Inversion thickness & density of states must also both scale. Rodwell, DRC 2010 Calculating Current: Ballistic Limit Channel Fermi voltage voltage applied to cdos Natori determines Fermi velocity v f through E f qV f m * v 2f / 2 mean electron velocity v (4 / 3 )v f Channel charge : s cdos V f Vc cdoscequiv cequiv cdos V cdos q2 gm * / 22 cdos,o g (m * / mo ) , where g is the # of band minima mA Vgs Vth g (m * / mo )1 / 2 J 84 3/ 2 m 1 V 1 (cdos,o / cox ) g (m * / mo ) 3/ 2 Do we get highest current with high or low mass ? gs Vth Drive current versus mass, # valleys, and EOT mA Vgs Vth J K1 84 m 1 V normalized drive current K 1 0.35 3/ 2 , where K1 InGaAs <--> InP 1 (c g m* mo 1/ 2 * dos,o / cequiv ) g ( m / mo ) Si 3/ 2 g=2 g=1 0.3 cequiv ( 1/cox 1/cdepth )1 0.25 εSiO2 /EOT 0.2 0.3 nm 0.4 nm 0.15 0.1 0.05 0.6 nm EOT includes the wavefunction depth term (mean wavefunction depth* SiO2 /semiconductor ) 0 0.01 EOT=1.0 nm 0.1 m*/m 1 o InGaAs MOSFETs: superior Id to Si at large EOT. InGaAs MOSFETs: inferior Id to Si at small EOT. Fischetti / Solomon / Laux Density-of-States-Bottleneck → III-V loses to Si. III-V Band Properties, normal {100} Wafer valley GaAs Si X valley L valley ml / mo mt / mo E x E ml / mo mt / mo E L E 1.29 0.19 0.83 eV 1.23 0.062 0.47 eV 0.067 1.13 1.30 0.16 0.22 0.87 eV 0.47 eV 0.65 1.90 0.050 0.075 0.57 eV 0.28 eV --- 0.92 0.19 (negative) material substrate m* / mo material substrate 0.045 In 0.5Ga 0.5As InP 0.026 InAs InP GaAs Si L X L - valley transverse masses are comparable to valleys Consider instead: valleys in {111} Wafer valley GaAs Si X valley L valley ml / mo mt / mo E x E ml / mo mt / mo E L E 1.29 0.19 0.83 eV 1.23 0.062 0.47 eV 0.067 1.13 1.30 0.16 0.22 0.87 eV 0.47 eV 0.65 1.90 0.050 0.075 0.57 eV 0.28 eV --- 0.92 0.19 (negative) material substrate m* / mo material substrate 0.045 In 0.5Ga 0.5As InP 0.026 InAs InP GaAs Si L X Orientation : one L valley has high vertical mass X valleys & three L valleys have moderate vertical mass Valley in {111} wafer: with quantization in thin wells valley GaAs Si X valley L valley ml / mo mt / mo E x E ml / mo mt / mo E L E 1.29 0.19 0.83 eV 1.23 0.062 0.47 eV 0.067 1.13 1.30 0.16 0.22 0.87 eV 0.47 eV 0.65 1.90 0.050 0.075 0.57 eV 0.28 eV --- 0.92 0.19 (negative) material substrate m* / mo material substrate 0.045 In 0.5Ga 0.5As InP 0.026 InAs InP GaAs Si L X Selects L[111] valley; low transverse mass {111} -L FET: Candidate Channel Materials valley material material m* / mo In material 0.5Ga 0.5As In Ga 0.045 0.5 0.5As GaAs GaAs 0.067 GaSb GaSb 0.039 Ge /m mm l /l mo o 1.23 1.23 valley LLvalley / m EEL LEE mm t /t mo o 0.062 0.47 0.47eV eV 0.062 1.90 1.90 1.30 1.30 1.58 0.075 0.075 0.10 0.10 0.08 0.28eV eV 0.28 0.07eV eV 0.07 (negative) Well thickness for L alignment 1 nm (?) 2 nm 4 nm --- =0 eV L=177 meV X[100]= 264 meV X[010] = 337 meV Wavefunctions 3 nm GaAs well AlSb barriers Energy, eV Standard III-V FET: valley in [100] orientation 2 1.5 1 0.5 0 -0.5 -1 -1 X[010] X[100] L L 1st Approach: Use both and L valleys in [111] 2.3 nm GaAs well AlSb barriers [111] orientation -1 X L[111] L[111] L[111] = 41 meV L[111] (1)= 0 meV L[111] (2)= 84 meV L[111] , etc. =175 meV X=288 meV -1 L[111] Drive current vs. mass, # valleys, and EOT mA Vgs Vth J K1 84 m 1 V normalized drive current K 1 0.35 3/ 2 , where K1 {111} -L channels 1 (c 1/ 2 g=2 g=1 0.3 InGaAs...InP channels 0.25 0.3 nm 0.4 nm 0.15 0.1 0.05 * dos,o / cequiv ) g ( m / mo ) Si 0.2 g m* mo 0.6 nm EET=Equivalent Electrostatic Thickness =T / +T / ox SiO2 0 0.01 ox inversion SiO2 semiconductor 0.1 m*/m EET=1.0 nm 1 o Isotropic bands : transport in either valley, L [111] valley on (111) oriented surface or X [100] , [100] or [1 00] valleys on (100) oriented surface 3/ 2 Transit delay vs. mass, # valleys, and EOT 1/ 2 Lg m* 1 Volt Qch where K 2 ch K 2 7 m ID 2 . 52 10 cm/s V V gs th 0 EET=1.0 nm 1.5 ox SiO2 ox inversion SiO2 1 nm 0.4 nm 0.6 nm 0.4 nm semiconductor Si 1 {111} -L channels 1/ 2 * cdos,o m 1 g ceq mo 0.6 nm EET=Equivalent Electrostatic Thickness =T / +T / 2 Normalized transit delay K 1/ 2 g=1, isotropic bands 0.5 g=2, isotropic bands InGaAs...InP channels 0 0 0.05 0.1 0.15 0.2 0.25 m*/m Isotropicbands : transport in either valley, L [111] valley on (111) oriented surface 0.3 0.35 0.4 o or X [100] , [100] or [ 1 00] valleys on (100) oriented surface 2.52 107 cm/s Vgs Vth vinjection K 1 Volt 2 1/ 2 2nd Approach: Use L valleys in Stacked Wells Three 0.66 nm GaAs wells 0.66 nm AlSb barriers [111] orientation L[111](1) = 0 meV L[111](2)= 61 meV L[111](3)= 99 meV =338 meV L[111], etc =232 meV X=284 meV X L[111] L[111] -1 All L[111] -1 High-Current L & -L channels: 6 Approaches Rodwell et al, 2010 Device Research Conference 6/21/2010 0.1 EET=1.0 nm 0.1 m*/m 1 {111} -L channels Si InGaAs...InP channels 0 0.1 all curves: g=2 0 0.01 0.1 m /m t g=1 g=2 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 m*/m o 0 0.3 nm EET=1.0 nm o 0.5 0 l 0.2 1 EET=1.0 nm 0.6 nm 1 nm 0.4 nm 0.6 nm 0.4 nm isotropic in-plane transport 0.3 1.5 g=2 1 1 GaSb GaAs m /m =1.23 l 0 m /m =1.3 l 0 m /m =1.58 l 0 m /m =1.9 0.5 Ge InGaAs l 0 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 m /m t o l 0 all curves: g=4 0.6 nm 0.2 0.1 EET=1.0 nm 0 0.01 o 0.6 nm 0.3 nm 0.4 nm 0.3 1 EET=1.0 nm m /m =1.23 (InGaAs) l 0 m /m =1.3 (GaSb) l 0 m /m =1.58 (Ge) l 0 m /m =1.9 (GaAs) 0.3 nm 0.4 2 1.5 InGaAs...InP channels 0.6 nm 0.5 0.1 m /m t 3 g=4 Drain current, mA/m 0.4 nm 0.6 nm 0.4 normalized drive current K 0.15 m /m =1.23 l 0 m /m =1.3 l 0 m /m =1.58 l 0 m /m =1.9 0.4 nm normalized transit delay K 1 0.3 nm 0.2 0.05 g=1 g=2 0 0.01 0.5 normalized drive current K {100} Si 0.25 2 Normalized transit delay K {111} -L channels 0.3 2 0.35 normalized transit delay K normalized drive current K 1 red = occupied blue = vacant 1 o EET=1.0 nm 0.6 nm 2.5 0.3 nm 2 GaSb GaAs 1.5 m /m =1.23 l 0 m /m =1.3 l 0 m /m =1.58 l 0 m /m =1.9 1 Ge InGaAs 0.5 l 0 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 m /m t o 8 2.5 nm well pitch 7 0.3 nm EET 0.6 nm EET 6 5 4 3 5 nm well pitch 2 V -V =0.3 V 1 gs th 0 0.01 0.1 1 m*/mo mA Vgs Vth J K1 84 m 1 V 3/ 2 2.52 107 cm/s Vgs Vth K2 1 Volt 1/ 2 vinjection 3rd Approach: High Current Density L-Valley MQW FINFETs 8 2.5 nm well pitch Drain current, mA/m 7 6 V -V =0.3 V gs 5 3 5 nm well pitch 2 1 EOT includes wavefunction depth term 0 0.01 2 2 2 i 2m*W 2 th 4 (mean wavefunction depth* valley energies Emin,i qVmin,i 0.3 nm EOT 0.6 nm EOT current I i SiO2 / 0.1 m*/mo semiconductor ) 1 gq 2 V f Vmin,i charge : Qch gl 2m*qV f Vmin,i gate voltage :Vgs V f Qch / Cox i Concerns Nonparabolic bands reduce bound state energies Failure of effective mass approximation:1-2 nm wells 1-2 monolayer fluctuations in growth → scattering→ collapse in mobility Purdue Confirmation Purdue Confirmation Steiger, Klimeck, Boykin Ryu, Lee, Hegde, Tan THz FET scaling: with & without increased DOS Gate length nm Gate barrier EOT nm well thickness S/D resistance effective mass # band minima canonical fixed DOS stepped # 50 1.2 nm 8.0 m 210 *m0 0.05 1 1 1 35 0.83 25 0.58 18 0.41 13 0.29 9 0.21 5.7 150 0.05 4.0 100 0.05 2.8 74 0.08 2.0 53 1.4 37 0.08 0.08 1.4 1 1 2 1 1 2.8 1 2 4 1 3 5.7 1 3 3000 2500 f 4000 2500 max 1500 3500 3000 fmax 2000 f f , GHz 2000 canonical scaling stepped # of bands transport only , GHz Scaled FET performance: fixed vs. increasing DOS 1500 1000 500 500 0 2.5 0 1000 SCFL static divider clock rate, GHz drain current density, mA/m 1000 mA/m→ VLSI metric 2 1.5 1 0.5 200 mV gate overdrive 0 0 10 20 30 40 gate length, nm 50 60 SCFL divider speed 800 600 400 200 0 0 10 20 30 40 gate length, nm 50 Increased density of states needed for high drive current, fast logic @ 16, 11, 8 nm nodes 60 THz & nm Transistors DC to daylight; far-infrared Integated Circuits IR today→ lasers & bolometers → generate & detect Far-infrared ICs: classical device physics, classical circuit design It's all about the interfaces: ...wire resistance,... ...& charge density. contact and gate dielectrics... ...heat,... band structure and density of states ! (end) III-V Fabrication Processes Must Change... Greatly 32 nm base & emitter contacts...self-aligned 32 nm emitter junctions 1 m2 contact resistivities 70 mA/m2 → refractory contacts high-K dielectric replaces heterojunction 15 nm gate length 15 nm source / drain contacts...self-aligned < 10 nm source / drain spacers (sidewalls) 1/2 m2 contact resistivities 3 mA/m → 200 mA/m2 contacts above ~ 5 nm N+ layer → refractory contacts ! 670 GHz Transceiver Development: DARPA THz transmitter interconnects receiver circuits R1 Lout2 VOUT L1 R3 Lout1 Q5 Q3 Q4 LC3 Q9 R2 LC2 LE1 CVar Q8 L3 L4 DIVOUT R4 Q6 LB Q1 Q7 Q10 LC1 Q2 Q3,4 R7 L5 RFIN CVar LE2 R5 RE C2 Q5,6 R6 Q11 R4 R2 C1 R1 C2 C3 VBB C4 Q2 VEE VEE VTUNE VEF L6 Q1 R3 C1 L2 C3 Why Build THz Transistors ? 500 GHz digital logic → fiber optics THz amplifiers→ THz radios → imaging, sensing, communications precision analog design at microwave frequencies → high-performance receivers Higher-Resolution Microwave ADCs, DACs, DDSs Frequency Limits and Scaling Laws of (most) Electron Devices thickness C area / thickness Rtop contact / area Rbottom contact area PIN photodiode Rtop Rbottom sheet width 4 length I max, space-charge-limit area / thickness 2 power length T log length width To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1