Download A Temperature Compensation Technique for CMOS Current Controlled Current Conveyor (CCCII)

A Temperature Compensation Technique for CMOS
Current Controlled Current Conveyor (CCCII)
Montree Siripruchyanun
Department of Teacher Training in Electrical Engineering, Faculty of Technical Education,
King Mongkut’s Institute of Technology North Bangkok Bangkok, 10800, THAILAND
Email: [email protected]
ABSTRACT
An integrable temperature compensation technique
for CMOS current controlled current conveyor (CCCII) is
proposed. It uses a current biasing circuit which has a
current that is directly proportional to the absolute
temperature and can also be electronically controlled. The
HSPICE simulation results through the BSIM3v3 model
parameters of 0.5 μm CMOS technology from MOSIS
are given here. Furthermore, basic application examples
as a current controlled second-order bandpass filter and a
floating inductance simulator have been also considered.
CMOS technology are given to confirm the performance
of the proposed circuit. In addition, simulation results of
compensated CCCII in application examples, as a secondorder bandpass filter and a floating inductance simulator
are also included here.
2. CIRCUIT DESCRIPTION
2.1 Conventional CCCII
The matrix-relationship between the voltage and
current variables among port X, Y and Z of an ideal
CCCII can be described by the following matrix equation
Keywords: CCCII, Temperature compensation, CMOS
⎡ iy ⎤ ⎡0 0 0⎤ ⎡v y ⎤
⎢ v ⎥ = ⎢1 R 0 ⎥ ⎢ i ⎥
x
⎢ x⎥ ⎢
⎥⎢ x ⎥
⎢⎣ iz ⎥⎦ ⎢⎣ 0 ±1 0 ⎥⎦ ⎢⎣ vz ⎥⎦
1. INTRODUCTION
Second generation current conveyor (CCII) is a
versatile analog device which is used to implement many
analog signal processing functions such as active filters,
impedance simulators, and oscillators, etc. This currentmode device offers several advantages, such as greater
linearity and wider bandwidth over voltage-mode active
device likes op-amps [1]. The recently introduced second
generation current controlled current conveyor (CCCII)
[2-4] has the advantage of electronic adjustability over the
CCII. CCCII allows the adjustment of the x-terminal
intrinsic resistance via a bias current. Unfortunately, this
resistance is directly proportional to thermal voltage for
bipolar technology [2] and surface mobility ( μ ) for
CMOS technology [6]. This means that the characteristics
of the current controlled current conveyor-based circuits
will strongly depend on the absolute temperature.
Therefore, a technique of temperature compensation is
required.
In bipolar technology, this problem has been solved
using bias circuit, the principle is to generate a current that
directly relates to the thermal voltage [5]. However, this
technique cannot be used in CMOS technology.
In this paper, a temperature compensation technique
for CMOS CCCII is proposed. This technique uses
current biasing circuit with current directly proportional
to μ Cox′ and current divider circuit to generate bias
current for CCCII. The principal feature of the proposed
circuit is that the circuit employs only CMOS and some
external voltage and current sources such that the circuit
can be easily integrated on one chip. Simulation results of
the compensated CCCII by HSPICE through a 0.5μm
(1)
where the positive and negative signs of the current iz
denote the positive (CCCII+) and negative type (CCCII-),
respectively, and Rx is the X-terminal intrinsic resistance
of CCCII.
The circuit configuration for conventional CMOS
CCCII+ is illustrated in Fig.1, which based on
complementary source follower [6]. The X-input
impedance is calculated as
Rx ≈
1
( g m10 + g m11 )
(2)
where g mi denote the transconductance of transistor
number i , respectively. If matched transistors are
considered (M10 matching M11), that is g m10 = g m11 , then
Rx =
1
8β I 0
(3)
W⎞
W⎞
⎛
⎛
⎟ = β M11 = ⎜ μ Cox′
⎟ .
L ⎠ M10
L ⎠ M11
⎝
⎝
Since transconductance of transistor is proportional to
1/ I 0 , so that it is possible to control its value by
where
β = β M10 = ⎜ μ Cox′
changing the bias current. The temperature stability of Rx
strongly depends on physical parameter; β of the CMOS,
when temperature dependence is dominated on β as
followed [7]
VDD
M7
M6
M12
M5
M13
X
M1
Io =
M9
M8
M3
M2
Z
M10
M4
VSS
Fig.1: Conventional CMOS CCCII+
MR8
VDD
MR9
MR10
MR17
MR18
M=4
MR14
MR15
Ib
MR6
MR7
MR5
MR4
M=2
MR3
Ia
MR2
MR1
M=4
MR16
MR11 MR12
and 0 < m < 1 .
I b2
I b2
=
I a ⎛ μ Cox′ W ⎞ ⎛ V ⎞ 2
⎜ 2 L⎟ ⎜
⎟
⎝
⎠ MR1 ⎝ 1 − m ⎠
(7)
where I b is the external bias current.
Fig. 3 shows the completed circuit schematic of
temperature compensated CMOS CCCII and its transistor
dimensions are listed in Table 1. Using equations (3) and
(7), the intrinsic resistance Rx can be found as
2
Io
MR13
M=4
M=2
V
(W L )MR1 (W L )MR8
(W L )MR2 (W L )MR9
To obtain low supply regulation sensitivities, cascode
transistors, MR3 to MR7, are added to current mirror of
circuit. The current reference I a is available through
MR12.
MR13 to MR19 function as current multiplier-divider
[9] and provide an output current I o of the form
M11
Y
I0
where m =
MR19
VSS
⎛ μ Cox′ W ⎞ ⎛ V ⎞
⎜ 2 L⎟ ⎜
⎟
1
⎝
⎠ MR1 ⎝ 1 − m ⎠
=
Rx =
.
8β I b2
8β I o
(8)
W⎞
⎛
If ⎜ μ Cox′
= β , then
⎟
L ⎠ MR1
⎝
Fig.2: Current Biasing Circuit
⎛T ⎞
β = β0 ⎜ ⎟
⎝ T0 ⎠
Rx =
−1.5
(4)
where β 0 is a reference physical parameter of the CMOS
at a reference temperature; T0 . Hence, temperature
coefficient of Rx can be obtained as
1 ∂Rx 3 −1
= T .
Rx ∂T 4
(5)
It can be found that, from equation (5), Rx contributes a
positive temperature coefficient, thus current biasing
circuit that provides a negative temperature coefficient is
required for the compensation.
(
V
)
4 1 − m Ib
.
(9)
Now we can see that Rx is temperature insensitive
and can be controlled by I b .
Table 1: Transistor Aspect Ratio
Transistor
MR1-MR4
MR5-MR10
MR11-MR12
MR13, MR14, MR15, MR16, MR19
MR17, MR18, MR20, MR21
M1, M2, M3, M5, M8, M9, M11
M4, M6, M7, M10, M12, M13
W/L (μm/μm)
12/2.4
50/5
50/2.4
5/5
50/5
12/2.4
55/2.4
2.2 Proposed Technique
3. SIMULATION RESULTS
The principle of proposed temperature compensation
technique is based on a current biasing circuit that
generates a current with a negative temperature
coefficient. Fig. 2 shows the current biasing circuit which
generates a current that directly relates to the absolute
temperature. Transistors MR1, MR2, MR8 and MR9
function as a current reference generator [8] and generate
a current I a of the form
The performance of the proposed circuit in Fig. 3 was
simulated using HSPICE through a MOSIS 0.5 μm CMOS
process BSIM3v3 model parameters. The circuit was
operated with ±3 V supply, the currents I b is set to 85 μA,
V = 250 mV and an input signal voltage is applied at port
X. The simulation results are shown in Fig. 4, which
displays the resistance at port X against temperature
variations.
⎛ μ Cox′ W ⎞ ⎛ V ⎞
Ia = ⎜
⎟
⎟ ⎜
⎝ 2 L ⎠ MR1 ⎝ 1 − m ⎠
2
(6)
VDD
MR8
MR9
MR17
MR10
MR18
MR21
MR20
M6
M7
M13
M12
Ib
MR5
MR6
MR7
M5
M=4
MR4
MR3
MR14
Y
Io
MR15
M11
M=2
X
Z
M10
M4
Ia
MR1
MR2
M=2
V
M=4
MR11
M1
M=4
MR13
MR12
M2
M3
M8
M9
MR19
MR16
VSS
Fig.3: Temperature Compensated CMOS CCCII+
The simulation result in Fig. 4 shows that the
temperature performance of the compensated circuit is
much better than that of the conventional circuit. The
maximum resistance deviations of conventional and
compensated circuit are approximately equal to 25.24 and
3.34 %, respectively, in temperature range -20 to 100 °C.
2600
Compensated
Conventional
Resistance, Rx (Ω)
2400
2200
Equation (11) indicates that the value of ω0 is
adjusted by bias current of CCCII+s without affecting
either the quality factor or the gain.
The filter circuit was simulated with I b = 80μA and
V = 250 mV for CCCIIs. The simulation results in Fig. 5
show the frequency responses obtained with C1 = 4 nF
and C2 = 10 nF at temperature 0, 27 and 75 °C, compared
between the conventional CMOS CCCII+ and the
temperature compensated CMOS CCCII+, as depicted in
Fig. 5(a) and (b), respectively.
2000
1800
1600
1400
1200
-20
0
20
40
60
80
100
Temperature (°C)
Fig.4: Resistance Rx against Temperature variations
4. APPLICATION EXAMPLES
4.1 Current Controlled Second-order Bandpass Filter
(a) Using the Conventional CMOS CCCII+
The second-order band-pass filter requires two
CCCII+s and two grounded capacitors, improved from
[3]. When both bias currents I b1 and I b 2 of CCCII are
equal to I b , their intrinsic resistances have the same value
Rx . Therefore, transfer function of this circuit whose gain
at ω0 is unity, will be characterized by
vout
Rx C1 s
= 2
vin
Rx C1C2 s 2 + Rx C1 s + 1
(
ω0 = Rx C1C2
Q = C2 C1 .
)
−1
(10)
(11)
(12)
(b) Using the Temperature Compensated CMOS CCCII+
Fig.5: Frequency responses of the bandpass filter for
difference temperatures; × : 0 °C, + : 27 °C, , : 75 °C.
4.2 Floating Inductance Simulation
The floating inductance simulator, which is modified
from [10], employs four CCCII+s and one grounded
capacitor. The equivalent impedance is given by
Z eq = ( Rx1 + Rx 2 )( Rx 3 + Rx 4 ) Cs .
circuit is less temperature sensitive than conventional
circuit, the simulation results of application examples as
second-order bandpass filter and inductance simulator are
additionally good evidences. Also, the resulting circuit is
suitable for further implementing in integrated circuit.
(13)
When all bias currents are identical, the equivalent
inductance is
6. ACKNOWLEDGEMENT
The author would like to thank Mr. Kriangkrai
Sooksood for his help to prepare paper and simulation.
2
⎛
⎞
1
V
⎟ C.
L = 4 Rx2 C = ⎜
4 ⎜ 1 − m Ib ⎟
⎝
⎠
(
)
(14)
From Equation (14), it can be found that the
inductance can be controlled by the bias current.
The performance of inductance simulator was
verified by series RLC resonance circuit with R = 1kΩ
and C = 1nF. The current characteristics of the circuit are
shown in Fig. 6 with different temperatures as 0, 27 and
70 °C.
(a) Using the Conventional CMOS CCCII+
(b) Using the Temperature Compensated CMOS CCCII+
Fig.6: Current characteristics of series resonance
circuit; × : 0 °C, + : 27 °C, , : 70 °C.
5. CONCLUSION
In this paper, a temperature compensation technique
for CMOS CCCII has been proposed. A current biasing
circuit with a current proportional to absolute temperature
is used to compensate the temperature sensitivity of a
CMOS CCCII. The simulation results obtained from
HSPICE confirm that the temperature compensated
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