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National Aeronautics and Space Administration
Analysis of Performance Degradation of Integrated Circuits due to Transistor
Aging Effects in Nano-Scale
Jesus Garcia, Joshua Lohse, John Paulino, Hector Prado
Advisers: Hamid Mahmoodi, Amelito Enriquez, Paul Grams; Mentors: Sridevi Lakshmipuram, Atul Balani
The resistance values which simulate SBD effect can be related to time using
the equation:
Vdd = supply voltage, I0 = Initial leakage or defect current
GR = defect current growth rate, t = time
1100000
C. POWER
900000
I. Investigate and understand Soft Oxide Breakdown (SBD) in Integrated
Circuits.
II. Gain experience in Very Large Scaled-Integration (VLSI) design
software.
III. Analyze delay multisampling feasibility.
IV. Relate computer simulation data to experimental results.
300
250
250
3.2GR NMOS
200
300000
150
100
-100000
200
5 Stage
7 Stage
3 Stage
50
0
2
Figure 2. Transistor Symbol
with RSBD
4
6
8
Time (years)
10
12
Power (μWatts)
500000
100000
GOALS
300
700000
Power (μWatts)
Integrated Circuits, or ICs, work behind the scenes to improve the standard
of life. IC performance dramatically improved since their first creation.
However, with scaling of ICs to nano-scale, an ideal integrated circuit
delivering reliable performance over its lifetime is nearly impossible. All ICs
experience degradation over time due to the aging of underlying transistors.
In this research, analysis of transistor breakdown is performed through
computer simulations to understand effects on circuit power and
performance. To simulate transistor breakdown effect, a 90nm ring oscillator
circuit is utilized. This breakdown is modeled by resistors placed between
the transistor terminals. This study aims to offer better insight into the
impact of transistor breakdown and to improve IC design in nano-scale.
TIME-RESISTANCE RELATIONSHIP
Leakage Resistance (Ohm)
ABSTRACT
The results from the three ring oscillators show no perceptible difference in
delay up to the 10kΩ average life limit proposed in this study. Differences
occur when the SBD is close to a hard breakdown ~3-4kΩ, which causes the
circuit to fail completely. The differences in delay and period are believed to
be too small for multisampling measurements within the confines of this
study. Multisampling may be possible with simulations that have multiple
inverters that suffer from SBD because they increase the delay further.
150
5-stage
100
7-stage
3-stage
50
0
14
200
20
Resistance (KOhm)
2
0
0
Figure 8. Power vs. Resistance
Figure 3. Resistance vs. Time Plot
5
Time (years)
10
Figure 9. Power vs. Time
Figure (8) indicates that the power consumption of the circuit increases as the
leakage resistance decreases because it is easier for the defect current to get
through the gate oxide.
ANALYSIS
According to Figure (9), as ICs age, the power consumption mimics an
exponential growth curve due to SBD.
A. CIRCUIT UNDER TEST: RING OSCILLATOR
SOFT OXIDE BREAKDOWN
EXPERIMENTAL RESULTS
1.20E-04
1.00E-04
T=20C
Fresh IC
Current(A)
8.00E-05
6.00E-05
Figure 4. Schematic of 5 Stage Ring Oscillator
4.00E-05
Figure 5. Input and Output Voltages of Ring
Oscillator showing delay
A ring oscillator is used in place of a logic circuit for ease of design and
simulation. Three ring oscillators were created in three, five and seven stages.
B. DELAY
350.0
300.0
300.0
250.0
250.0
200.0
150.0
100.0
100
10
Resistance (kOhm)
3 Stage
1
1.5
2
Figure 11. Section of chip being stress tested
14.00
12.00
12.00
10.00
10.00
10
Resistance (kOhm)
1
7 Stage
5 Stage
3 Stage
Delay (ps)
14.00
4.00
CONCLUSION
3 Stage
50.0
0.0
0.00E+00
6.00
100
0.5
Voltage(V)
5 Stage
100.0
1
APPROACH
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5 Stage
2.00E+08
Time (s)
•
4.00E+08
•
Figure 6. NMOS Gate to Source: Period vs. Resistance on left and Period vs. Time on right
1000
0
7 Stage
150.0
0.0
1000
0.00E+00
The leakage vs. voltage plot of an IC before and after shows significant
change as a result of breakdown after stress test.
200.0
50.0
8.00
• Model Soft Oxide Breakdown using resistance values at NMOS Gate to
Source and Gate to Drain.
• Take a range of resistance values from 1MΩ down to 1kΩ and relate
those values to time.
• Consider a reasonable lifetime of five years with cutoff resistance of
10kΩ.
• Use Synopsys Custom Designer for schematic design and HSPICE for
running simulations.
7 Stage
Period (ps)
350.0
Period (ps)
All integrated circuits will experience degradation, which can come in many
forms. SBD is a type of degradation that involves the formation of traps in
the gate oxide layer of the transistor. These traps, which are defects in the
structure of the SiO2 gate oxide, form conduction paths and develop
leakage current from the polysilicon gate to the silicon substrate. The
leakage current affects the power consumption of the circuit even during its
off state. There is debate about the cause of trap formation, which includes
fabrication issues, hole creation, proton release, irradiation, and thermal
damage.
2.00E-05
Figure 10. Current leakage measurements of Fresh IC at
T=20C and stress tested IC measured at T=20C and T=100C
Delay (ps)
Figure 1: Cross Section of NMOS transistor showing traps
and conduction path in the gate oxide region
T=20C
After
Stress
T=100C
After
Stress
•
•
8.00
7 Stage
6.00
5 Stage
4.00
2.00
2.00
0.00
0.00
0.00E+00
3 Stage
1.00E+08
2.00E+08
3.00E+08
4.00E+08
Time (s)
Figure 7. NMOS/PMOS Gate to Drain: Delay vs. Resistance on left and Delay vs. Time on right
PMOS/NMOS Gate to Drain shows an increase in performance until a
different physical behavior called hard breakdown occurs. This breakdown
causes the delay to increase exponentially.
•
Adding resistors to the IC produces reliable approximations to the effects
of SBD.
SBD causes the delay to decrease under Gate to Drain breakdown, but
an increase with Gate to Source.
Delayed Multisampling is not feasible with single inverter breakdown.
This research confirms that power consumption increases due to the
increase in leakage current from SBD.
Experimental results support our data simulations.
Acknowledgements
This project is sponsored by NASA
Office of Education through
the Curriculum Improvement
Partnership Award for the
Integration of Research (CIPAIR)