Download SHF-0289 SHF-0289Z 0.05 - 6 GHz, 1.0 Watt Product Description

Product Description
Sirenza Microdevices’ SHF-0289 is a high performance AlGaAs/GaAs
Heterostructure FET (HFET) housed in a low-cost surface-mount plastic
package. The HFET technology improves breakdown voltage while minimizing
Schottky leakage current resulting in higher PAE and improved linearity.
SHF-0289
SHF-0289Z
Pb
RoHS Compliant
& Green Package
0.05 - 6 GHz, 1.0 Watt
GaAs HFET
Output power at 1dB compression for the SHF-0289 is +30dBm when
biased for Class AB operation at 7V,200mA. The +43 dBm third order
intercept makes it ideal for high dynamic range, high intercept point
requirements. It is well suited for use in both analog and digital wireless
communication infrastructure and subscriber equipment including 3G,
cellular, PCS, fixed wireless, and pager systems.
The matte tin finish on Sirenza’s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Product Features
Directive 2002/95. This package is also manufactured with green molding • Now available in Lead Free, RoHS
compounds that contain no antimony trioxide nor halogenated fire retarCompliant, & Green Packaging
dants.
• High Linearity Performance at 1.96 GHz
+30 dBm P1dB
+43 dBm OIP3
+23.7 dBm IS-95 Channel Power
+14.6 dB Gain
• +21.7 dBm W-CDMA Channel Power
• High Drain Efficiency (>50% at P1dB)
• See App Note AN-032 for circuit details
Gain, Gmax (dB)
Typical Gain Performance (7V,200mA)
40
35
30
25
20
15
10
5
0
Gmax
Gain
Applications
0
1
2
3
4
5
• Analog and Digital Wireless Systems
• 3G, Cellular, PCS
• Fixed Wireless, Pager Systems
6
Frequency (GHz)
S ym bol
T e s t C o n d it io n s , 2 5 C
V D S = 7 V , ID Q = 2 0 0 m A
D e v ic e C h a r a c t e r is t ic s
Test
F re q u e n c y
U n it s
M in
Typ
M ax
Z S = Z S*, Z L= Z L*
0 .9 0 G H z
1 .9 6 G H z
2 .1 4 G H z
dB
dB
dB
-
23
20
1 9 .5
-
( u n le s s o t h e r w is e n o t e d )
Gm ax
S
21
M a x i m u m A v a i la b le G a i n
[1 ]
In s e r t i o n G a i n
[2 ]
G a in
P o w e r G a in
O IP 3
O u t p u t T h i r d O r d e r In t e r c e p t P o i n t
P 1dB
O u tp u t 1 d B C o m p r e s s i o n P o i n t
P
IS - 9 5 C h a n n e l P o w e r ( - 4 5 d B c A C P R )
C HA N
[2 ]
[2 ]
[2 ]
Z S= Z L= 5 0 O hm s
0 .9 0 G H z
dB
1 6 .7
1 8 .5
2 0 .3
A p p li c a t i o n C i r c u i t
1 .9 6 G H z
dB m
1 3 .1
1 4 .6
1 6 .1
A p p li c a t i o n C i r c u i t
1 .9 6 G H z
dB m
4 0 .5
4 3 .0
-
A p p li c a t i o n C i r c u i t
1 .9 6 G H z
dB m
2 8 .7
3 0 .2
-
A p p li c a t i o n C i r c u i t
1 .9 6 G H z
dB m
-
2 3 .7
-
A p p li c a t i o n C i r c u i t
1 .9 6 G H z
dB
-
4 .0
-
m A
408
588
768
NF
N o is e F ig u re
ID S S
S a tu r a te d D r a i n C u r r e n t
V
= V
D S
m
T r a n c o n d u c ta n c e
V
D S
m S
288
396
504
P
P i n c h - O f f V o lt a g e
V
= 2 . 0 V , ID S = 1 . 2 m A
D S
V
- 3 .0
- 1 .9
- 1 .0
IG S = 2 . 4 m A , d r a i n o p e n
V
-
-1 7
-1 5
IG D = 2 . 4 m A , V
V
-
-2 2
-1 7
C /W
-
41
-
V
-
-
8 .0
m A
-
-
280
C
-
-
1 .4
g
V
B V
B V
GS
G D
[1 ]
G a t e - S o u r c e B r e a k d o w n V o lt a g e
G a t e - D r a i n B r e a k d o w n V o lt a g e
R th
T h e r m a l R e s i s ta n c e
V
O p e r a t i n g V o lt a g e
D S
ID Q
P
D IS S
O p e r a ti n g C u r r e n t
P o w e r D i s s i p a ti o n
[3 ]
[3 ]
[1 ]
[1 ]
= V
, V
D SP
D SP
, V
= 0V
GS
GS
= - 0 .2 5 V
G S
= - 5 .0 V
ju n c t i o n - t o - le a d
d ra in -s o u rc e
d ra in -s o u rc e , q u ie s c e n t
[3 ]
o
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board.
The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR.
[3] Maximum recommended power dissipation is specified to maintain TJ<140C at TL=85C. VDS * IDQ< 1.4W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent
rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or
systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MM
1
http://www.sirenza.com
EDS-101241 Rev E
SHF-0289 1 Watt HFET
Absolute Maximum Ratings
Parameter
MTTF is inversely proportional to the device junction
temperature. For junction temperature and MTTF
considerations the bias condition should also
satisfy the following expression:
PDC < (TJ - TL) / RTH
where:
PDC = IDS * VDS (W)
TJ = Junction Temperature (°C)
TL = Lead Temperature (pin 4) (°C)
RTH = Thermal Resistance (°C/W)
Total Dissipated Power (W)
Value
Unit
Drain Current
IDS
400
mA
Forward Gate Current
IGSF
2.4
mA
Reverse Gate Current
IGSR
2.4
mA
Drain-to-Source Voltage
V DS
+9.0
V
Gate-to-Source Voltage
V GS
<-5 or >0
V
RF Input Power
P IN
400
mW
Operating Lead Temperature
TL
See Graph
°C
Storage Temperature Range
Tstor
-40 to +165
°C
Power Dissipation
P DISS
See Graph
W
TJ
+165
°C
Channel Temperature
MTTF @ TJ=150C exceeds 1E7 hours
Symbol
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation, the device
voltage and current must not exceed the maximum operating values
specified in the table on page 1.
Power Derating Curve
3.0
2.5
2.0
1.5
1.0
Operational (Tj<140C)
ABS MAX (Tj<165C)
0.5
0.0
-40
-10
20
50
80
110
140 170
Lead Temperature (C)
Design Considerations and Trade-offs
1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-topart precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is
recommended to maintain acceptable performance (RF and thermal).
2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB).
3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance.
Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished
using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each
device to eliminate the effects of pinchoff process variation.
4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage
should be increased to 8V to maximize P1dB. For small signal operation the OIP3 may be improved by reducing the
voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V
bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation limit (shown on page 1).
303 S. Technology Court , Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-101241 Rev E
SHF-0289 1 Watt HFET
De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=7V, IDS=200mA, 25°C)
S11, S22 vs Frequency
0
-5
-10
-15
-20
-25
-30
-35
-40
Gmax
Gain
Isolation
0
1
2
3
4
5
1.0
0.5
Isolation (dB)
Gain, Gmax (dB)
Gain & Isolation
40
35
30
25
20
15
10
5
0
2.0
6 GHz
5 GHz
4 GHz
6 GHz
0.2
5.0
5 GHz
3 GHz
4 GHz
0.0
3 GHz
0.5
0.2
1.0
2 GHz
2 GHz
2.0
5.0
inf
50 MHz
50 MHz
1 GHz
S22
0.2
6
5.0
Frequency (GHz)
1 GHz
S11
0.5
2.0
1.0
Note: S-parameters are de-embedded to the device leads with Z S=Z L=50Ω. The data represents typical performace of the device.
De-embedded s-parameters can be downloaded from our website (www.sirenza.com).
DC-IV Curves
0.7
0.6
IDS (A)
0.5
0.4
VGS = -2.0 to 0V, 0.2V steps
T=25° C
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
VDS (V)
Typical Performance - Engineering Application Circuits (See App Note AN-032)
Freq
(MHz)
VDS
(V)
IDQ
(mA)
P1dB
(dBm)
-45dBc
Channel
Power
(dBm)
-55dBc
Channel
Power
(dBm)
OIP3[6]
(dBm)
Gain
(dB)
S11
(dB)
S22
(dB)
900
7
200
30.2
23.5[4]
21.1[4]
43.0
19.2
-15
-12
3.2
1960
7
200
30.2
23.7[4]
21.3[4]
43.0
14.6
-18
-10
4.0
2140
7
200
30.3
21.7[5]
20.4[5]
43.0
13.8
-18
-7
4.1
NF
(dB)
[4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW)
[5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW)
[6] POUT= +13dBm per tone, 1MHz tone spacing
303 S. Technology Court , Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-101241 Rev E
SHF-0289 1 Watt HFET
Part Number Ordering Information
Pin Description
Function
1
Gate
2
Source
3
Drain
4
Source
Description
RF Input
Connection to ground. Use via holes to reduce lead
inductance. Place vias as close to ground leads as possible.
RF Output
Same as Pin 2
Part Number
Reel Size
Devices/Reel
SHF-0289
7"
1000
SHF-0289Z
7"
1000
Part Symbolization
The part will be symbolized with the “H2”
designator and a dot signifying pin 1 on the top
surface of the package.
Mounting and Thermal Considerations
It is very important that adequate heat sinking be provided
to minimize the device junction temperature. The following
items should be implemented to maximize MTTF and RF
performance.
Package Dimensions
.161
3
1. Multiple solder-filled vias are required directly below the
ground tab (pin 4). [CRITICAL]
2. Incorporate a large ground pad area with multiple platedthrough vias around pin 4 of the device. [CRITICAL]
3. Use two point board seating to lower the thermal
resistance between the PCB and mounting plate. Place
machine screws as close to the ground tab (pin 4) as
possible. [CRITICAL]
4. Use 2 ounce copper to improve the PCB’s heat spreading
capability. [RECOMMENDED]
.016
.177 .068
.019 .118
1
2
Pin #
.096
.041
.015
.059
DIMENSIONS ARE IN INCHES
Recommended Mounting Configuration for
Optimum RF and Thermal Performance
H2Z
2
3
1
2
H2
1
1
1
4
3
SHF-0x89
4
2
Plated Thru
Holes
(0.020" DIA)
2
3
Ground Plane
3
Machine
Screws
Caution: ESD sensitive
Appropriate precautions in handling, packaging and
testing devices must be observed.
303 S. Technology Court , Broomfield, CO 80021
Phone: (800) SMI-MMIC
4
http://www.sirenza.com
EDS-101241 Rev E