Download Fast Analysis of Analog Design Trade-offs via Geometric Programming Theerachet Soorapanth

Fast Analysis of Analog Design Trade-offs via
Geometric Programming
Theerachet Soorapanth
National Electronics and Computer Technology Center, Bangkok, Thailand
Email: [email protected]
Abstract-This paper concerns a method for solving a variety
of analog design trade-off problems, which is based on
formulating the problem as a geometric program (GP). These
nonlinear, constrained optimization problem can be transformed
to convex optimization problems, and then solved (globally) very
efficiently. Designers can analyze quantitatively trade-offs among
different specifications as well as construct trade-off curves very
quickly owing to the efficiency of the method.
I.
INTRODUCTION
Most analog design problems deals with how to size a
circuit appropriately to achieve a set of specifications subject
to various constraints while spending the least amount of
resources such as power consumption, for instance. This
scenario allows one to formulate such problem as a
constrained optimization problem. The variables are often the
sizes of transistors and other circuit components as well as
biasing conditions. It is also possible to include other design
variables such as threshold voltage, supply voltage, and oxide
thickness. The choice of design variables determines various
top-level circuit objectives, such as the total area of the circuit,
the total power it consumes, its bandwidth and other
objectives such as noise tolerance, robustness to process and
environment parameter variations, and so on. These objectives
can be very complex functions of the design variables. In
addition, there are many constraints that must be satisfied.
There are many approaches to circuit sizing, including
heuristics, and methods based on circuit simulation coupled to
a generic numerical optimization.
This paper focuses on a particular approach, in which the
sizing problem is modeled (at least approximately) as a
geometric program (GP), a special type of mathematical
optimization. Fortunately, majority of analog circuit sizing
problems can be directly (if not, approximately) casted as GP
problems. Over the years, the efficient algorithms, such as an
interior-point method, to solve such problems have been
developed. GPs with tens of thousands of variables and
hundreds of thousands of constraints can be reliable solved in
minutes, on a personal computer. In addition, since GP is a
type of convex optimization, the achieved solution (if feasible)
is guaranteed to be globally optimal.
proposed for transistor and wire sizing based on Elmore delay,
that was later found to be a GP. Other digital circuit design
problems, that can be formulated as GPs, can be found in, e.g.
[2,3,4]. Recently, GP has been introduced to solve analog and
mixed-signal circuit problems [5,6].
A geometric program is an optimization problem of the
form
minimize
f0 ( x)
subject to
f i ( x ) $ 1,
i " 1,
,m
g i ( x ) " 1,
i " 1,
,p
x i # 0,
i " 1,
,n
(1)
where f 0 , , f m are posynomial functions and g1 , , g p
are monomial functions. Posynomial function has the form
t
!
!
f ( x1,..., xn ) " % ck x1 1k x2 2k
k "1
nk
x!
n
(2)
where c j 0 and ! ij is real. When there is only one term
in the sum, f is called a monomial function. A geometric
program can be reformulated as a convex optimization
problem by changing variables and considering the logs of the
function involved. We define new variables yi " log xi and
take the logarithm of a posynomial f to get
(
+ t T
h( y) " log f (e y1 ,...,e yn ) " log)) % e!k y,bk &&
'
* k "1
(3)
where ! kT " [!1k !! nk ] and bk " log ck . It can be shown
that h is a convex function of the variable y . Similar
transformation can be made to the equality constraint function
g . The convexity property guarantees the problem’s solution
(if feasible) is globally optimal. In addition, the problem can
be solved using a very efficient interior-point method [7].
III. CIRCUIT MODELING FOR GP
II. GEOMETRIC PROGRAMMING
GP-based circuit optimization is not new; it has been used
for digital circuits since the 1980s. In [1], a method was
For circuit problem to be solved by GP, each design
equations must be modeled (or approximated) by
posynomial/monomial functions. Fortunately, majority of
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circuit design equations can be modeled as such. For instance,
the following long-channel MOS device equation
1
I D " K pWL-1(VGS -VT )2
2
(4)
can be considered as a monomial function of transistor width
W , transistor length L , and overdrive voltage VGS - VT .
Similarly, the transconductance equation can be written in
monomial form as
2 3
gm (W , L, I D ) " 2K p
W1/ 2 L-1/ 2 I 1D/ 2
1/ 2
(5)
In addition to device equations, constraint on device operating
condition can be modeled by a monomial as well. For instance,
the constraint for an MOS to be in saturation,
VGS - VT $ VDS ,min , can be written in monomial form as
+ 2
(
1
)
&I 1/ 2L1/ 2W -1/ 2 $ 1
) K p 2VDS,min ,VT 3 & D
*
'
(6)
Submicron short-channel devices can also be modeled with a
posynomial by performing a SPICE-simulation-based
posynomial function fitting over large ranges of length, width,
and bias currents.
IV. EXAMPLE: AN OP-AMP DESIGN
As an example, we will apply the GP method to the design
of a common analog circuit building block, an operational
amplifier. There are several op-amp architectures. We will
consider a two-stage architecture as shown in Fig. 1. Other opamp architectures can be applied as well, but this particular
architecture is chosen for its design simplicity and good
achieved performance.
Figure 1. Two-stage op-amp architecture.
To set up the op-amp design problem for GP, we have to
consider a variety of performance measures and constraints,
which must be formulated in GP-compatible forms. The
design variables are the transistor sizes (width and length), the
value of the passive components (capacitors and resistors),
and the value of the bias currents and bias voltages. For this
particular two-stage op-amp, there are nineteen design
variables. The constraints in the design of this op-amp are
summarized as follows
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
Symmetry and matching: M 1 " M 2 , M 3 " M 4
Limit on device sizes: W Wmin , L Lmin
Limit on chip area: A $ Amax
Systematic input offset voltage
Current ratio equalities: I M 5 0 I M 8 , I M 7 0 I M 8 ,
IM1 0 IM 5
Bias conditions: VGS - VT $ VDS
Gate overdrive voltage: VGS - VT VOD,min
Limit on power consumption: P $ Pmax
Open-loop DC gain
Unity-gain bandwidth
Phase-margin
Slew-rate
Common-mode rejection ratio
Power-supply rejection ratio
Input-referred noise
In total, there are forty-six constraints, both inequalities and
equalities expressed by posynomials and monomials,
respectively, according to (1). The objectives of the design can
vary depending on the specifications.
V. DESIGN IMPLEMENTATIONS
The op-amp design has been implemented in C language for
GP optimization. We choose a 0.8-1m CMOS technology and
specify the design objective to be unity-gain bandwidth
maximization. The results are shown in Table 1 and 2.
The first column in Table 1 identifies the performance
measures; the second gives the specification. The third column
shows the performance of the design obtained from GP
optimization. The fourth column shows the value of the
specification as simulated by SPECTRE from our optimal
design (Fig. 2).
We can see that both GP calculation and SPECTRE
simulation achieve or exceed all of the required specifications.
Note that some of the constraints are loose, some are tight.
Tight constraints include power consumption, phase margin,
and input-referred noise, for instance. This suggests that there
are some trade-offs among these performance measures,
which will be further explored in the next section.
The computer time required for the design is two seconds
owing to the efficiency of the interior-point algorithm.
The optimal design parameters found are shown in Table 2.
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TABLE 1
DESIGN SPECIFICATIONS AND ACHIEVED PERFORMANCE
Performance Measure
Specification
Optimal
(GP calculation)
Optimal
(SPECTRE simulation)
Device length (1m)
Device width (1m)
Area (1m2)
Capacitance size (pF)
Load capacitance (pF)
Common-mode input range (V)
Output voltage range (V)
Power (mW)
DC gain (dB)
Unity-gain BW (MHz)
Phase margin (4)
Slew rate (V/1s)
CMRR (dB)
Neg. PSRR (dB)
Pos. PSRR (dB)
Input-referred noise, @1KHz (nV/5Hz)
0.8
2.0
$ 10000
0.1 $ C $ 2000
3
includes 0.5Vdd
[0.1,0.9]Vdd
$5
80
80
60
10
60
80
80
$ 300
0.8 (min)
2.0 (min)
7283
2.68
3
includes 0.5Vdd
[0.028,0.91]Vdd
5
89.4
90.1
60
87.2
92.6
98.5
118.5
300
0.8 (min)
2.0 (min)
7283
2.68
3
[0,0.77]Vdd
[0.02,0.94]Vdd
4.9
95.5
123
72
49
99
104.5
125.5
274
TABLE 2
OPTIMAL DESIGN FOR DESIGN EXAMPLE
Variable
Optimal value
W1=W2
W3=W4
W5
W6
W7
W8
L1=L2
L3=L4
L5
L6
L7
L8
Cc
Rc
Ibias
225.3 1m
109.5 1m
57.5 1m
557.9 1m
146.6 1m
2 1m
0.8 1m
0.8 1m
0.8 1m
0.8 1m
0.8 1m
0.8 1m
2.68 pF
94.3 ohm
9.1 1A
Figure 2. SPECTRE simulation plots.
TABLE 3
ACHIEVED PERFORMANCE FOR DIFFERENT DESIGN OBJECTIVES
Performance Measure
Device length (1m)
Device width (1m)
Area (1m2)
Capacitance size (pF)
Load capacitance (pF)
Common-mode input range (V)
Output voltage range (V)
Power (mW)
DC gain (dB)
Unity-gain BW (MHz)
Phase margin (4)
Slew rate (V/1s)
CMRR (dB)
Neg. PSRR (dB)
Pos. PSRR (dB)
Input-referred noise, @1KHz (nV/5Hz)
Specification
0.8
2.0
$ 10000
0.1 $ C $ 2000
3
includes 0.5Vdd
[0.1,0.9]Vdd
$5
80
80
60
10
60
80
80
$ 300
Max. UGBW
0.8 (min)
2.0 (min)
7283
2.68
3
includes 0.5Vdd
[0.028,0.91]Vdd
5
89.4
90.1
60
87.2
92.6
98.5
118.5
300
Design Objective
Max. DC gain
Min. noise
0.8 (min)
0.8 (min)
2.0 (min)
2.0 (min)
9162
10000
2.7
3.86
3
3
includes 0.5Vdd
includes 0.5Vdd
[0.018,0.9]Vdd
[0.026,0.904]Vdd
5
5
91.7
95.8
80
80
60
60
53.5
61.4
99.1
95
105
100.9
124.9
120.8
244.7
209
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Min. power
0.8 (min)
2.0 (min)
7218
2.68
3
includes 0.5Vdd
[0.024,0.908]Vdd
3.9
91.5
80
60
68.5
94.7
100.6
120.6
300
VI. TRADE-OFF ANALYSIS
VII. CONCLUSIONS
We can consider trade-offs among design specifications by
running GP optimization with four different objectives as
follows
We have shown how geometric programming can be used
to design analog circuits such as op-amps. The method is very
fast and efficient, can handle a wide variety of constraints and
provide globally optimal design. This allows designers to
spend more time on exploring different circuit architectures
rather than wasting time on optimizing a particular design
which may end up with a locally optimal solution. Trade-off
analysis can be performed very quickly thanks to the
efficiency of the GP algorithm.
./
./
./
./
Maximizing unity-gain bandwidth
Maximizing DC gain
Minimizing input-referred noise
Minimizing power consumption
Keeping the constraints unchanged, the optimization results
are compared in Table 3. The results indicate clear trade-offs
among gain, noise, unity-gain bandwidth, and power
consumption. For instance, if higher DC gain is desired, the
optimal design possesses lower unity-gain bandwidth. If lower
input-referred noise is preferred, larger chip area would be
required to accommodate larger device sizes. Finally, if low
power is favored, the smallest allowed bandwidth and
maximum allowed noise level result. Also, it is interesting to
note that some constraints, e.g. phase margin specification,
remain tight regardless of design objectives. This suggests that
all four previously-mentioned performance measures become
worsen with higher phase margin requirement.
Since the computation time for each optimization takes
merely two seconds, we can explore various design trade-offs
very quickly. Besides changing design objectives, we can
construct trade-off curves, like Fig. 3, by repeatedly solving
the design problem while varying one of the specifications.
Within a matter of minutes, we can sweep out the globally
optimal trade-off curve between competing objectives (with
the others fixed). Designers can determine which
specifications are more critical or relaxed.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
J. Fishburn, and A. Dunlop, “TILOS: A posynomial programming
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C. Chu and D. Wong, “Closed form solutions to simultaneous buffer
insertion/sizing and wire sizing,” ACM Transactions on Design
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D. Patil, Y. Yun, S.-J. Kim, S. Boyd, and M. Horowitz, “A new method
for robust design of digital circuits,” International Symposium on
Quality Electronic Design (ISQED) Digest of Technical Papers, 2005.
W. Chen, C.-T. Hseih, and M. Pedran, “Simultaneous gate sizing and
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M. Hershenson, S. Mohan, S. Boyd, and T. Lee, “Optimization of
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Figure 3. Trade-off curves between optimal unity-gain bandwidth, DC gain,
input-referred noise and power consumption, all versus phase margins.
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