Download Analysis and verification of routing effects on

Analysis and verification of routing effects on
signal integrity for high-speed digital stripline
interconnects in multi-layer PCB designs
Andreas Frejd
LiTH-ISY-EX-ET--10/0372--SE
Analysis and verification of routing effects on signal
integrity for high-speed digital stripline interconnects in
multi-layer PCB designs
by
Andreas Frejd
Bachelor Thesis
in Electronic Design
at
ISY – Department of Electrical Engineering,
Linköping Institute of Technology
LiTH-ISY-EX-ET--10/0372--SE
Supervisors:
Per-Olof Hansson
Digital HW Designer, ÅF
Alina Oramas Alvarez
Manager, TRX Design, Ericsson AB
Examiner:
Dr. J Jacob Wikner
Visiting associate professor, ISY, LiTH
c Andreas Frejd
July 2011, Stockholm
Linköpings tekniska högskola
Linköpings universitet
SE-581 83 Linköping
Avdelning, Institution
Datum
Division, Department
ISY
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Date
Språk
Rapporttyp
Language
Report category
Svenska/Swedish
Licentiatavhandling ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
Övrig rapport
2011-07-31
ISBN
—
LiTH-ISY-EX-ET--10/0372--SE
Serietitel och serienummer ISSN
Title of series, numbering
—
URL för elektronisk version
http://ep.liu.se
Titel
Title
Analys och verifiering av ledardragningens betydelse för signalintegriteten hos
digitala höghastighetsanslutningar på flerlagermönsterkort
Analysis and verification of routing effects on signal integrity for high-speed
digital stripline interconnects in multi-layer PCB designs
Författare Andreas Frejd
Author
Sammanfattning
Abstract
The way printed circuit board interconnects for high-speed digital signals
are designed ultimately determines the performance that can be achieved for
a certain interface, thus having a profound impact on whether the complete
communication channel will comply with the desired standard specification or
not. Good understanding and methods for anticipating and verifying this behaviour through computer simulations and practical measurements are therefore essential.
Characterization of an interconnect can be performed either in the time
domain or in the frequency domain. Regardless of the domain chosen, a
method for unobstrusively connecting to the test object is required. After
various different attempts it could be concluded that frequency domain measurements using a vector network analyzer together with microwave probes
will provide the best measurement fidelity and ease of use. In turn, this
method requires the test object to be prepared for the measurement.
Advanced computer simulation software is available, but comes with the
drawback of dramatically increasing the requirements on computational resources for improved accuracy. In general, these simulators can be configured
to show good agreement with measurements at frequencies as high as ten
gigahertz. For ideal interconnects, the simplest and, thus, fastest methods
will provide good enough accuracy. These simple methods should be complemented with the results from more accurate simulations in cases where the
physical structure is complex or in other ways deviates from the ideal.
Several practical routing situations were found to introduce severe signal
integrity issues. Through appropriate use of the methods developed in this
thesis, these can be identified in the design process and thereby avoided.
Nyckelord
Keywords
Signal integrity, PCB, digital interconnect, high-speed, microwave probing,
EM field solver
Abstract
The way printed circuit board interconnects for high-speed digital signals are
designed ultimately determines the performance that can be achieved for a
certain interface, thus having a profound impact on whether the complete
communication channel will comply with the desired standard specification
or not. Good understanding and methods for anticipating and verifying this
behaviour through computer simulations and practical measurements are
therefore essential.
Characterization of an interconnect can be performed either in the time
domain or in the frequency domain. Regardless of the domain chosen, a
method for unobstrusively connecting to the test object is required. After
various different attempts it could be concluded that frequency domain
measurements using a vector network analyzer together with microwave
probes will provide the best measurement fidelity and ease of use. In turn,
this method requires the test object to be prepared for the measurement.
Advanced computer simulation software is available, but comes with the
drawback of dramatically increasing the requirements on computational
resources for improved accuracy. In general, these simulators can be
configured to show good agreement with measurements at frequencies as
high as ten gigahertz. For ideal interconnects, the simplest and, thus, fastest
methods will provide good enough accuracy. These simple methods should
be complemented with the results from more accurate simulations in cases
where the physical structure is complex or in other ways deviates from the
ideal.
Several practical routing situations were found to introduce severe signal
integrity issues. Through appropriate use of the methods developed in this
thesis, these can be identified in the design process and thereby avoided.
i
Acknowledgements
“Long is the way, and hard, that out of hell leads up to light.”
–John Milton, Paradise Lost
Starting out in late March 2010, this thesis was expected to be finished before
the end of June the same year. Assuming the original plan to work out as
expected, this plan would probably have been reasonable. But, for various
reasons, it did not. Instead, in spite of all efforts put into the project, by
the end of June, only small progress had been made. In fact, the project
had reached a dead end, calling for a completely new approach to be taken,
ultimately suspending the project for over seven months, before it eventually
could be resumed and finished in March 2011.
Without a doubt, this thesis work has been all but straight forward, and along
the way quite a few people have been involved, a few of which deserves to be
acknowledged here.
First and foremost I’d like to thank my current manager Alina Oramas Alvarez, manager for TRX design at Ericsson, for giving me the opportunity to
perform this thesis at Ericsson in the first place. Not only has this thesis been
very instructive and interesting for me personally, but the subject is also very
relevant for contemporary digital design. I’d also like to thank Alina for her
patience and understanding when things haven’t gone as expected.
From a more technical point of view, I’d like to thank Johan Sjöström, designer radio, for his helpfulness and sharing of experience, especially within
microwave measurements, but also EM simulations. His knowledgeable, scientific approach has been very much appreciated.
Gunnar Larsson, designer hardware, also deserves to be mentioned here for all
his efforts with the layout of the test board and the accurate result thereof.
I’d like to thank Per-Olof Hansson, digital hardware designer, for supervising
this project, for many interesting discussions and for putting up with all my
questions throughout the project.
iii
iv
I also appreciate the efforts made by all others who have contributed in different ways, for instance Anna T Jansson, TRX principal design engineer, for assistance with creation of schematics for the test board, and Marek Buczkowski,
digital hardware designer, for general ideas and assistance regarding simulation software.
Thanks also to Rohde & Schwarz and Agilent Technologies for your flexibility
when lending instruments and equipment used in the project.
Finally, I’d like to thank all others for kindly showing interest in the project,
which I have found very inspiring.
Andreas Frejd, Stockholm, March 2011
Contents
1 Introduction
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Thesis scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Report outline . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
2
2 Theoretical background and signal integrity nomenclature
2.1 Printed circuit boards – Basic design considerations . . . . . .
2.1.1 The stack-up . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 The traces . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Vias and connections . . . . . . . . . . . . . . . . . . . .
2.2 Digital differential signaling . . . . . . . . . . . . . . . . . . . .
2.3 Signal propagation at high data-rates . . . . . . . . . . . . . . .
2.3.1 Frequency content of a digital signal . . . . . . . . . . .
2.3.2 Awareness of electrically large circuits . . . . . . . . . .
2.3.3 The behaviour of a lossless transmission line . . . . . . .
2.3.4 Impedance of a transmission line . . . . . . . . . . . . .
2.3.5 Lossy transmission lines . . . . . . . . . . . . . . . . . .
2.3.6 Line discontinuities and importance of matching . . . .
2.3.7 Non-ideal current return paths . . . . . . . . . . . . . .
2.4 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Crosstalk transmission line model . . . . . . . . . . . . .
2.5 Mode conversions . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Network analysis . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Scattering matrix . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Mixed-mode scattering parameters . . . . . . . . . . . .
2.6.3 Transfer scattering matrix . . . . . . . . . . . . . . . . .
2.6.4 De-embedding . . . . . . . . . . . . . . . . . . . . . . .
2.7 Time domain vs. frequency domain analysis . . . . . . . . . . .
2.7.1 TDR/TDT analysis – the time domain approach . . . .
2.7.2 S-parameter analysis – The frequency domain approach
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v
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Contents
3 Study of a product PCB – A first attempt of signal integrity
analysis
39
3.1 Analyzing signal integrity of a PCB for an existent product –
the original plan . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 PCB selection and analysis – finding critical nets . . . . . . . . 40
3.3 Data management . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 Computer simulation software – selection and configuration . . 42
3.5 Preparing for the measurements – finding a method for accurate
and efficient probing . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5.1 Connecting to the PCB using semi-rigid cables . . . . . 43
3.5.2 Using microwave probes – a superior method? . . . . . . 44
3.6 VNA calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6.1 Calibration methods . . . . . . . . . . . . . . . . . . . . 46
3.6.2 Test environment set-up and inital calibration . . . . . . 48
3.6.3 The OSM calibration algorithm . . . . . . . . . . . . . . 52
3.6.4 LRM calibration algorithm . . . . . . . . . . . . . . . . 55
4 Designing a test board for the purpose
57
4.1 Selection of relevant test cases . . . . . . . . . . . . . . . . . . . 57
4.1.1 Test port characterization and reference traces . . . . . 58
4.1.2 Crosstalk test structures . . . . . . . . . . . . . . . . . . 59
4.1.3 Via effect . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1.4 Miscellaneous test cases – practical routing situations . 61
4.2 Testboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3 Board characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4 A new analysis methodology . . . . . . . . . . . . . . . . . . . . 67
4.5 A new application to aid the new analysis . . . . . . . . . . . . 67
4.6 Probe characterization and the inital measurements . . . . . . 68
4.7 Selecting and configuring an EM simulator . . . . . . . . . . . . 70
4.7.1 Momentum configuration for good agreement with measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.8 A few words on TDR/TDT set-up . . . . . . . . . . . . . . . . 76
4.8.1 A first comparison between simulated and measured responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5 Analysis of the routing effects
5.1 Impact from vias . . . . . . . . . . . . . . . . . .
5.2 Crosstalk behaviour . . . . . . . . . . . . . . . .
5.3 Evaluation of various practical routing situations
5.3.1 Non-solid reference planes . . . . . . . . .
5.3.2 Change of differential pair spacing . . . .
5.3.3 Serpentine delay line . . . . . . . . . . . .
5.4 A quick comparison with a faster simulator . . .
5.4.1 Simulating a straight stripline . . . . . . .
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Contents
5.4.2
5.4.3
5.4.4
vii
Crosstalk simulations . . . . . . . . . . . . . . . . . . .
Via models . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations . . . . . . . . . . . . . . . . . . . . . . . . .
6 Conclusions and future work
6.1 What have been learned so far?
6.1.1 Simulation techniques .
6.1.2 Measurement methods .
6.2 For the future . . . . . . . . . .
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Bibliography
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Abbreviations
109
List of Figures
113
1
Introduction
1.1
Background
With a trend towards more sophisticated integrated circuits, with more connections and increasing data rates, the requirements on the printed circuit
board, PCB, design have become ever so important in order to guarantee reliable transmission of digital data between subsystems on a single circuit board.
But as data rates increase, the interconnects begin to exhibit high-frequency
behaviour and can no longer be described as independent, lumped conductors
with evenly distributed currents and voltages. For a signal traveling on such
interconnect the actual surrounding, in terms of material variations and adjacent voltage signal levels, may have a profound impact on its quality, more
often referred to as its integrity. As speed and, thus, frequency increase, this
impact will become more pronounced, resulting in a clear deterioration of the
signal integrity during its propagation in the interconnect. This deterioration could for instance be attenuation of the signal voltage level or unwanted
voltage variation due to interaction with neighbouring signals.
In order to cope with the steadily increasing speed requirement, the design
team has to have full control over these high frequency phenomena, not only
by knowing their causes and by being able to predict them early on in the
design phase, but also in terms of methods for verification of these issues,
both with the aid of computer simulations and with real world measurements
on a fabricated board.
These statements may sound obvious, but the way they can be accomplished
is not, as will be demonstrated in this report.
1.2
Thesis scope
Signal integrity is a large and fast growing field within contemporary PCB
design for digital circuitry. This thesis aims to find methods for investigating
1
2
Chapter 1. Introduction
how the interconnects between circuits used by on-board high-speed electrical
signaling systems may influence the overall signal integrity, including prediction through computer simulations and verification through measurements.
The focus here will be on small-scale issues, such as how a single conductor,
or pair of conductors, is affected by its surrounding environment and how it
affects other conductors in close proximity, rather than how these small scale
effects ultimately interact in a working system. Being restricted to signal
integrity issues caused by the interconnect, the impact of connecting circuits
is, thus, not considered in this project.
Most signaling systems currently used for high-speed digital signaling, such
as LVDS (low-voltage differential signaling) and CML (current mode logic),
are differential systems, and therefore the outcome of this project should be
applicable for such systems, although single-ended systems also should be
evaluated for reference.
This thesis tries to answer the following questions:
• What routing properties, such as distance between adjacent conductors and usage of vias, are most critical for accurate characterization
of high-speed interconnects in order to achieve reliable prediction and
verification of signal integrity issues?
• What measurement methods should be used in order to characterize
these signal integrity issues?
• How well will computer simulations predict the same results?
In order for the results to be relevant, the computer simulations and practical
measurements had to be performed on a multi-layer PCB, typically used in
an advanced digital layout.
1.3
Report outline
This report does not expect the reader to have any prior knowledge of signal
integrity, only a basic understanding of circuit theory is sufficient. For this
reason, after this introduction, a basic theoretical introduction to PCB design
and transmission line theory will follow. Besides serving as an introduction,
this chapter also presents most of the terminology used throughout this report.
For the reader well accustomed with these topics, this chapter might as well
be ignored.
In the following chapter the original plan for analyzing a PCB for a current
product will be motivated. A strategy for data management will be explained
1.3. Report outline
3
and the initial measurement results will be presented. Due to the nonsatisfying outcome from these measurements, the new approaches taken, will be
motivated.
Generally speaking, as the original plan did not work out as expected, a
completely new approach to the problem had to be taken, including the design
of a test board, specifically made for the purpose. The process of designing this
board will be described in chapter 4. The inital measurement- and computer
simulation set-up and results will also be presented in this chapter.
In chapter 5, with all the details sorted out, the results from the simulations
and measurements on the test board will finally be presented.
The lessons learned from this project, together with suggestions on how this
knowledge can be used will be summarized in chapter 6. Here, future work
on this topic will also briely be discussed, which concludes this report.
2
Theoretical background and signal integrity
nomenclature
2.1
Printed circuit boards – Basic design
considerations
For more than half a century [1] printed circuit boards, PCBs 1 , have been
the basic building block for electronic products, by providing an efficient way
to interconnect electronic components to form an electronic system. Even
though the design of modern PCBs conceptually is still the same, fabrication
processes, materials and design rules have evolved in a multitude of different
directions. It is clearly beyond the scope of this thesis to evaluate all fabrication parameters in any further detail. Here, a very general approach is taken,
with the purpose of giving the reader unfamiliar with PCB design a notion of
the basic terminology and concepts, used throughout this report.
2.1.1
The stack-up
In order to facilitate interconnection of many components, placed on a limited area, conductors are normally placed, or routed, in more than two layers;
creating a multilayer PCB design2 . In such a design, not all layers are necessary signal layers. Often, whole planes are dedicated ground- or power planes,
which is the recommended approach for improved signal integrity performance,
especially for high speed designs. How the different layers are arranged and
what layers that are used, is often referred to as the stack-up. A simple example of a stack-up is depicted in figure 2.1.
1
Sometimes also referred to as printed wiring boards, PWBs.
The PCB is then referred to as a multilayer board, MLB. By definition a multilayer
board has three or more circuit layers [1].
2
5
6
Chapter 2. Theoretical background and signal integrity nomenclature
Pre-preg
Etched
copper
Copper
L1
L2
L3
Laminate
sheet
L4
L5
Figure 2.1: A simple example of a five-layer PCB stack-up.
Just as the name stack-up implies, the PCB is made up of a stack of layers,
basically consisting of a combination of fiber mats and laminate sheets3 [2].
The fiber mats often consists of a weave-like structure of fiber threads preimpregnated with a resin, and are used to strengthen the structure. Because
of this structure, they are simply called the pre-preg. The internal structure
of the laminate sheets are also made up of pre-preg, but this pre-preg is fully
cured, unlike the pre-preg used between the different laminate sheets, which is
only partially cured. Moreover, the laminate sheets have copper foil attached
to one or both of the outer sides. In the fabrication process the stackup is
heated under pressure and the partially cured prepreg will bind to the laminate
sheets [2], creating a solid structure.
As already mentioned, many different materials exist for this process, and
choices made will have a profound impact on the electrical properties of the
board. The by far most common group of standardized laminate systems is
the flame retardant 4, FR-4 4 [1], which is based on an epoxy resin, normally
with glassfiber reinforcement. For the boards studied in this thesis, halgon
free FR-4, HFFR-4 , was used.
Electrically, the laminate sheets and pre-preg surrounding the conductors, are
insulators and therefore called dielectric. The dielectric is primary characterized by how much resistance an applied electric field will encounter, expressed
by its permittivity. For free space the permittivity, 0 , has the value shown in
equation (2.1) [3].
0 =
1
· 10−9 [F/m]
36π
(2.1)
For other media, such as the dielectric in a PCB, the permittivity is normally
given in relation to 0 , by the relative permittivity constant, r , defined in
3
The laminate sheets are sometimes simply called cores.
FR-4 – Flame retardant 4 – A standard defined by N.E.M.A. - National Electrical
Manufacturers Association.
4
2.1. Printed circuit boards – Basic design considerations
7
equation (2.2) [3].
, r 0
(2.2)
The permittivity is a fundamental property of the PCB dielectric, determining
the behaviour of a signal traveling in an adjacent conductor. For instance, for
a conductor surrounded by a homogenous dielectric, the propagation speed of
a signal is determined by the simple relation shown in equation (2.3)5 .
v0
vp = √
r
(2.3)
where v0 is the speed of light in vacuum.
A higher level of resin relative to glass yields lower permittivity, which in
general is better for high-speed PCB design. High permittivity will for instance
require a thicker stackup for a given impedance and increase the capacitive
coupling between conductors [2].
The laminate sheets tend to have a lower resin content than the prepreg [2],
which, in other words, means that the laminates usually have a slightly higher
permittivity than the prepreg sheets.
Another fundamental parameter used for electrically characterizing the dielectric, the loss tangent, deserves to be mentioned here as well, but will be
described in more detail in section 2.3.5.2.
2.1.2
The traces
The conductors, or traces, in a PCB normally consist of copper and are created
through an etching process of the copper foils attached to laminates. In most
cases, the thickness of the copper foil is expressed in ounces, that represent the
weight of copper per square foot of surface area, where the 0.5 ounce, 1.0 ounce
and 2.0 ounce are the most common ones [4]. Generally, it is advantageous to
use thin traces, as it, nonintuitively, will reduce losses and coupling and also
improve impedance control [2].
Due to different fabrication methods, the traces may exhibit large variations
in shape and in surface roughness (which will be further explained in section
2.3.5). As pointed out in [2], it is of great importance to be aware of the physical difference between traces due to fabrication, when analyzing the results
of any signal integrity analysis.
5
In general, another fundamental property, the relative permeabilty, µr , would also exist
under the square root. However, for non-magnetic materials it will be equal to one [3] and
is left out here.
8
Chapter 2. Theoretical background and signal integrity nomenclature
Trace
(etched)
Dielectric
Reference
plane
(a) Microstrip.
(b) Stripline.
Figure 2.2: The two basic types of traces used in PCB design.
For a conventional PCB design, traces can be divided into two basic categories,
based on where the traces are placed; either on the surface, as in the microstrip
case shown in figure 2.2a, or buried within the board, as in the stripline case,
shown in figure 2.2b. In fact, microstrip and stripline are two transmission
line types. Transmission line theory will be discussed further in section 2.3.
The interconnects analyzed in this thesis will be striplines.
2.1.3
Vias and connections
In order to interconnect signals between different layers in a multilayer board,
vertical connections between the layers, known as vias 6 , are used.
Vias are normally either through hole, buried or blind. These three different
kinds are displayed in figure 2.3. Traditionally, through hole vias have always
been used, but as a result of the increasing demands on package density [1],
buried- and blind vias were introduced, allowing traces in other layers to pass
over or under the via. Most vias will be drilled between a standard number of
layers, rather than only between the layers to be connected, leaving a stub7 ,
an example of which also can be seen in figure 2.3. As will be shown later,
this stub may have a significant impact on high-speed signals.
For each layer there is a ring of copper, called pad, that is used to make contact
with traces of a certain layer. In some designs, especially on thick PCBs, these
pads are left for unconnected layers in order to anchor the via in the stackup
[2]. These unconnected pads are then referred to as non-functional pads. This
may, however, increase the self-capacitance of the via [2]. In order to allow
signal vias to pass through ground- and power planes, a clearance hole in the
plane is created, referred to as an anti-pad.
For high-speed signals, as will be described further in this report, the via may
play a critical role, as it has very different electrical properties compared to
6
7
The term Via is an abbreviation for Vertical Interconnect Access.
This stub can be removed by precision backdrilling.
2.2. Digital differential signaling
9
Figure 2.3: Three different via types.
the traces. In addition to the stub-effect, it can briefly be mentioned that,
due to the lack of solid dielectric surrounding, the signal may experience losses
and additionally, also introduce, or be subject to, coupling.
The devices mounted on the outer edges of a PCB, be it a surface mounted
discrete component or a large integrated circuit, are normally soldered to a
conductive area, usually made up of goldplated copper. These metal areas
are also commonly referred to as pads. To meet the requirements of different
circuit types there exist quite a few different PCB pads. These are, however,
not analyzed further in this thesis and a more detailed description is therefore
left out here. Instead, the interested reader is referred to [1, chapter 3].
2.2
Digital differential signaling
Since early 1960s differential pairs have been used for transferring digital signals in high-speed interconnects and is nowadays used in virtually all highspeed serial links [5]. A differential signal is represented by the voltage difference between two nodes, having the same size, but opposite sign with respect
to a fixed potential, as opposed to a single-ended signal, simply represented
by the voltage difference between a single node and a fixed potential. In a
strict sense, the two nodes should have equal impedance to this potential [6].
The voltage difference is called differential mode, DM , and is, thus, defined
10
Chapter 2. Theoretical background and signal integrity nomenclature
as UDM = U1 − U2 . Correspondingly, the common mode, CM , is defined as
the voltage level common to the two nodes as UCM = (U1 + U2 )/2.
In spite of the requirement of two traces to be routed and that extra care
must be taken for making these the same length [7], differential signaling
comes with several important advantages. One advantage, often mentioned,
is the reduced sensitivity against sources of disturbance common to the two
traces8 , as the two conductors within the pair then will be contamined with
the same disturbance, not affecting the voltage difference. In a similar fashion,
a differential signal also affects adjacent signals to a less extent [6].
From a signal integrity perspective, a fundamental advantage of using differential pairs are the virtual reference plane between the conductors within the
pair, providing a continuous reference [9], the importance of which will be
explained in the following sections.
Other advantages include the doubled voltage swing and suppression of even
order harmonics caused by non-linearities.
2.3
Signal propagation at high data-rates
As was briefly mentioned in section 1.1, at higher data-rates the characteristics
of the actual interconnect becomes of great importance for the signal integrity,
but why is this not true for lower data-rates?
In order to understand these issues, the signals traveling on the interconnect
has to be considered voltage- and current waves, propagating with finite speed
on the interconnect, generating variations in the surrounding electromagnetic
field. Using this approach, the interconnect is called a transmission line.
Somewhat simplified, with the transmission line perspective, not only the final
value due to a signal change can be calculated, but all transients that lead to
that value can be obtained. In fact, all electrical signals can be described in
this way, but, since computationally much more involved, it is important to
understand when use is appropriate. This will be motivated, before the basic
theory behind high speed signal behaviour will be explained.
2.3.1
Frequency content of a digital signal
First, how can the data rate of a digital signal be related to frequency? In
order to make a theorethical approximation, assume the digital signal can be
approximated as a trapezoidal waveform, as shown in figure 2.4 and expressed
8
According to [8, p. 115] this argument is not true for PCBs, but only in free space.
2.3. Signal propagation at high data-rates
11
Figure 2.4: Trapezoidal approximation of a digital signal.
Figure 2.5: Magnitude spectrum of trapezoidal pulse train approximation,
plotted in log-log scale.
by a fourier series, in general given by:
∞
X
v(t) = c0 +
|c+
n | cos n
n=1
2πf t
+ arg{c+
n}
T
(2.4)
If it is further assumed that the rise time, τr , is equal to the fall time, τf , it
can be shown that the one-sided complex fourier series expansion coefficients
can be expressed as [3]:
|c+
n|
τ
= 2A
T
sin(nπτ /T ) sin(nπτr /T ) nπτ /T nπτ /T n 6= 0
(2.5)
r
and
c0 = A
τ
T
n=0
(2.6)
where A is the signal amplitude, τ is the pulse width and T is the pulse period,
as annotated in figure 2.4. The fundamental and harmonics of the fourier series
exist at the discrete frequencies for which f = n/T . By neglecting that for
the moment and substituting that expression into equation (2.5), a continuous
12
Chapter 2. Theoretical background and signal integrity nomenclature
frequency spectrum of the signal can be obtained, the magnitude function of
which is plotted in figure 2.5 in a log-log scale9 . From this plot it can be
seen that the influence of the high frequency components rapidly decays after
1/(πτr ). Based on this observation, the bandwidth required to accurately recreate a digital signal is in this thesis assumed to be given by equation (2.7)
[3].
BW =
1
τr
(2.7)
This rule of thumb, corresponding to approximately three times the 1/(πτr )
frequency, is commonly used in the industry. Sometimes, however, it is considered too moderate and half this frequency is used instead [10].
2.3.2
Awareness of electrically large circuits
Using the concept of fourier series, the digital signals, described as voltageand current waves, can be considered to be made up of simple single-frequency
sinusoidal waves, as was shown in the previous section. For instance, the
voltage of a single sinusoidal voltage wave with amplitude V , propagating
with constant speed along an ideal interconnect can be described as:
v(x, t) = V cos(ωt − βx)
(2.8)
where t is the time, x is the position along the line, ω is the angular frequency
and β is a constant, known as the phase constant.
A wavelength represents the distance that a sinusoidal wave must travel in
order to change phase by 360◦ , or 2π 10 .
Since the phase shift for one wavelength is 2π, β is given by:
βλ = 2π ⇔ β =
2π
λ
(2.9)
By observing a common point on the wave, the argument must be constant as
shown in equation (2.10a). Rewriting equation (2.10a) as shown in equation
9
In this figure an asymptot is also plotted, based on the fact that |(sin x)/x| is approximately equal to one for small x and 1/|x| for large x.
10
Strictly, this only applies to uniform plane waves, but as other waves have similar
characteristics this is valid for other waves as well [3].
2.3. Signal propagation at high data-rates
13
(2.10b) and then differentiating with respect to t, the velocity of propagation
is obtained in (2.10c), where the last equality comes from equation (2.9).
ωt − βx = constant
⇔x=
v=
(2.10a)
ω
constant
t+
β
β
(2.10b)
∂x
ω
v
= = λf ⇔ λ =
∂t
β
f
(2.10c)
The last equation, equation (2.10c), relating frequency and wavelengths, is
fundamental in order to understand when use of transmission line theory is
appropriate.
So far it has been said that signal integrity issues may occur at “higher datarates”. Though to some extent correct, it is indeed a very vague way of putting
it. In fact, these issues are not directly related to a particular data rate,
but, as was shown in section 2.3.1, the frequency content of a signal is. By
increasing the data-rate, the important frequency components of the signal
will also move up in frequency, and, as indicated by equation (2.10c), for a
constant propagation speed, the wavelengths will decrease accordingly. When
the wavelengths approaches the physical lengths of the conductors, the values
of the signal voltages and currents can no longer be considered equal along the
interconnect, nor to change instantaneously. As will be shown in the following
sections, the behaviour of the actual conductors becomes critical.
Rather than using the physical size when characterizing an interconnect, the
term electrical dimensions is used, which is the physical size in terms of wavelengths. For instance, a circuit of which lumped circuit models do not apply,
is referred to as electrically large. As a widely used rule of thumb, a circuit or
interconnect is considered electrically large when its largest dimension, L , is
larger than one tenth of a wavelength [3]:
L >
1 v
10 fmax
(2.11)
Using fmax = 1/τr from section 2.3.1 and L = vTD , equation (2.11) can be
rewritten as:
1
(2.12)
TD > τr ⇔ τr < 10TD
10
From equation (2.12) it can be seen that for a signal with rise times smaller
than about ten one-way propagation delays of the line, then transmission
14
Chapter 2. Theoretical background and signal integrity nomenclature
line effects is of importance. For digital signaling on an electrically large
interconnect, these effects are especially important during a signal change,
where the transient behaviour may ruin the signal integrity. For an electrically
small interconnect, on the other hand, these transients are neglectable.
2.3.3
The behaviour of a lossless transmission line
Even though the use of the transmission line equations is rather complicated,
their actual derivation can be motivated in a straight forward manner, as will
be described here. It should be emphasized that this is just a motivation,
the intention of which is not to provide the mathematical rigor of a complete
electrodynamic derivation, but to provide the reader with the basic concepts
required for understanding most high-speed signal integrity issues.
y
+
+
V
-
-
+
-
+
-
+
-
y
+
I
HT
ET
-
I
x
x
z
z
(a) Electric field in transverse.
(b) Magnetic field in transverse.
Figure 2.6: Electric- and magnetic fields.
Consider the two conductors as depicted in figure 2.6, extended in x-direction.
If a voltage is applied (figure 2.6a), an electric field will occur, that is in
transverse to the conductor extension, i.e. in the yz-plane. The amount of
charge stored is known as the capacitance of the conductor, which can be
measured per unit length as Farads per meter [F/m]. The value is obviously
dependent on the properties of the conductor.
Similarly, if a current is applied, a magnetic field will occur (figure 2.6b),
which can be characterized as the inductance per unit length, as Henries per
meter [H/m].
Putting these two observations together, a first order lossless model of the
actual transmission line can be formed, consisting of an infinite series of identical elements. This model is depicted in figure 2.7, where l and c are the distributed per-unit-length inductances and capacitances, respectively and ∆x is
the length of each section.
2.3. Signal propagation at high data-rates
l x
15
l x
l x
c x
c x
c x
x
Figure 2.7: First order distributed transmission line model.
I(x+ x,t)
I(x,t)
+
V(x,t)
l x
+
c x
-
V(x+ x,t)
-
Figure 2.8: Lossless transmission line per-unit-length equivalent circuit.
Application of Kirchhoff’s voltage law, KVL, to a single section as shown in
figure 2.8, where the voltage and the current is a function of both time and
position on the transmission line, yields:
V (x + ∆x, t) − V (x, t) = −l∆x
∂I(x, t)
∂t
(2.13)
⇔
V (x + ∆x, t) − V (x, t)
∂I(x, t)
= −l
∆x
∂t
The left hand side of equation (2.13) is the well-known definition of a derivative. Thus, by letting ∆x → 0, the first transmission line equation, describing
the voltage along the line, can be obtained as:
∂V (x, t)
∂I(x, t)
= −l
∂x
∂t
(2.14)
By applying Kirchhoff’s current law, KCL, the second equation, describing
16
Chapter 2. Theoretical background and signal integrity nomenclature
the current along the line, can be obtained in a very similar fashion:
I(x + ∆x, t) − I(x, t) = −c∆x
∂V (x + ∆x, t)
∂t
(2.15)
⇔
I(x + ∆x, t) − I(x, t)
∂V (x + ∆x, t)
= −c
∆x
∂t
⇒
∂I(x, t)
∂V (x, t)
= −c
when ∆x → 0
∂x
∂t
(2.16)
These linear differential equations, as given by equations (2.14) and (2.16), and
also known as the Telegrapher’s equations, completely describes the behaviour
of a lossless transmission line. As can be seen from these equations, all the
structual information about the transmission line must be contained in the
per-unit-length parameters, l and c, and nowhere else. Thus, in order to make
any use of these equations the per-unit-length parameters must be computed.
However, the exact values of these parameters are not available in closedform [3]. Instead, numerical methods, implemented by computer simulation
software, is normally used.
Equations (2.14) and (2.16) both contain line voltages and currents, and they
are said to be on coupled form. In order to find the time domain solution,
one normally start by uncoupling them, which for instance can be done by
differentiating equation (2.14) with respect to x and equation (2.16) with
respect to t as:
∂ 2 V (x, t)
∂ 2 I(x, t)
=
−l
∂x2
∂t∂x
(2.17)
∂ 2 V (x, t)
∂ 2 I(x, t)
= −c
∂x∂t
∂t2
(2.18)
Substituting equation (2.18) into equation (2.17) yields:
∂ 2 V (x, t)
∂ 2 V (x, t)
=
lc
∂x2
∂t2
(2.19)
Similarly, differentiating equation (2.14) with respect to t and equation (2.16)
with respect to x yields:
∂ 2 I(x, t)
∂ 2 I(x, t)
=
lc
∂x2
∂t2
(2.20)
2.3. Signal propagation at high data-rates
17
The time domain solution to the uncoupled equations (2.19) and (2.20) is
given by [3]:
V (x, t) = V + t −
x
v
+V− t+
1 +
x
I(x, t) =
V
t−
ZC
v
x
v
(2.21a)
1 −
x
−
V
t+
ZC
v
(2.21b)
p
where ZC = l/c is the characteristic impedance of the transmission line
(as will be described in section 2.3.4). The propagation speed is given as
v = 1/(lc). V + represents the forward traveling voltage wave11 , whereas V −
corresponds to the wave traveling in the opposite direction.
2.3.4
Impedance of a transmission line
By definition, the characteristic impedance of a transmission line is equal to
the ratio of the propagating voltage and current waves on the line. For a
lossless transmission line, the characteristic impedance can also be shown to
be given by equation 2.2212 .
s
ZC =
l
c
(2.22)
Approximate expressions recommended by IPC13 for the characteristic impedance
of a single-ended microstrip and stripline are available. The expression for
the stripline case is shown in equation (2.23) [11], where h is the dielectric
thickness below the signal trace to the plane, w is the line width, b is the
plane-to-plane spacing and t is the metal thickness.
60
2b + t
Z0 = √ ln
r
0.8w + t
2.3.5
(2.23)
Lossy transmission lines
So far, only ideal lossless conductors have been described. Practical transmission lines are, however, not lossless. There are several contributors to these
losses, here divided into two groups; losses due to the actual conductors and
losses due to the surrounding dielectric.
11
This is evident from the equation; as t increases, x must also increase in order to keep
the argument constant.
12
In some literature the characteristic impedance is denoted Z0 . In this thesis ZC is used.
13
Institute for Interconnecting and Packaging Electronic Circuits.
18
Chapter 2. Theoretical background and signal integrity nomenclature
2.3.5.1
Conductor losses
Two important and closely related contributors to the conductor losses are
the skin effect and surface roughness.
W
t
(a) At DC.
(b) At higher frequencies.
Figure 2.9: Skin effect. At DC the current will be evenly distributed across
the crossectional area of the conductor, whereas at higher frequencies, the
current tends to be concentrated closer to the edges.
The skin effect phenomena is depicted in figure 2.9. Figure 2.9a shows how,
at zero or very low frequencies, the whole crossectional area of the conductor
is utilized for conducting charges, creating a low resistive path, whereas at
higher frequencies (figure 2.9b), the charge distribution is moved towards the
edges, thereby increasing the resistance of the conductor, which in turn results
in higher losses.
r
[
/m]
10 dB/dec
rdc
fbreak
f [Hz]
Figure 2.10: Conductor resistance variation due to skin effect as a function of
frequency.
As shown in figure 2.10, this loss, or rather increase in resistance, is approximately proportional to the square root of frequency, therefore increasing by
10 dB/dec in a logarithmic scale, after a certain breakpoint frequency [3].
It should also be noted that due to the skin effect, thicker traces may not
necessarily have a loss advantage over thinner ones [2].
2.3. Signal propagation at high data-rates
19
Skin depth
/roughness
[ m]
20
15
Skin depth copper
Average roughness for
0.5 oz commercial foil
10
5
0
0.01
0.1
1
10
100 f [GHz]
Figure 2.11: Skin depth and surface roughness versus frequency for commercially available 0.5 oz copper foil.
Moreover, the outer edges of the traces in a fabricated PCB will be far from
smooth. In fact, the copper is usually deliberately roughened to ensure adhesion to the dielectric [9]. At lower frequencies, this is of little concern, but
due to the skin effect, at higher frequencies, all of the current will flow in the
rough part, where the ac resistance is larger [2], resulting in additional losses.
Inspired by [1], figure 2.11 shows an example which demonstrates how for frequencies approximately exceeding five gigahertz, all the current will flow in
the rough part for commercially available 0.5 oz copper foil14 .
Another closely related effect that cause losses is imperfect trace thickness due
to fabrication process. Generally, this will not have as much impact as the
imperfectness due to surface roughness [2].
2.3.5.2
Dielectric losses
High frequency phenomenas that result in losses are not limited to effects in
the actual conductors. Also losses in the dielectric must be considered.
Each time the electric field changes direction, the bound charges of the dipoles
in the dielectric will try to align with the new field. When the dielectric is
unable to completely do so, losses will occur in the conductors [3, 9], an effect
that will become apparent at higher frequencies. To account for this frequency
dependence, the permittivity can be described as [3]:
(ω) = 0 (ω) + j00 (ω)
(2.24)
14
This is by the way the same copper thickness as used in the testboard described in
chapter 4.
20
Chapter 2. Theoretical background and signal integrity nomenclature
where 0 is related to the stored energy in the medium and 00 is related to the
actual loss of energy in the medium.
More commonly, the loss of a dielectric material is expressed by its loss tangent, defined in equation (2.25), where σ is the free charge conduction.
tan δ ,
ω00 + σ
ω0
(2.25)
This report will not go any further in this direction, and here it suffices to say
that the loss tangent, as the name implies, is a measure of the loss that occur
within the dielectric and for the frequencies and materials studied here, it can
normally be considered constant.
However, in a fabricated board, the permittivity can vary significantly, due to
the fiber-weave inside the dielectric [9, 12] (see section 2.1.1). This fiber-weave
effect can therefore be of great importance for the performance of high-speed
digital interconnects15 .
Though not practically possible, by routing the traces diagonally, the fiberweave effect can be eliminated. This has been verified by another project
at Ericsson. From this test, it was also concluded that the effect of surface
roughness, previously described, is much larger than this effect.
2.3.5.3
Inclusion of losses in Telegrapher’s equation
I(x+ x,t)
I(x,t)
+
r x
V(x,t)
-
l x
c x
+
g x
V(x+ x,t)
-
Figure 2.12: Lossy transmission line per-unit-length equivalent circuit.
As has been shown so far in sections 2.3.5.1 and 2.3.5.2, practical transmission
lines are not lossless. Up to this point only the development of the Telegrapher’s equations for lossless transmission lines have been shown. In order to
account for losses in this model, a series resistance, r, representing conductor
losses and a shunt conductance, g, representing dielectric losses, can be added
to each section of the lossless model, as depicted in figure 2.12. Using the
same approach as for the lossless case, the uncoupled lossy transmission line
15
see [13] for a practical demonstration
2.3. Signal propagation at high data-rates
21
equations can be derived. However, the inclusion of losses will significantly
complicate their solution [3]. In practice, as has been shown in previous sections, these losses are also frequency dependent, which cannot be accounted
for in a closed-form solution of these equations [3].
The approach normally taken in order to evade this difficulty is to use a
frequency domain solution known as the phasor method, where a sinusoidal
inputsignal in steady state is assumed16 . Equations (2.14) and (2.16) for the
lossless case can then simply be written as:
dV (x)
= −zI(x)
dx
(2.26a)
dI(x)
= −yV (x)
dx
(2.26b)
where z = jωl and y = jωc. If losses are to be included r and g are simply added to z and y, respectively. By differentiating and substituting the
uncoupled form can be obtained as:
d2 V (x)
− zyV (x) = 0
dx2
(2.27a)
d2 I(x)
− yzI(x) = 0
dx2
(2.27b)
The solutions to equation (2.27) is now given by [3]:
V (x) = V + e−αx e−jβx + V − eαx ejβx
I(x) =
V + −αx −jβx V − αx jβx
e
e
−
e e
ZC
ZC
(2.28a)
(2.28b)
where the characteristic
impedance,
ZC , and the propagation constant, γ, is
p
p
√
z/y
=
(r
+
jωl)/(g
+ jωc) and γ = zy = α + jβ =
given
as
Z
=
C
p
(r + jωl)(g + jωc), respectively. α is known as the attenuation constant,
which obviously is equal to zero in the lossless case. β is the phase constant as
mentioned in section 2.3.2. V + and V − can here be seen as undetermined constants for the forward- and backward traveling waves respectively, determined
by the source and load impedances.
16
This means that the “full” solution, i.e including both transient and steady state, as in
the time domain case, is no longer obtained [3].
22
Chapter 2. Theoretical background and signal integrity nomenclature
2.3.6
Line discontinuities and importance of matching
As has been already mentioned, in practice, the transmission line medium
is never perfectly homogenous. Any change in the medium can be seen as
a discontinuity, causing reflections, signal loss and perhaps interference with
consecutive data bit in a practical system. Obviously, imperfect terminations
at the end of the transmission line will also result in the same phenomena.
The characteristic impedance of a transmission line is defined as the ratio
between the forward traveling voltage- and current waves, as was mentioned
in section 2.3.4. When the waves hit a line discontinuity, represented by a
second transmission line with different characteristic impedance, part of the
forward traveling wave must be reflected in order to fulfill this relation for the
second transmission line [14].
The ratio of the reflected voltage, V − , to the incident voltage, V + , is called
the reflection coefficient, which consequently is defined as:
Γ,
V−
V+
(2.29)
Generally, it can be shown that the reflection coefficient is equal to [9, 14]:
Γ=
Z2 − Z1
Z2 + Z1
(2.30)
where Z1 and Z2 are arbitrary (complex) impedances.
Figure 2.13: Impedance discontinuity – example circuit.
As a simplistic example of a line discontinuity, consider the circuit depicted in
figure 2.13, where the source- and load impedances, Rs and RL , are assumed
to be equal, and where the two transmission line segments are of equal length,
with different purely resistive characteristic impedances, Z1 and Z2 . It is
further assumed that the termination resistances have a lower resistance than
Z1 , and that the opposite is true for Z2 . A possible example of the reflected and
transmitted voltages for this scenario, when an ideal voltage step is applied, is
shown in figure 2.14, where each voltage level simply can be calculated using
equations (2.29) and (2.30).
2.3. Signal propagation at high data-rates
(a) Reflected voltage over RS .
23
(b) Transmitted voltage over RL .
Figure 2.14: Example response for circuit shown in figure 2.13, assuming Z1
and Z2 to be purely resistive and that Z2 < Rs = RL < Z1 .
For instance, since Z1 is greater than RS , a positive reflection initially occurs
at the input, resulting in a voltage that is added to the applied voltage, and
therefore it first appears greater than the final steady state value in figure
2.14a. What is not reflected will obviously propagate through Z1 until it
reaches Z2 , where a negative reflection will occur, the impact of which will
appear at the input after two times the delay of the first transmission line
segment. This way, reflections will continue until the steady state value has
been reached.
Ideally, from this reasoning is understood that each conductor should be of
constant impedance and perfectly terminated, in order to avoid reflections.
However, a digital system has so many connections that designing perfect
impedance matching networks for all traces, is not practically possible, unlike
for instance a RF-system [8]. Instead, the system must be designed to have a
tolerance for impedance mismatches.
When analyzing a certain interconnect it is often of interest to be able to locate
these impedance discontinuities. Then, a similar approach as was shown in
the simple example above is used, called time domain reflectometry, TDR.
This method will be described in more detail in section 2.7.1.
2.3.7
Non-ideal current return paths
It is very easy to only focus on the signal trace, forgetting about one fundamental concept of circuit theory; any current injected to a system must return
to the source and it will do so through the path of least impedance. Thus, the
characteristics of the current return path, through the reference plane, often
in combination with ground vias, are as important as the trace and signal vias
themselves.
24
Chapter 2. Theoretical background and signal integrity nomenclature
Non-ideal current return paths occurs for instance when a discontinuity in the
reference plane causes return current to diverge from the ideal path, which
results in increased loop area, and, thus, increased inductance. If the delay of
this path is longer than the rise- and fall times of the the signal, the signal
waveform will be severly distorted [9]. This same phenomena occurs in via
structures, where a ground via is placed at a certain distance away from a
signal via. Another example of non-ideal return paths occurs when the return
current must flow through a region of increased impedance [9].
2.4
Crosstalk
As was explained previously in section 2.3.3, every electrical signal propagating
on an interconnect will cause electromagnetic field variations. It is not difficult
to imagine that there might be electromagnetic coupling between two or more
conductors placed close enough in space. Such unintended electromagnetic
coupling between conductors that are in close proximity are referred to as
crosstalk.
Crosstalk will affect the fundamental behaviour of the transmission line, as
both the characteristic impedance and propagation velocity of a line will
change [3, 9].
Due to its electromagnetic nature, the amount of coupling is clearly a function of the distance between the conductors. For a PCB design, crosstalk is
expected to occur both between traces inside the board and between closely
spaced vias.
Interestingly, of greater importance might not be crosstalk from other signal
traces, but from the reference plane due to non-ideal return paths for the
other signals. As a consequence, crosstalk may occur between traces that
are centimeters apart, since the return path may be in close proximity to
the conductor, or their return paths may even coincide. For this case, the
crosstalk regions will become a bit more tricky to locate, since the current
return paths must be anticipated. For differential signals, as is studied in this
thesis, it should be noted that this effect will be clearly reduced due to the
virtual reference plane within the differential pair, that can be thought of as
a continuous return path [9].
A similar phenomena due to non-ideal return paths will occur in via structures,
in the following called via crosstalk, in order to distinguish it from conventional
crosstalk. According to [9], this crosstalk may result in a dramatic increase
in crosstalk in via structures. In principle, the via structures will act as a
antennas, radiating energy through the dielectric layers and planes that is
being picked up by other via structures.
2.4. Crosstalk
25
RS
+
+
VS (t)
RNE
VA (x,t)
VNE
-
-
IA(x,t)
Aggressor line
IV(x,t)
Victim line
+
+
VV (x,t)
VFE
-
-
RL
RFE
Figure 2.15: Three conductor crosstalk model.
The simplest crosstalk case is that for a three-conductor line, schematically
shown in figure 2.15, where two circuits are sharing a common return path.
A voltage is driven by a voltage source, Vs , with output impedance RS , on
the outer loop. The electromagnetic fields generated in the outer circuit will
interact with the inner circuit, inducing a current and a voltage in this circuit.
Since this was not intended, the inner loop is often referred to as victim line,
whereas the outer loop is called the aggressor line 17 . Due to coupling, voltages
will appear across the resistors RN E and RF E on the near-end and far-end
side respectively, with respect to the generator. In the near-end case the
inductive and capacitive currents will interact, whereas for the far-end case
they will counteract, and, thus, far-end crosstalk is always smaller than nearend crosstalk.
2.4.1
Crosstalk transmission line model
In section 2.3.3 the Telegrapher’s equations were derived for a single transmission line. In a similar fashion from the circuit shown in figure 2.16, the
corresponding equations can be derived for the three conductor crosstalk case
described in previous section, if we assume that both aggressor and victim
traces are parallel with the x-axis. Just like for the single transmission line,
lA and lV are the per-unit-length self-inductances for the aggressor and victim conductors respectively, representing the magnetic fluxes penetrating each
loop. Similarly, cA and cV are the per-unit-length self-conductances, representing the electric fields. The new elements, lM and cM , is the mutual inductance and capacitance, respectively. Again, by applying the same methods as
was done in section 2.3.3, the differential equations can be written in matrix
17
The aggressor line is sometimes also called generator conductor. The victim line is then
called receptor conductor.
26
Chapter 2. Theoretical background and signal integrity nomenclature
IA(x+ x,t)
IA(x,t)
+
lm x
VA (x,t)
cm x
IV(x,t)
+
lV x
+
cV x
VV (x,t)
-
+
lA x
cA x
VV (x+ x,t)
-
IA(x,t) + IV(x,t)
-
VA (x+ x,t)
-
Figure 2.16: Lossless per-unit-length equivalent circuit for a three conductor
transmission line with crosstalk.
form as:
∂
∂
V(x, t) = −L I(x, t)
∂x
∂t
(2.31a)
∂
∂
I(x, t) = −C V(x, t)
∂x
∂t
(2.31b)
where
(2.31c)
#
"
V (x, t)
V(x, t) = A
VV (x, t)
"
l
L= A
lM
lM
lV
#
"
#
I (x, t)
I(x, t) = A
IV (x, t)
"
(2.31d)
#
(cA + cM )
−cM
C=
−cM
(cV + cm )
(2.31e)
Intuitively, the inductive coupling will dominate the capacitive coupling for
low impedances with respect to the characteristic impedance, since a lower
impedance yields a larger current, while the opposite is true for larger impedances
[3].
The matrix representation given in equation (2.31) can without difficulties be
extended to hold for a system with an arbitrary number of conductors, often
referred to as a multiconductor transmission line-system. However, just like
for a single transmission line, the L- and C matrices calculations is normally
implemented by a field solver software application.
2.5. Mode conversions
2.5
27
Mode conversions
Evidently, a practical system contains a lot of imperfectness, as so far has been
described as discontinuities. For a differential pair, one important aspect is
the symmetry of the two conductors within the pair. For reasons already
mentioned, any two conductors in a practical PCB design will not be equal
and, thus, asymmetric. Any such asymmetry will result in mode-conversion
[9], converting part of the original signal to a different mode. For a few reasons
this might pose a problem.
Intuitively, one would only think of differential to common mode conversion as
a problem if it is large enough to saturate the drivers [12]. But the commonmode crosstalk can be much higher than for the differential case and consequently the common mode signal level must be kept small.
Another important aspect is that the time-delays for differential- and common
mode signals may be different, which may affect consequtive bits, in a fast
digital bitstream.
2.6
Network analysis
Any linear and time-invariant (LTI) system can be fully characterized by only
evaluating the signals on its ports [9], regardless of the internal structure of the
system. The system response to any input can then be calculated by simply
evaluating a linear equation system.
Many ways exist for obtaining this port information, normally described as
network parameters of the system. Commonly used parameters include impedance,
admittance and hybrid parameters, all of which contain the same information,
but differ in the way measured. For this reason a set of network parameters,
known as scattering parameters, or simply just s-parameters have become popular, especially for higher frequencies, since each port is evaluated when all
other ports are terminated with a matched impedance. The reason being the
fact that this situation is much easier to achieve in practice, than perfect openor short circuit that is required by the impedance- and admittance parameters
respectively.
2.6.1
Scattering matrix
In its simplest form, a two-port network, as depicted in figure 2.17, can be
described by a linear equation system on matrix form as:
" #
"
b1
s
s
= 11 12
b2
s21 s22
#"
a1
a2
#
(2.32)
28
Chapter 2. Theoretical background and signal integrity nomenclature
where
bi V − =
sij = i+ aj a =0
Vj V + =0
(2.33)
i
i
and where Vi+ or bi is the output signal from port i. Vj+ or aj is the input
signal at port j. More precisely, a and b are incident and reflected power
waves, respectively, which for a system with equal terminations on all ports
can be written as:
a=
1 V + Z0 I
p
2 |R{Z0 }|
(2.34)
b=
1 V − Z0∗ I
p
2 |R{Z0 }|
(2.35)
for the voltage V , current I and impedance Z, on each port.
a1
S
a2
b2
b1
Figure 2.17: Simple twoport network with incident and reflected waves
denoted a and b respectively.
When the s-parameters are collected from a system, they are evaluated at a discrete number of
frequencies for a selected frequency range. For
each frequency, every s-parameter, sij , will be
described by an unitless complex number, just
like the frequency response of a system is evaluated for a certain frequency. In the same way, the
evaluated s-parameter will contain information
about both magnitude and frequency. In order
to be useful, the s-parameters have to be specified together with the characteristic impedance
they were measured at18 .
For reciprocal systems, the s-parameter representation is
For instance will s21 equal s12 for a two-port system.
When measured in practice, however, this is a good thing, since this property
can be used to verify the measurement; in particular to verify proper probing
at both ports.
redundant19 .
The theory for a two-port system can simply be expanded to describe any
N -port network and the measured s-parameters can in general be written on
matrix form as:
b = Sa
18
19
(2.36)
This impedance is almost exclusively 50 ohm.
Mathematically, for a purely reciprocal system, the S-matrix will equal its transpose.
2.6. Network analysis
29
where S is a N xN -matrix, and a and b are N x1-matrices. For instance, a
single-ended system with four ports is given by:

 
s11
b1
b  s
 2   21
 =
b3  s31
s41
b4
2.6.2
s12
s22
s32
s42


s14 a1
 
s24 
 a2 
 
s34  a3 
s44 a4
s13
s23
s33
s43
(2.37)
Mixed-mode scattering parameters
For differential signaling, the system’s differential and common mode responses are of greater importance than the single-ended ones. If the fourport single-ended system described by equation (2.37) in the previous section,
instead would be evaluated for differential and common mode signals, the
mixed-mode S-parameter matrix for the corresponding differential two-port
would be obtained. This is shown in equation (2.38). When a distinction
must be made between these representations, equation (2.37) is often referred
to as the standard s-parameter matrix.



bd1
sdd11
b  s
 d2   dd21
 =
 bc1   scd11
bc2
scd21
sdd12
sdd22
scd12
scd22
sdc11
sdc21
scc11
scc21


sdc12 ad1
 
sdc22 
 ad2 
 
scc12   ac1 
scc22 ac2
(2.38)
where
sddij
bdi =
adj a
(2.39)
ci =acj =adi =0
sdcij
bdi =
acj a
(2.40)
ci =adi =adj =0
scdij
bci =
adj a
(2.41)
ci =acj =adi =0
bci sccij =
acj 2.6.2.1
(2.42)
aci =adi =adj =0
Standard to mixed mode scattering parameter conversion
In [15] a method for direct extraction of the mixed-mode s-parameters from
the standard s-parameters is proposed and demonstrated in a later work by
the same author in [16]20 .
20
Please note the difference in port number notation used in this paper compared to what
is used in this thesis.
30
Chapter 2. Theoretical background and signal integrity nomenclature
Here, in equations (2.43) through (2.48), a brief motivation21 of this method
for the four-port case is presented.
Intuitively, the relationship between incident single-ended and mixed mode
signals can be expressed as:



ad1
1
a 

1 0
 d2 
 = √ 
 ac1 
2 1
0
ac2


a1
0 −1 0


1 0 −1 a2 

 
0 1
0  a3 
a4
1 0
1
(2.43)
(2.44)

bd1


 
b1
1 0 −1 0


0 −1 b2 

 
1
0  b3 
b4
0 1 0
1
b 
1 
 d2 
0 1
 = √ 
 bc1 
2 1 0
bc2
(2.45)
or on a more compact matrix form:
Amm = MAstd
(2.46)
Bmm = MBstd
(2.47)
Since B = SA, it can easily be shown that:
Bmm = MSstd M−1 Amm
(2.48)
where the conversion matrix, M, has the property: M−1 = MT [15].
Obviously, this simple transformation shows that it is still the very same
information, only represented in a slightly different way.
One very important observation that can be made in the original derivation
of this method, is the inherited assumption about the relation between the
two conductors. This assumption is that Zodd = Zeven , which means that the
two transmission lines within the pair are uncoupled. For this reason, quite
unsurprisingly, the result from this conversion will not be the same as when
the system is driven by a true mixed-mode input signal22 , even though the
theoretical approximation achieves relatively good correlation for differential
signals. For the mode-conversion parameters23 , scd och sdc , on the other hand,
the differences will be large [17]. Uncertainties larger than the magnitude of
the parameters themselves, have been reported [16]. Consequently, for accurate determination of these parameters, the mixed-mode conversion matrix
cannot be used.
21
For a more rigid derivation of this method, the reader is referred to [15].
Such a result can be obtained when a pure-mode vector network analyzer, PMVNA, is
used [16]. This mode is also called true differential-mode by some instrument manufacturers.
23
Sometimes also referred to as cross-mode parameters.
22
2.6. Network analysis
31
However, computer simulation software seldomly support true mixed mode
s-parameters. The approach used in this thesis is therefore to use the mixedmode representation, but in order to create comparable results, both practical
measurements and performed simulations were made single-ended.
2.6.3
Transfer scattering matrix
The transfer scattering matrix 24 , or simply just the T-matrix, is another matrix representation of incident and reflected waves used for N-port networks,
very similar to the scattering matrix described in the previous section. The
T-matrix has the advantage of making it possible to cascade several networks
by simple matrix multiplication. In this thesis this method will be used for
de-embedding, as will be described in section 2.6.4.
The T-matrix can be expressed in several ways [18]. These cannot, however, be
used interchangeably; since the calculated parameters unsurprisingly will be
different. For instance, for a simple two-port network, the T-parameters can
be expressed as shown in both equation (2.49) and (2.50), where the former
is used in this thesis.
"
#
"
a1
T
T12
= 11
b1
T21 T22
"
#
"
b1
T
T12
= 11
a1
T21 T22
#"
b2
a2
#"
a2
b2
#
(2.49)
#
(2.50)
In order to convert from S-parameters to the T-parameters shown in equation
(2.49), it is simply a matter of solving for a1 and b1 in the linear equation
system described by the s-parameters, and then the T-parameters can be
identified. In this case:
(
b1
b2
24
= s11 a1 + s12 a2
= s21 a1 + s22 a2
Sometimes this matrix is also referred to as chain scattering matrix.
(2.51)
32
Chapter 2. Theoretical background and signal integrity nomenclature
Solving for a1 and b1 and identifying yields:

1

T11 = s21






T21 = ss11
21








T12 = − ss22
21
T22 = − s∆s
21
(2.52)
∆s = s11 s22 − s12 s21
The same approach can be used in order to convert back from T-parameters
to s-parameters, yielding the following parameters:

21

s11 = Ts11







s21 = T111








s12 =
∆T
T11
s22 = − TT12
11
(2.53)
∆T = T11 T22 − T12 T21
For the four-port networks used in this thesis, the following notation is used:



a1
T11
a  T
 3   21
 =
 b1  T31
b3
T41
T12
T22
T32
T42
T13
T23
T33
T43


T14 b2
 
T24 
  b4 
 
T34  a2 
T44 a4
(2.54)
The conversion parameters are computed in the same way as for the two-port
network, but not shown here for convenience.
2.6.4
De-embedding
Figure 2.18: Cascaded four-ports.
2.7. Time domain vs. frequency domain analysis
33
Suppose that there exist a network, consisting of three cascaded subnetworks,
as principally depicted in figure 2.18. Assume that it is only possible to
obtain the s-parameters for the whole system, but only the middle part is
to be characterized. Then, if s-parameters are available for the other two
sections, the wanted s-parameters can be extracted, by using a method called
de-embedding.
In this thesis, the first and last subnetwork in figure 2.18 represents the sparameters for the microwave probes, yet to be described, and the middle
section, the analyzed interconnect. As will be discussed further in section
3.6, this procedure is also a fundamental part of vector network analyzer
calibration.
As was briefly mentioned in section 2.6.3, the actual de-embedding is just a
matter of matrix manipulation. For the situation shown in figure 2.18, assume
that the s-parameters for the complete structure is available as Stot . Applying
the methods for conversion of s-parameters to T-parameters, the T-parameters
for the whole structure can be obtained as Ttot . Similarly, T1 and T3 can
also be obtained.
−1
Ttot = T1 T2 T3 ⇔ T2 = T−1
1 Ttot T3
(2.55)
Then, all that is left is to convert T2 to S2 and the s-parameters for the middle
section are available.
2.7
Time domain vs. frequency domain analysis
Thus far, various signal intergrity issues have been described both in time domain and in frequency domain and, in fact, both time- and frequency domain
analysis of an interconnect is relevant for a signal integrity analysis. How the
data is collected is, in theory, irrelevant since both are just different mappings describing the same system. In practice, it is a slightly different story,
however.
Parameters that can be extracted from each domain will be described in this
section, followed by how practical measurements can be performed.
2.7.1
TDR/TDT analysis – the time domain approach
Due to the inherited time domain characteristics of digital signaling, the most
intuitive approach for analyzing digital interconnects is simply in the time
domain. Such analysis can be performed by making use of a measurement
34
Chapter 2. Theoretical background and signal integrity nomenclature
method known as time domain reflectometry, TDR. In practice, an oscilloscope together with a step-generator25 is used, from which a step is applied
to the input of the system, and due to impedance mismatches, just as was described in section 2.3.6, reflections will occur. This way, all line discontinuities
are clearly visible as deviations from an ideal step, seen by the reflected voltage waveform observed at the driver. For differential analysis, a differential
step can be applied in the same way26 .
In both the differential- and single-ended cases a capacitive discontinuity, will
result in a “dip” in the reflected TDR signal, whereas a “peak” will occur in
the inductive case [19]. Typically, circuit connections, contacts, vias, non-ideal
return paths in the reference plane and other discontinuities are inductive,
whereas circuit input stages (CMOS) and trace bends, are capacitive [9]. In
order to estimate the impact of such a discontinuity for the real application,
the ideal step, can be changed to have a rise time similar to that of a system.
Often, instead of representing the mismatches by the reflected voltage, the
corresponding impedance is often used instead. This can simply be obtained
by utilizing the equations in section 2.3.6 [19], when the source impedance
is known. The variations for each discontinuity expressed in impedance will
be larger, but otherwise the two curves will have the very same appearance.
This observation is, by the way, also interesting, as it indicates that a signal
represented by a voltage, will not be very sensitive for impedance variations.
For this reason it is the opinion of the author, that the impedance response is
not of interest, in this thesis.
It should be noted that the TDR method is only an approximation, since
it expects all of the reflected signal to come back to the input, and that all
changes up to each impedance change are small [12, 9].
The rise time of the incident pulse is a critical measure for the accuracy of
the measurement as it will determine the smallest distinguishable distance
between two discontinuities. A TDR measurement can only resolve structures
that are electrically long compared to the rise-time, which can be approximated by the rule of thumb shown in equation (2.56) [19].
TDRresolution ≥
Trise
2
(2.56)
In addition to the rise time, other characteristics such as overshoot and settling
of the pulse is obviously important for the accuracy of the measurement [19].
25
Normally this step-generator comes as an extension to the oscilloscope used, and is the
called TDR-module.
26
Strictly, this method is called differential time domain reflectometry, DTDR. Unless a
distinction is necessary, in this thesis both will be referred to as TDR.
2.7. Time domain vs. frequency domain analysis
35
All information of the system cannot be extracted from the reflections however.
For this reason, the system output port is measured, when a TDR voltage step
is applied to the input port. In this case, the measurement of the output port
is referred to as time domain transmission, TDT .
2.7.1.1
Time-delay, propagation speed and a way to locate
line-discontinuities
As have been demonstrated so far, the most straight forward use of a TDRanalysis is to verify the actual impact of line discontinuities. With the use of
a few, very basic relationships, as soon will be shown, the exact location of
these discontinuities can be calculated.
The time-delay, TD , is one of the fundamental properties of a transmission
line and is simply the time it takes for a signal to propagate through an interconnect. Thus, it is obtained by measuring the time-difference between the
incident- and outgoing voltages27 . The only difficulty in this measurement is
to determine at what voltage level the measurements should be taken. Ideally,
though not practically possible, the measurement points would be where the
waveforms just begin to rise, in order to minimize the impact of rise time
degradation along the trace. Choosing another, arbitrary, voltage level may
therefore yield a large difference in the result. For all TDR-measurements
made in this thesis, 50 % of the steady state level is chosen as threshold voltage for both measurements. For differential measurements, differential- and
common mode delays are calculated in the same way, considering the signal
as single signal.
When the time-delay is known, the propagation speed, vp , for a trace of given
length, can simply be calculated, from which the precise locations of the discontinuities can be found.
2.7.1.2
Crosstalk in the time domain
By applying a TDR-signal to one port, and by measuring the output from an
adjacent conductor instead of the output port, the amount of crosstalk can be
characterized. In the time domain, crosstalk is generally defined as the ratio
between the measured voltage level on the victim line and on the aggressor
line, and is, thus, given as a percentage.
The amount of coupling will be proportional to the derivate of the rise time.
The area under the peak, however, will be constant regardless of the rise time.
27
Even though not used in this thesis, it can be noted that the time-delay can also be
obtained as half the time difference between the incident and reflected voltages, when the
output port is left open. Due to longer propagation distance resulting in more edge rate
degradation, this method is not recommended if TDR/TDT is available [19].
36
Chapter 2. Theoretical background and signal integrity nomenclature
In practice this means that if the section where crosstalk occur is short enough
compared to the rise time, the coupled voltage will not have time to build up
to reach its maximum value. For this reason, it is also relevant to perform a
crosstalk measurement, using a voltage step with a rise time similar to that of
the practical system, just as was recommended in the case of discontinuities.
2.7.1.3
Mode conversion
Evaluating mode conversion is of interest for number of reasons mentioned
in section 2.5. For a practical measurement in the time domain, it is just
a matter of inserting a differential or common mode signal, and sensing the
opposite. The measured mode conversion is then normally given as the ratio
between the outgoing and incident voltages.
2.7.2
S-parameter analysis – The frequency domain approach
As was previously mentioned in section 2.6, s-parameters can be obtained from
any LTI-system, normally evaluated over a range of discrete frequencies. For a
practical system, this measurement is performed by a vector network analyzer,
VNA. The VNA is the most accurate tool available to characterize high-speed
digital circuits [19], and compared to the TDR oscilloscope it provides superior
accuracy, dynamic range and frequency coverage28 [20].
Once the s-parameters are obtained, a lot of information about the system can
easily be extracted, and arbitrary signals can be applied to the interconnect
using computer simulation software. The parameters described in the following sections were considered relevant for the purposes of this thesis. In the
literature, just as for the TDR-case, many other methods for extracting other
parameters such as permittivity and per-unit-length parameters are available.
None of these methods are used in this thesis.
2.7.2.1
Transmission- and reflection behaviour
For several reasons explained in section 2.3.5, any signal propagating through
an interconnect will be subject to frequency dependent losses. Being dependent on frequency, these losses will, in addition to reducing the amplitude of
the signal, have the effect of a lowpass filter on the signal, thereby increasing
the edge rate. Ultimately, these characteristics will determine the highest bit
rate that the system can handle.
In order to investigate these effects of an interconnect, the transfer characteristics must be studied. As was explained previously in section 2.6.1, according
28
In other words faster rise times from a digital point of view.
2.7. Time domain vs. frequency domain analysis
37
to the the standard notation, sij contains the response measured at port i,
for a sinusoid applied at port j. Evidently, if port i and port j are physically connected, calculating the magnitude of this parameter will yield some
transfer characteristics. This parameter was used when analyzing the transfer
characteristics in this thesis, and when appropriate, the magnitude function
was calculated in dB as:
20 log10 (|sij (ω)|)
[dB]
(2.57)
where ports i and j are connected.
The magnitude function of sij , where port i and j typically are connected,
is often also referred to as the insertion loss 29 from port j to port i. In this
report, these two notations are used interchangeably.
Similarly to the interconnect transmission characteristics, the reflection characteristics can be calculated by taking the magnitude of the reflection sparameters, sii , for port i30 .
In most cases, for the differential circuits, the same characteristics were analyzed for the differential s-parameters sddij and Sddjj , respectively.
2.7.2.2
Phase response and propagation delay
In this thesis, the phase response, obtained through equation (2.58), was primary used for sanity checking the results obtained31 .
Φ(ω) = arg{sij (ω)}
[rad]
(2.58)
Neglecting the reflections at the input port, any of the s-parameters sij , or
sddij , where, again, port i and port j are physically connected, is comparable
to the frequency response of a system. Then, the propagation delay introduced
by the interconnect, will correspond to the calculated phase delay 32 .
Generally, the phase delay of a system with frequency response H(jω) is defined as shown in equation (2.59) [21], where Φ corresponds to the unwrapped
phase function, describing the phase response in radians, and given by equation (2.60) [21]. HR (ω) and HI (ω) here corresponds to the real and imaginary
parts of H(jω).
τf (ω) , −
29
Φ(ω)
ω
(2.59)
Note that, since this is a loss measure, the value in dB-scale should be positive. Normally the minus sign is left out, however, and so is done here as well.
30
These s-parameters, by the way, as per the s-parameter definition, correspond to the
reflection coefficient, previously described in section 2.3.6.
31
More precisely, in this thesis the unwrapped, or accumulated, phase response was used
for being easier to analyze.
32
This was verified through simulation in this thesis.
38
Chapter 2. Theoretical background and signal integrity nomenclature
where
HI (ω)
Φ(ω) , arg{H(jω)} = arctan
HR (ω)
(2.60)
It can be noted that this measurement has a clear advantage over the corresponding time domain measurement. Not only is the actual measurement
made with a VNA more accurate [19], but losses, which is the main contributor to the uncertainty in the time domain case, will have very little impact on
the phase response. In the TDR-case, and as was discussed in section 2.7.1.1,
a source of great uncertainty is the decision of at what voltage level the propagation start and ends. As was concluded, this is not very clear. In the case of
the phase delay, it can be calculated exactly over the wanted frequency range.
2.7.2.3
Crosstalk and mode conversions
The amount of crosstalk and mode conversions are easily obtained from sparameter data, as s-parameters contains the transfer characteristics between
any of the ports. Often the magnitude of these parameters are displayed
in dB-scale as 20 log10 |s|, where s in the case of mode conversion, would
correspond to any of the mode conversion parameters, sdc or scd . In the case
of crosstalk, it would correspond to any of the s-parameters describing the
transfer characteristics between any of the internally not connected ports.
For instance, sdd31 represents the near-end differential crosstalk.
3
Study of a product PCB – A first attempt of
signal integrity analysis
Now, with some of the basic theory for small scale signal integrity clarified, the
strategy for the actual analysis used in this thesis can be explained. Following
an overview of the conditions and resources available at the start of the project,
the original approach to the problem will be described in more detail. As
will be seen in this chapter, however, this approach turned out to be all but
optimal, ultimately demanding for a completely new approach to be taken.
3.1
Analyzing signal integrity of a PCB for an
existent product – the original plan
In order to evaluate the routing effects on signal integrity for the interconnects
in a typical contemporary digital design, it was decided to study one or more
PCBs used in current products. Since a PCB designed to be used in a real
application does not contain any ideal test cases, it was considered necessary
to analyze many nets in order to be able to make any conclusions about
measurement methods, computer simulation accuracy or even more general
signal integrity behaviour later on. By taking this approach, the importance
of efficient data management and data collection methods for cooping with
the large amount of test data to be produced, was early recognized. A lot
of effort in this thesis was therefore spent on this part, the first approach of
which will be presented in section 3.3.
The data to be analyzed was to be collected through measurements both
in time- and frequency domain, using a TDR-oscilloscope and a VNA respectively. Following this analysis, the measurements would additionally be
compared with the results from computer simulations. The data management
R application with a
and analysis was going to be based around a MATLAB
simple graphical user interface, GUI .
39
40
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
At this stage, during project planning, a few critical issues were identified, the
most obvious of which was to find an accurate probing technique. Perhaps
more important was, however, the question of whether it would be possible at
all to obtain any relevant results, measuring on a PCB with many unterminated traces close in proximity to the measured traces. These issues will be
discussed in more detail later in this chapter.
3.2
PCB selection and analysis – finding critical
nets
For the analysis, a typical twelve-layer PCB design was selected. At this stage,
the first obvious question was; what nets are relevant for analysis? Clearly,
not all nets are of interest. What particular properties that was looked for
can be summarized as:
• Close to ideal nets for measurement characterization
• Nets with several vias
• Nets with reference plane discontinuities
• Nets with possibility of crosstalk
Even though traces designed for high-speed digital signals, exclusively comes
as differential pairs, here, also single-ended traces were considered to be of
interest for comparison reasons.
Traces selected for measurement characterization, were typically straight traces
with no extra vias and small reference plane variations. These were primary
selected to be used as reference for comparison with less ideal traces.
For the crosstalk sections the most straight forward situation to both locate
and characterize, is that of two conductors, or pairs, in close proximity, as was
described previously in section 2.4. However in practice, for a well-designed
PCB, these would, or at least should, be hard to find.
3.3
Data management
As was previously mentioned, a lot of data was expected to be handled and,
R application was to be developed to facilitate the analysis.
thus, a MATLAB
The planned data management is conceptually illustrated in figure 3.1.
The basic idea was that information about the interesting nets to be studied
would be entered through this application, and stored in a simple database.
3.3. Data management
41
Figure 3.1: The original plan for data management and analysis.
This information would for instance include the name of the net, comments
about why it had been selected and trace lengths to allow for analysis of each
parameter per-unit-length. As soon as the measurements had been performed,
the next step would be to enter the file paths for the simulation- and measurement data. Through the GUI, the user would then be able to select arbitrary
nets for simple analysis and comparison.
The s-parameter data was expected to be stored in TouchStone version 1 file
format, and support for this was implemented according to the specification
(see [22]). TDR-data was expected to be stored in a simple CSV (comma
separated) ASCII-file.
For the s-parameter data, calculation of the following parameters was implemented as previously defined in section 2.7:
• Magnitude function
• Phase response
• Phase delay
The s-parameters would automatically be divided into a few appropriate groups,
distinguishing between transmission- and reflection s-parameters, and nearend- and far-end crosstalk s-parameters respectively.
In order to analyze differential behaviour, including mode-conversions, for
single-ended s-parameters, support for mixed-mode calculations, as described
in section 2.6.2, was also implemented.
For the TDR-data case, not as many ways of displaying the data was considered relevant. Basically, support for single-ended and differential signals, and
automatic calculation of propagation speed and distance between test points
and the largest discontinuites was implemented.
42
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
3.4
Computer simulation software – selection and
configuration
The initial goal for the computer simulations in this thesis, was to find the limitations of a relatively simple two-dimensional, or cross-sectional, field-solver,
rather than to achieve accurate results using a more sophisticated full-wave
three-dimensional field-solver. The former kind of application is commonly
used to quickly get a basic idea of suspected signal integrity issues during
R from Menpost-route analysis. Primary due to its ease of use, HyperLynx
R was considered an appropriate choice for this task. Moreover,
tor Graphics
R from the same
as the layout for this PCB was made using Board Station
company, providing for good integration, this choice seemed natural.
R simulation
Figure 3.2: Flow for exporting layout when using HyperLynx
software.
R exporting a layout is straight forward, as shown
When using HyperLynx,
R
in figure 3.2. As indicated in this figure, two separate programs, BoardSim
R
R
and LineSim, both part of the HyperLynx suite, were used. The net to
R into LineSim
R for simulation.
be analyzed was exported from BoardSim
When exporting s-parameters, this will simply be a matter of mapping port
numbers to pin numbers, in other words, a straight forward task1 . In order to
simulate a TDR-response, however, a custom model with 50 ohm termination,
producing a close to ideal step, had to be manually added to each port of the
interconnect. Moreover, in order to analyze the TDR-response from different
ports the added models had to be modified prior to simulating an inserted
signal at each port.
Setting up all different TDR/TDT simulations manually this way, is a daunting and error prone task. Further, being a very simple simulation tool, lacking
any ability for automation, it was decided early on that this process must be
simplified in some way. It was found that each file used for simulation is a plain
R
text file that could be edited externally. After studying how HyperLynx
stored the information in this file, most of this work of replacing models could
be automated using a few scripts.
1
R
In fact, s-parameters can even be exported directly from BoardSim.
3.5. Preparing for the measurements – finding a method for accurate and
efficient probing
43
3.5
Preparing for the measurements – finding a
method for accurate and efficient probing
Finding a reliable method that can be used for verification of fabricated PCBs
through measurements have been one of the main objectives of this thesis.
Reliable methods are also equally important in order to validate the accuracy
provided by computer simulation software.
In order to be able to measure all interesting interconnects, the PCBs primary
had to be analyzed without any components mounted2 .
Prior to making any measurements, a severe drawback for the measurement
accuracy was therefore anticipated. The reason for this being the risk of
resonances to occur in any of all the unterminated traces during analysis of
the densely spaced striplines. Such resonances could basically ruin the measurement. Clearly, this issue would have been avoided analyzing a testboard
specifically made for the purpose, but at the same time, such a solution would
consequently not allow for verification of a final product. To validate this
hypothesis, a few measurements were planned to be conducted on a fully
functional PCB, where all traces, except the measured ones, would be terminated. In spite of this risk, it was considered worth to investigate, and, thus,
finding a method of inserting and measuring signals onto the bare PCB had
to be found.
3.5.1
Connecting to the PCB using semi-rigid cables
How this connection between the test equipment and the device under test,
DUT , is made will, naturally, have a profound impact on the accuracy of
the obtained measurement data. Besides the more obvious requirement of
high measurement fidelity, for a method to be applicable in this case, it was
desired to allow for efficient data acquisition for the relatively large amount
of measurements to be conducted.
The first idea was to connect to the PCB, by soldering so called semi-rigid
cables, with SMA-connectors, to the pads for the nets to be studied, a method
which in terms of efficiency did not appear very attractive. Further more, at
least two major electrical drawbacks with this approach was identified. Firstly,
when attached to the board, the characteristics of these semi-rigid cables become unique. In other words, as they cannot be characterized, their contribution cannot be removed from the measurement data through de-embedding.
Secondly, for accurate measurement results in the gigahertz-range, the outer
ground shield of the semi-rigid cable have to be grounded very close to the
2
Sometimes the PCB is then referred to as bare [1].
44
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
selected test points on the PCB. Ideally, this distance would be in the order of
one millimeter or less away from the signal connection to suppress the ground
loop inductance, making the method practically impossible when manually
soldered.
In practice, a secondary drawback for this ground shield connection is that
it requires relatively large areas around the test points to be made ground,
preventing many closely spaced test points to be analyzed.
For all these reasons, this approach was quickly abandoned without any further
investigations and a new method therefore had to be found.
3.5.2
Using microwave probes – a superior method?
Figure 3.3: Microwave probe.
Many of the shortcomings of using semi-rigid cables, as was mentioned in the
previous section, would, at least theoretically, be either eliminated or dramatically suppressed using microwave probes 3 . According to [19], this kind of
probe, an example of which is shown in figure 3.3, is the most accurate available; exhibiting very small parasitics, very small ground loops and usually
being 50 ohm all the way to the probe tip. In [19], these probes are well recommended for TDR- as well as for VNA measurements, and is even preferred
over mounted SMA-connectors, that are said to have rather high capacitive
loading in comparison. Other important advantages include high measurement repeatability, and also the availability of accurate calibration methods,
when used together with a VNA. For these reasons, using microwave probes
was thought to be ideal for the measurements to conducted in this thesis.
No microwave probes were available for the project, however, and therefore
these probes had to be specifically ordered. When deciding which kind of probe
to use, besides the obvious characteristics such as bandwidth and connection
3
Thanks to Zoran Draganic for your advice on using microwave probes.
3.5. Preparing for the measurements – finding a method for accurate and
efficient probing
45
type, two characteristics were paid special attention; the probe configuration 4
and the probe pitch.
The probe configuration, describing the tip placement as seen from above with probe tip pointing
towards the beholder, are normally any of GSG, SG
or GS, where S corresponds to the signal tip and G
to the ground tip. For example, depicted in figure
3.4 is a probe tip in GSG configuration. Generally,
the GSG configuration is recommended due to better shielding [23]. As this configuration requires two
ground points to be available on exact locations with
respect to the signal test point, the simpler SG/GS
configuration was considered adequate for the pur- Figure 3.4: Microwave
poses of the measurements in this thesis. Yet, for probe tip in GSG coneach test point, a single good ground point must be figuration.
available at a distance corresponding to the probe
pitch.
After considering the layout, a pitch of two millimeter seemed suitable. Using this pitch many of the
currently available ground pads of the studied PCB
could be utilized, but still for some test points no
ground was available. For these cases, the best solution found was to drill a 0.6 mm hole through the
board and solder a metal wire to reach the ground
plane on the other side of the board. In order to
make good contact with the probe, these holes were
then filled with either solder or solder paste. However, this method was expected to introduce large Figure 3.5: Probe tip
parasitics. The difficulty of filling this hole creating for ECP18-GS-2000a smooth surface, perfectly leveled with signal pad DP.
was another limitation of this method.
The final probe ordered was the ECP18-GS/SG-2000-DP
Picoprobe from GGB Industries, Inc. This probe came with a 2000 µm pitch,
SMA-connector and probe-tip configuration as illustrated in figure 3.5. The
probe was specified to have a smoothly decaying magnitude function, for the
transmission s-parameters with a loss in the order of one dB at 18 GHz.
4
Sometimes called tip footprint or contact pattern.
46
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
3.6
VNA calibration
Compared to the oscilloscope, the VNA is able to achieve much better accuracy
[19, 20, 24]. Another important advantage being the availability of accurate
calibration methods, allowing for nothing but the DUT to be characterized.
As will be seen in this chapter, these calibrations can be performed in many
ways, and for reasons yet to come, several methods have been tested in this
thesis.
3.6.1
Calibration methods
Normally, prior to making any measurements the VNA test set-up, including
probes with accompanying cables, has to be calibrated. The calibration will
define a reference plane, which is the boundary between the test fixture and
the DUT, ideally placing it at the probe tips. By doing so, the systematic
errors, which are due to non-random imperfections of the measurement system,
will be removed. In general, this can be achieved by measuring a device
with accurately known characteristics, called calibration substrate 5 . For some
calibration methods, these characteristics are entered as calibration coefficients
describing equivalent circuit values as will be shown later.
The substrate normally contains several calibration standards, such as shortand open circuits, thru6 connections and loads. The most important error
terms, that generally must be accounted for by calibration include [19]:
• directivity – part of the incident signal is lost before reaching the DUT
• reflection tracking – variation of magnitude and phase versus frequency
in connections
• transmission tracking – corresponding to the above error term, but for
transmission
• source match – difference between VNA source impedance and ideal
impedance
How these error terms are accounted for is determined by the algorithm used
for the selected error model. This choice should be made based upon the
expected errors in the test setup, the accuracy requirement of the measurement
and by the calibration standards available, and is critical for the achievable
accuracy of the subsequent measurements [23], as only errors due to the error
5
Sometimes also impedance standard substrate, ISS.
For some reason, rather than using through, this informal spelling is more commonly
used.
6
3.6. VNA calibration
47
Figure 3.6: Flow graph for twelve-term two-port system error model displaying
error terms in forward direction.
terms accounted for will be handled properly. One of the most common system
error models used is the twelve-term model, the flow graph of which is depicted
for a two-port system in the forward direction in figure 3.6. In this flow graph
e00 relates to the directivity error, e10 e01 to the reflection tracking, e10 e32 to
the transmission tracking, e30 to leakage and, finally, e11 and e22 to the port
match at port one and port two respectively [25]. Correspondingly, the other
six terms can be identifed in the other direction.
The suggested calibration methods, or algorithms, for the substrate ordered
together with the probes, a CS-17 from the GGB Industries, Inc., were ShortOpen-Load-Thru, SOLT , and Line-Reflect-Match, LRM 7 , where SOLT is the
by far most commonly used method [23]. Just as the name implies, SOLT
requires short-, open- and load measurements for each port and a thru measurement for each two-port combination. Using SOLT, the errors of the test
system is reasonably well characterized using a short-circuit inductance, an
open-circuit capacitance, a load inductance and a through delay. At higher
frequencies, however, it is difficult to determine these values consistently [26].
Another drawback is the nearly ideal behaviour of the thru standard expected8 , a major limitation as it will introduce significant errors for orthogonally connected probes [23]. Further, according to [23], the SOLT method may
also have other numerical problems, that for a non-ideal system may result in
an over-determined equation system, leading to increased inaccuracy.
The LRM method is expected to be a better choice, and is recommended by
[23] for its superior performance over SOLT. This method requires a line, or
through, standard, identical reflect standards and identical match standards.
The main advantage of this method is that no calibration coefficients are
required. For the match standard, the only strict requirement is that its
behaviour is consistent throughout the calibration process.
7
This method is equivalent to the method also known as Thru-Reflect-Match.
A real through standard does not exist, since the probes cannot be directly connected,
but a short transmission line must be used.
8
48
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
Another advantage of LRM in comparison with SOLT, is the lower number of
measurements required, in general 0.5N (N − 1) + 3N , or 18 for a four-port,
as opposed to 0.5N (N − 1) + 2N , or 14 for LRM9 .
3.6.2
Test environment set-up and inital calibration
For the measurements, the ZVA-24 four-port VNA from Rohde & Schwarz,
with a frequency range from 10 MHz to 24 GHz was to be used. The probes
R with
were connected to this instrument using microwave cables from GORE,
a specified bandwidth of 40 GHz.
Figure 3.7: Two ECP18-GS/SG-2000-DP probes placed on a thru calibration
standard.
For the reasons motivated in the previous section, the initial plan was to
use the LRM calibration algorithm, available as a step-by-step process in the
instrument software. Unfortunately, after several calibration attempts, the
probes repeatedly appeared to be very sensitive above a few gigahertz. The
same was true for the SOLT calibration. After further investigation, the reason
for this behaviour became evident when measuring the thru-standard using
two probes as depicted in figure 3.7. This measurement was made with the
measurement reference plane placed at the probe SMA-connectors through
use of the automatic calibration unit, ZV Z52, from Rohde & Schwarz. The
magnitude function of the measured transmission s-parameters, for this set-up
is shown in figure 3.8.
Being very far from the specification provided by the manufacturer, this behaviour was therefore neither expected, nor acceptable. As long as the measurements would be repeatable, however, it would still be possible to characterize and later de-embed the influence of this behaviour from the measurements, at least in theory. In practice, however, for the frequency ranges with
low signal levels, large uncertainties in the result would be expected. From
this point of view, this approach seemed possible in this case, but clearly far
from optimal. Due to the poor results, low measurement repeatability, was
9
These figures assume that full four-port calibrations are performed, where leakage between all ports are taken into account. This is not the case for the LRM algorithm, described
in section 3.6.4.
3.6. VNA calibration
49
0
1
Magnitude [dB]
2
3
4
5
6
7
0
2
4
6
8
10
frequency [GHz]
12
14
16
Figure 3.8: Magnitude function for the transmission s-parameters (s21 , s12 )
when measuring a thru standard with two ECP18-GS/SG-2000-DP probes,
with the measurement reference plane at the probe SMA-connectors.
also suspected, but after many measurements, this was later considered to
only have a slight influence on the non-satisfying measurement results. Typical results from three different open-, short-, and load measurements on the
calibration substrate are shown in figures 3.9 through 3.11.
The poor performance of the probes is clearly visible in these figures, appearing
as low open- and short circuit reflection above ten gigahertz (as seen in figure
3.9 and 3.10), and as very poor match almost over the whole frequency range
(as seen in figure 3.11).
In order to, perhaps not overcome, but rather mitigate these effects, it was
decided to use a two-tier calibration process, where the reference plane first
would be placed at the SMA-connectors at the end of the cables, and later
moved to the probe tips, using de-embedding. This is conceptually depicted
in figure 3.12. Using this method, the first reference plane would simply
and accurately be established using the automatic calibration unit mentioned
previously. Thereafter, acquisition of s-parameter data for the studied nets,
including the impact of the probes, would follow. Finally, as the second tier,
the impact of the probes would be removed using de-embedding. This deembedding requires the s-parameters of the probes to be known, which can be
obtained using a suitable calibration algorithm.
The main advantage of this approach is the clear separation between the
uncertain probe calibration and the measurement. A likely scenario using a
50
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
0.0
0.5
Magnitude [dB]
1.0
1.5
2.0
2.5
3.0
3.5
2
4
6
8
10
frequency [GHz]
12
14
16
Figure 3.9: Reflection magnitude function from three typical open standard
measurements using the same ECP18-GS-2000-DP probe on a CS-17 substrate.
0
Magnitude [dB]
2
4
6
8
2
4
6
8
10
frequency [GHz]
12
14
16
Figure 3.10: Same conditions as for the case shown in figure 3.9, but this time
the result from three typical short standard measurements is displayed.
single-tier calibration would be that during one or more of the measurements
of the calibration standards, the probes behave differently to what it will
3.6. VNA calibration
51
0
Magnitude [dB]
10
20
30
40
50
60
2
4
6
8
10
frequency [GHz]
12
14
16
Figure 3.11: Corresponding load (or match) standard measurement for the
case shown in figure 3.9 and 3.10.
Figure 3.12: Concept of two-tier calibration approach.
during the following measurements. Such a situation might be hard to perceive
during the calibration process, but would result in errorenous compensation for
all the following measurements made with this calibration, basically making
them useless. On top of that, if something have suspectedly gone wrong,
there is no other way to find out afterwards, but to go back and redo both
the calibration and the measurement. One might think that this scenario
could have been avoided if the calibration had been validated by measuring
a few of the standards again, but this might be deceptive, as an errorenous
measurement of a certain standard might occur twice, or might appear much
less significant, when errorenously compensated for.
52
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
Using the two-tier approach, the behaviour of the probes is extracted and can
easily be studied afterwards, and simply be corrected without re-doing the
measurements all over. With confidence in this idea, a method for extracting
the s-parameters of the probes only using the calibration substrate had to
found.
To what extent the poor results obtained from the measurements on the calibration substrate in general would affect the likelyhood of success for any such
method was hard to anticipate, though the chances seemed decent below ten
gigahertz. Nevertheless, as this frequency limit was considered acceptable, an
attempt to characterize the probes was to be made.
3.6.3
The OSM calibration algorithm
As was briefly mentioned in section 3.6.1, VNA calibration is typically achieved
through extraction and subsequent de-embedding of the expected error terms
for the measurement system. This way, the error terms obtained for the “errorboxes” at each port will correspond to the s-parameters for each port. Using
an appropriate calibration method, this way the s-parameters for the probes
could be obtained.
Figure 3.13: Flow graph for three-term one-port system error model.
The simplest case would be to characterize each probe individually, using a
one-port calibration procedure. For this case, the common twelve-term error
model previously shown in figure 3.6 simply reduces to the three-term error
model shown in figure 3.13 [25].
Based on the available calibration standards, it was decided to use the simple
Open-Short-Match, OSM algorithm, requiring one-port s-parameters for the
open-, short- and match standards in order to extract the error terms, corresponding the s-parameters of the probes. Using OSM, these standards are
assumed to behave as the equivalent circuits shown in figure 3.14, with the
component values given by the calibration coefficients provided by the probe
3.6. VNA calibration
(a) Open.
53
(b) Short.
(c) Match.
Figure 3.14: Equivalent circuits for calibration standards.
manufacturer, knowing that:
s11 = Γ =
Z2 − Z1
Z2 + Z1
(3.1)
where Z1 = 50[ohm] and Z2 is equal to 1/(jωCstd )[ohm], jωLstd [ohm] and
Z1 + jωLstd [ohm] for the open-, short- and match circuit respectively.
From figure 3.13 it can easily be shown that the measured- and actual reflection
coefficients can be expressed as shown in equation (3.2) and (3.3) respectively,
where ∆e = e00 e11 − e10 e01 [25].
ΓM =
b0
e00 − ∆e Γ
=
a0
1 − e11 Γ
(3.2)
ΓM − e00
ΓM e11 − ∆e
(3.3)
Γ = s11 =
Re-writing yields:
e00 + ΓΓM e11 − Γ∆e = ΓM
(3.4)
Assuming the probes to be reciprocal, i.e. that s21 = s12 or expressed in error
terms e10 = e01 , and with three unknowns, this problem boils down to a simple
linear equation system, written with matrix notation as:




1 ΓstdOpen ΓmeasOpen −ΓstdOpen
e00
ΓmeasOpen


 
1 ΓstdShort ΓmeasShort −ΓstdShort  e11  ΓmeasShort 
1 ΓstdLoad ΓmeasLoad −ΓstdLoad
∆e
ΓmeasLoad
(3.5)
As can be seen, the reflection s-parameters, s11 and s22 corresponding to the
error terms e00 and e11 , are directly available from equation (3.5), whereas the
54
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
transmission s-parameters can finally be obtained from the (complex valued)
∆e -term:
∆e = e00 e11 − e10 e01 ⇔ e10 e01 = e00 e11 − ∆e = eT r
⇒ s11 = s22 = e10 = e01 =
q
(3.6)
|eT r |ej0.5 arg{eT r }
which is valid as a consequence of the assumption of reciprocality.
Code for extracting s-parameters for the probes, using this method was inR application described in section 3.3 and the
tegrated into the MATLAB
result was successfully evaluated using the Advanced Design System, ADS,
computer simulation software from Agilent Technologies. Unfortunately, the
result in practice was not satisfying, starting already at a few gigahertz.
Several attempts were made, where the s-parameters for the probes were extracted, followed by a new measurement on the calibration substrate, the
second time with the obtained s-parameters for the probes de-embedded from
the measurements using the de-embedding feature, available in the VNA instrument software.
0
Magnitude [dB]
10
Measured
Eq. circuit model
20
30
40
50
60
2
4
6
8
10
frequency [GHz]
12
14
16
Figure 3.15: Magnitude of reflection coefficients from equivalent circuit model
and from measured data.
The most likely reason for this to fail was thought to be the frequency response of the probes, especially for the open- and short standards (previously
shown in figure 3.9 and 3.10), being too sophisticated to be modeled by the
simple first order equivalent circuits, described by the calibration coefficients
provided by the manufacturer. This idea seemed reasonable for frequencies
3.6. VNA calibration
55
above ten gigahertz, but did not explain the unexpected behaviour for lower
frequencies. Another possible reason found was the poor match response, compared with the expected response described by the equivalent circuit model.
This comparison is plotted in figure 3.15. An attempt was made to improve
the outcome by adjusting the equivalent circuit model values to fit the measured data better, but still, the probes could not be reliably characterized.
Apparently, the probes simply was not good enough. Still it was decided to
try to find a better way to characterize the probes. Looking back, at this stage
it probably would have made the best sense to file a complaint to the probe
manufacturer, replacing the probes. This was, unfortunately, not made, but
instead, assuming that the problem was a result of the equivalent circuits used
by the algorithm being too simple, it was decided to try another algorithm,
not requiring any calibration coefficients.
3.6.4
LRM calibration algorithm
One algorithm that seemed suitable was the previouly mentioned LRM algorithm10 . As opposed to the OSM algorithm, LRM is not dependent on any
absolute values for the calibration substrate to be known. Instead, for high
accuracy only the difference between the different reflect- and match standard
measurements, should be minimized, or ideally zero [27].
Figure 3.16: Flow graph for the eight-term system error model used by the
two-port LRM calibration algorithm.
The flow graph for the eight-term system error model used by the LRM algorithm is depicted in figure 3.16. The three calibration standards, line, reflect
and match, are assumed to be given by the s-parameter matrices as described
by equations (3.7a) through (3.7c) [27].
"
0 1
SL =
1 0
#
(3.7a)
10
This is basically a variation of the traditional TRL algorithm, where the line standard
is replaced by two identical match standards [27].
56
Chapter 3. Study of a product PCB – A first attempt of signal integrity
analysis
"
Γ
0
SR = ref l
0
Γref l
"
SM =
0
e−γl
e−γl
0
#
(3.7b)
#
(3.7c)
where γ is the propagation constant as mentioned at the end of section 2.3.5.3.
From equation (3.7b) and (3.7c) the reason for the equivalent reflect requirement and the non-reflecting match requirement is evident. From equation
(3.7a) follows that the thru, is assumed to be ideal.
The actual derivation of this algorithm is rather involved, and will therefore
not be shown here. Instead, the reader is referred to [27]11 , in which the
LRM-algorithm used in this thesis is derived.
R application12 . Just
This algorithm was also implemented in the MATLAB
as was done with the OSM-algorithm, this algorithm was later verified successfully using the ADS simulation software.
Again, the result in practice turned out to be a different story. Possible
reasons for this might have been the reflective match problem, or the nonideal through behaviour. This time, things was not investigated further, but
the probes were returned to the manufacturer, with the claim of not complying
with the specification.
The probe manufacturer, GGB Industries, Inc, reluctantly agreed to replace
the probes and accompanying calibration substrate with a new set of 500 µm
pitch GSG probes, basically claiming that the specified accuracy should not
be expected in practice for as large pitches as 2000 µm.
Replacing the probes with a new probe configuration, with smaller pitch,
meant that all the preparations of the measurement points made on the PCB
to be studied, no longer could be used, ultimately leading to a complete turning point for the project. In order to be able to perform any measurements, a
specifically made test board had to be made, the process of which will follow
in the next chapter. With the test board a new methodology for the analysis
had to be developed, unfortunately implying that a lot of the data management work prepared had been done in vain. This was an unfortunate result of
the fact that quite a lot of project time already had elapsed before the original
probes were received, and that this preparation work had been done in the
meantime13 .
11
The original derivation of the TRL algorithm, as desribed in [28], is a good complement
to this document.
12
Thanks to Johan Sjöström for sharing your invaluable TRL implementation in
R
MATLAB.
13
This is also the reason for the long theoretical background chapter :-).
4
Designing a test board for the purpose
With the new 500 µm pitch microwave probes, no longer would it manually
be possible to prepare a pre-made PCB for measurements, not only because
of the small physical size, but also due to the smooth, leveled contact surfaces required. The only way to achieve this would be to design a test board,
specifically made for the purpose. Clearly, this opened the doors to a completely new world of opportunities, allowing for a more scientific analysis to
be made, where each test trace would include nothing but the bare minimum
for analyzing a particular phenomena.
4.1
Selection of relevant test cases
The first step towards the final test board, was to decide what test cases that
would be relevant for analysis. Obviously, this was of vital importance as it
ultimately would affect the usefulness of the whole project. But to hand-pick
a limited number of test cases without any prior accurate simulations nor
measurements to rely upon, this task was not as simple as it first may have
appeared. Starting out with a lot of ideas, it eventually boiled down to about
50 single-ended and differential test cases, which, when sparsely placed, was
expected to be enough to fill the available board size.
Similar to the division suggested in section 3.2, these test cases could be
divided into the following four groups:
• Test port characterization
• Crosstalk
• Via effects
• Miscellaneous
57
58
Chapter 4. Designing a test board for the purpose
These groups and the considerations made for the test cases will be described
in the following sections.
With a few exceptions, all test cases for the test board, came in both a singleended- and a differential version, primary in order to simplify the analysis,
but additionally to see whether or not the differential choice would provide
any additional advantages.
For a fair and simple comparison between the different test cases, it was decided to route all test cases in the same layer, wherever possible. Additionally,
for the same reason, it was decided to only use two different trace lengths for
all test cases, taking the vertical lenghts of the vias into account. Due to the
sizes of the board, these lengths were 54 mm and 108 mm respectively, where
the latter primary were used for the crosstalk structures, and the former for
the others.
4.1.1
Test port characterization and reference traces
Besides the actual test traces, characterization structures for determination
of dielectric properties and for characterization of the probe-to-test-pad transitions were considered.
Several methods exist for determination of dielectric properties in terms of
permittivity and loss tangent on a board-to-board basis, for instance by measuring the resonance frequencies of resonator circuits integrated into the board.
For the purpose of this thesis, to determine these parameters were not considered necessary. Moreover, for computer simulations, it was considered more
relevant to analyze the accuracy of using the nominal values for these properties provided by the board manufacturer, as that typically would be the case
in a post-route simulation, where no board is available.
Perhaps more critical to characterize, however, is the probe-to-test-pad transition in order to facilitate the analysis of the stripline interconnect, without
disturbances from vias nor test pads. Characterization of the test-pad-tostripline transition, is often done by designing a few different structures, which
in this case would consist of a measurement pad, connected through a via down
to the stripline layer under test, where the stripline either would be left open,
shorted or connected with an identical structure forming a through connection. Assuming the transitions to be identical across the board, the basic
idea is that the impact of these transitions simply can be de-embedded from
the measurement once they have been characterized and, in that way, allow
for analysis of the stripline alone. This kind of test structure is commonly
referred to as a de-embedding structure. It was decided not to include such
structures for this test board, but instead use structures with plain striplines
of same length as the ones used for the actual test cases. If the computer
4.1. Selection of relevant test cases
59
simulation results could be configured to match the actual measurements for
each and one of the test structures on the board, the constribution from the
actual stripline under test could then reliably be extracted from the rest of
structure in the computer simulation software. Being as simple as possible,
these test structures were therefore included to serve as a good starting point
for this approach. This group of traces could additionally be used for comparison with the different test cases, and are, therefore from now on, referred
to as reference traces.
4.1.2
Crosstalk test structures
As was explained in section 2.4, crosstalk between two signals may not only occur as a result of the electromagnetic coupling between two conductors placed
close in proximity, but could also be a result of crosstalk from non-ideal current return paths for two conductors routed far apart. Since these non-ideal
return paths were considered hard to anticipate without a reliable computer
simulation software configuration, it was decided not to design such test structures. Instead, various test cases for the more straight-forward situation with
conductors placed close to each other were included.
(a) Single layer.
(b) Adjacent layers.
(c) Adj. layers (broadside).
Figure 4.1: Single-ended crosstalk test cases.
Apparently, for this case, the amount of crosstalk expected is dependent on the
physical distance between the conductors. The two conductors can be placed
in three different ways, as depicted in figure 4.1, where the horizontal edge-toedge distance for the cases shown in figure 4.1a and 4.1b were chosen as 150
and 200 µm. In other words, five different test cases had to be implemented.
For a practical signal with non-zero rise-time, the amount of crosstalk will
also be dependent on the total trace-length for which the two conductors are
routed close to each other, as was mentioned in section 2.7.1.2. For this test
board, parallel lengths of 10, 30 and 50 mm were considered relevant1 . The
final layout for the single-ended crosstalk test structures are illustrated in
figure 4.2.
1
For the crosstalk voltage level to reach its maximum value, these lengths would require
signal rise-times in the order of 60-300 ps.
60
Chapter 4. Designing a test board for the purpose
150um/200um/broadside
10/30/50 mm
>2 mm
Figure 4.2: Layout of single-ended crosstalk test traces.
150um
/200um
/broadside
30/50 mm
Figure 4.3: Layout of differential crosstalk test traces.
The differential test structures were designed in a similar fashion, with the
difference that the ten millimeter test cases were left out due to lack of space
on the test board. The same horizontal distances measured between the innermost trace edges, were used here as for the single-ended case. The final
layout is shown in figure 4.3.
4.1. Selection of relevant test cases
4.1.3
61
Via effect
Vias are a fundamental part of any multilayer
PCB design and, consequently, for a reliable
high-speed interconnect design, their behaviour
must be accurately anticipated during the design phase. Mainly due to lack of space, only
two single-ended and two differential test cases
for verifying the impact on a signal changing between two inner-layers were included in the test
board. This was, however, not considered a limFigure 4.4: Single-ended
itation for the analysis as long as the simulation
via test case.
results would resemble the measured behaviour
for these structures. If that would be the case,
it was thought that other situations easily and reliably could be simulated
instead.
An example of this test structure is shown in figure 4.4, where the signal
changes from layer three to layer seven. In a similar fashion, a test case with
a signal changing between layer three and four was also included.
4.1.4
Miscellaneous test cases – practical routing situations
For most larger PCB designs, there are normally numerous situations that
could be considered uncertain from a signal integrity point of view. A few of
these situations were included in the test board, in order to verify their contribution to the overall deterioration of a signal passing through an interconnect.
Figure 4.5: Non-ideal current return path – opening in reference plane.
For instance, as was described in section 2.3.7, the current return path for
any signal is as important as the signal conductor itself. Ideally, the stripline
should be surrounded by two solid ground planes. Still, for various reasons,
62
Chapter 4. Designing a test board for the purpose
Figure 4.6: Non-ideal current return path – Trace passing through an area
with ground vias.
this may in practice not always be the case. A typical situation is when a signal is connected to a larger circuit, such as an ASIC or a FPGA, under which
a solid ground plane cannot exist. Other practical situations may include,
transitions between different stack-ups and for designs without dedicated reference planes. In order to verify the impact from these and similar situations,
two different test cases were selected, where the reference plane either would
be missing, as shown in figure 4.5, or be full of ground vias, as shown in figure
4.6.
Two other closely related cases, possibly required when connecting a differential pair to any larger circuit, such as a FPGA, are shown in figures 4.7a and
4.7b. Here, two test structures that resemble situations where the differential
pair either has to be splitted or squeezed together before connecting to the
circuit were selected.
Another common situation for a digital design is the need to avoid skew on a
bus, or between data and clock signals. This is often solved by introducing a
serpentine delay line on some of the traces in order to make all traces to have
equal length and, thus, equal delay. But how will this affect an individual
signal? In order to find out, a test case illustrated in figure 4.8 was included,
where a trace of length 108 mm where designed to only take up as much space
as a trace of length 54 mm to simplify comparison. It should be noted here
that the serpentine part here is rather long, compared to a practical situation.
4.2. Testboard layout
Increased
space
20 mm
(a) Differential pair splitted.
63
Decreased
space
20 mm
(b) Differential pair “squeezed”.
Figure 4.7: Situations for differential pair under a circuit.
Figure 4.8: Serpentine used for matching trace lengths.
4.2
Testboard layout
Once the different test cases to be included was established and schematics had
been drawn, it was time to plan the layout. In principle, this work was quite
straight forward, as the size of the available board allowed the test structures
to be sparsely placed.
The measurement pads had to be planned carefully, however. The reason for
this being the size and inflexibility of the microwave probe holders to be used,
64
Chapter 4. Designing a test board for the purpose
Figure 4.9: Conceptual layout for single-ended test structure showing suggested probe placement.
Figure 4.10: Conceptual layout for differential test structure showing suggested probe placement.
requiring each test point to be measured from a different direction relative to
the others. Overlooking this issue would most likely have resulted in a board
that could not be measured with the available equipment. The final layout
used for all test structures together with the expected probe placement, is
conceptually depicted in figure 4.9 and figure 4.10 for the single-ended- and
differential test structures respectively2 . Each test point, consisting of one
2
Please note that the actual length of the stripline under test is left out in these figures
4.3. Board characteristics
65
signal pad and two ground pads, was created by placing two 0201 resistors on
top of each other, sharing one pad.
After this, an initial placement of the test structures was made and all the difR
ferent test cases could be routed. This layout was created using the Cadence
Allegro layout tool.
4.3
Board characteristics
Although the simple test traces basically could have
been routed using only two stripline layers, it was
decided to use a full 14-layer stack-up, as shown
in figure 4.11, in order for the test cases, especially
the ones involving vias, to resemble a situation that
would be typical in a contemporary digital design.
As can be seen from this figure, solid ground planes
were placed at layer two, five, eight, eleven and bottom. For this testboard, with a few exceptions, all
test traces were routed in layer three and layer four,
using layer two and five as solid reference planes for
the signals.
The core and pre-preg dielectric layers were based
on Panasonic Matshushita HF, having a thickness of
150 µm.
The copper etch layers had a thickness of 17 µm for
the inner layers of the board. For the outer layers,
i.e. the top- and bottom layers, copper thickness of
40 µm were used.
L1
PP
L2
Core
PP
L3
L4
Core
PP
L5
L6
Core
L7
PP
L8
Core
PP
L9
L10
Core
L11
PP
L12
Core
L13
For the board, trace widths of 125 µm and 75 µm
PP
were decided to be used for the single-ended and difL14
ferential traces respectively. The differential pairs
were designed with a gap, or distance between two Figure 4.11: 14 layer
stack-up used for the
innermost edges, of 100 µm.
test board.
All vias for the board were through-hole, with a
(drill) hole diameter of 0.25 mm, via pad diameter
of 0.65 mm and via clearance of 0.18 mm.
The board, manufactured by Aspocomp OY, had
nominal relative permittivity of 4.7 and nominal loss tangent of 0.014 as indicated in figures 4.12 and 4.13, where these dielectric properties are plotted
based on data provided by the manufacturer.
for convenience.
66
Chapter 4. Designing a test board for the purpose
Relative permittivity vs frequency
Upper uncertainty limit
Relative permittivity at 23° C
Lower uncertainty limit
Nominal value
Relative permittivity, ²r
5.2
5.0
4.8
4.6
4.4
0
2
4
6
frequency [GHz]
8
10
Figure 4.12: Relative permittivity up to ten gigahertz as provided by the
manufacturer.
Dielectric loss tangent vs frequency
0.05
Upper uncertainty limit
Loss tangent at 23° C
Lower uncertainty limit
Nominal value
Loss tangent, tanδ
0.04
0.03
0.02
0.01
0
2
4
6
frequency [GHz]
8
10
Figure 4.13: Loss tangent up to ten gigahertz as provided by the manufacturer.
4.4. A new analysis methodology
4.4
67
A new analysis methodology
With the new test board a new a method for the analysis, emphasizing quality
rather than quantity, was needed. The previous idea of only analyzing the
measurement data, with nothing but the results from a simple simulator for
comparison, no longer felt attractive, especially as the influence of each test
port, consisting of test pads and a via down to the stripline under test, could
be expected to have a major impact on the measurement result. A more
sophisticated approach was therefore desired. In other words, a way to extract
the behaviour of the actual stripline under test was needed.
As was mentioned in section 4.1.1, assuming that it would be possible to match
the results from computer simulations with the measured data, the impact of
each test port could be removed by simply excluding it from the simulation
model. For this to work, an accurate full-blown EM simulator was required.
If this could be accomplished, experimenting with different structures would
easily and reliably be done in the simulator. With full control over each part
of a structure, evaluation of the performance of a more simple simulator could
later be done. Finally, with an accurate s-parameter model for the circuit
at hand, analysis of measured and simulated TDR/TDT responses of the
structures could be made with the purpose of revealing the actual impact of
the test cases in time domain.
4.5
A new application to aid the new analysis
The way the new analysis method evolved did not suite the workflow for
R GUI application, as was described in
the previously developed MATLAB
section 3.3. Instead of re-writing this application, a new, more flexible GUI
was developed in C++, utilizing the Qt libraries for the GUI and an embedded
python interpreterer making use of the Matplotlib module for the plotting3 .
The application, being based around the TouchStone file format for the sparameter management, included the following main features:
• Plotting of s-parameters
• Probe characterization using LRM
• two- and four-port de-embedding of probe characteristics
For the plotting, only the magnitude function in linear- and log-scale was
implemented together with the unwrapped phase response and phase delay,
all implemented according to the definitions described in section 2.7.2.1.
3
All s-parameter plots in this report are automatically generated using this application.
68
Chapter 4. Designing a test board for the purpose
The LRM implementation used the very same algorithm as was described in
section 3.6.4, that is, an algorithm based on the assumption that the eightterm error model could be utilized for characterization of two probes at a time.
For the reasons motivated in in section 3.6.2, a two-tier calibration process
would be used, and the application was developed with the the following
intended workflow in mind:
1. Calibration of the VNA and cables using the automatic calibration unit.
2. Acquisition of data from measurements on the calibration substrate.
3. Acquisition of data from measurements on the test structures.
4. Extraction of probe s-parameters from the calibration substrate measurments.
5. De-embedding of probe s-parameters from test structure measurement
data.
This time, however, to avoid the risk of any unnecessary work, the actual
measurements were carried out before these ideas were implemented.
4.6
Probe characterization and the inital
measurements
After a few measurements with the new 40A-GSG-500-DP probes from GGB
Industries, Inc., the huge performance improvement compared with the previous probes soon became evident. Using the LRM calibration algorithm, the
well-haved probe characteristics could be extracted as shown in figures 4.14
and 4.15. For the calibrations, the short- rather than the open calibration
standard was utilized for the reflection measurement, as recommended by the
probe manufacturer.
For all the subsequent measurements the VNA was configured for a frequency
range from 50 MHz to 20 GHz with a stimulus input power of 0 dBm. For a
reasonable measurement time and good enough dynamic range, the measurement bandwidth was set to one kilohertz together with an average factor of
ten.
As was explained in section 3.6.4, among a few other things, the accuracy
of the LRM algorithm is dependent on two good match measurements. The
return loss for these measurements was found to be less than -20 dB over the
whole frequency range studied and the differences between the probes were
comparatively small.
4.6. Probe characterization and the inital measurements
0
s11 (K-connector side)
s22 (Probe-tip side)
10
Magnitude [dB]
69
20
30
40
50
600
5
10
frequency [GHz]
15
20
Figure 4.14: Typical return loss for a 40A-GSG-500-DP probe extracted using
the LRM algorithm.
0.0
Magnitude [dB]
0.1
0.2
0.3
0.4
0
5
10
frequency [GHz]
15
20
Figure 4.15: Typical behaviour of the magnitude of the insertion loss sparameters, s21 and s12 , for a 40A-GSG-500-DP probe, extracted using LRM.
70
Chapter 4. Designing a test board for the purpose
Moreover, being based on an eight-term error model, no leakage between
the probes would be taken into account. Consequently, leakage between the
probes on a differential measurement would reduce the accuracy. Based on
the planned probe placement, as was shown in figures 4.9 and 4.10 previously,
this would be most likely to occur for the differential ports. However, for two
probes on the distance used for this test board, no leakage was observable.
Another important advantage found was the very good measurement repeatability for the probes. A low repeatability would apparently have made the
characterization information useless. Fortunately this was not the case.
As no other issues was found, the first measurement on the test board could,
finally, be performed.
4.7
Selecting and configuring an EM simulator
As per the plan, once measurement data was available, the next step would
be to set-up an EM simulator.
Several choices exist when it comes to sophisticated EM simulators, including
R 4 and EMPro and Momentum from Agilent TechnoloHFSSTM from Ansys
gies. As Agilent Technologies was the only of the two companies to provide a
R Allegro layout tool, the HFSSTM
way to transfer a PCB layout from Cadence
was never considered. Although EMPro was quickly tested, it was decided to
use Momentum5 , which is recommended for planar structures for being more
efficient6 [29].
Figure 4.16: Conceptual equivalent circuit model used by the Momentum simulator for a sheet metallization layer, with a mesh consisting of three-by-three
cells.
4
R
Previously Ansoft.
All Momentum simulations in this thesis were performed using Momentum
MomEngine_64 8.60.412(*)351.500 Oct 13 2009, which is part of ADS 2009u1.
6
This is due to the fact that only the surfaces of the metals need to be taken into account
in the solution process when simulating a 3d structure, unlike for the methods employed by
EMPro, taking the whole structure into account [29].
5
4.7. Selecting and configuring an EM simulator
71
In the solution process Momentum uses a numerical discretization technique
known as the method of moments. Explaining the details of this method is
beyond the scope of this thesis and here it suffices to know that the solution,
derived from Maxwell’s equations, ultimately is found by solving for the electric and magnetic surface currents from an equivalent circuit coupling model
of the structure using Kirchoff’s voltage law. An example of such equivalent
circuit model for a piece of a metallization layer is shown in figure 4.16, where
all capacitors and inductors in the net are complex, frequency dependent and
mutually coupled7 . Shown in this figure, the piece of metal is divided by a
grid, known as the mesh.
Figure 4.17: Magnitude of s11 and s21 for a stripline obtained from one single
simulation and from two separate simulations, cascaded in a separate step.
From this very simplified view, it is easily understood that the size of the
problem and, ultimately the simulation time, will be strongly dependent on
the number of mesh cells, which in turn is dependent on the mesh density
and total size of metallization area used for the structure to be simulated.
In other words, the bigger the structure, the longer the simulation time. For
this reason, a complete test structure could not efficiently be simulated at
once, as the number of mesh cells simply would become too large. Instead the
circuit to be studied had to be divided into subcircuits, where each subcircuit
simulation would produce a s-parameter model. These s-parameter blocks
7
See the Theory of Operation for Momentum chapter in the ADS Momentum manual
for a more in-depth explanation of this concept.
72
Chapter 4. Designing a test board for the purpose
would then simply be concatenated for instance using ADS simulator from
Agilent Technologies. To verify the plausibility of this concept, a very simple
test was carried out, where a stripline was simulated both as one single piece,
and as two separate parts, the s-parameter representation of which afterwards
were cascaded. Shown in figure 4.17, this turned out to work perfectly fine8 .
This was also verified for the differential case, where nearly as good results
could be obtained, with deviations typically smaller than 0.1 dB.
For the analysis yet to come, another important thing to clarify was whether
mixed-mode s-parameters could be reliably studied for all differential signals or not. As indicated in [16, 17] and already mentioned in section 2.6.2,
for strongly coupled differential pairs, the mixed-mode parameters, based on
single-ended s-parameter measurement, could be clearly different from the sparameters obtained from a true differential measurement, especially for the
mode-conversion parameters. This was therefore verified through simulation
for the differential pairs used here and it was concluded that the observable
differences for the differential-to-differential parameters, mostly studied in this
thesis, would be neglectable.
4.7.1
Momentum configuration for good agreement with
measurements
Without any prior experience, setting up Momentum simulator to correlate
with the measurement turned out to be quite challenging and a lot of time had
to be spent on this part, before a satisfying result eventually was achieved.
The most frustrating part of learning Momentum is the long simulation times,
which for a simple ciruit may take many hours up to days on a powerful
workstation computer, making it very time consuming to verify the impact of
various configurations and parameters.
For a long time in this process, the main issue was a phenomena that manifested itself as “spikes” in a very narrow band of the magnitude function of the
s-parameters. A typical result of this is plotted in figure 4.18. By changing the
geometry of the ground planes in the circuit, the problem ended up at other
frequencies. It was found that the easiest way to distinguish between this
phenomena and other variations in the magnitude function, was to study the
phase response, which indicated a swift positive phase shift for the erroneous
frequency points. Without any deeper knowledge of microwave theory, this
was thought to be caused by some higher order microwave modes as a result
of the limited, or finite, ground planes that were used. A variety of different
geometries, stack-up- and mesh settings and port configurations were tested
8
Note that this correlation can only be obtained using calibrated ports, such as singlemode ports, i.e. this would not work as good for internal ports.
4.7. Selecting and configuring an EM simulator
73
Figure 4.18: Forward transmission magnitude and phase response simulation
results for a via model, showing typical erroneous result obtained at certain
frequencies when using finite ground planes.
before it was found that it is possible to use infinite ground planes as an inner
layer in the stack-up configuration9 . With this configuration, these issues finally could be solved. The result of this simulation is also shown in figure 4.18.
Interesting to note in this figure is how well the two methods correlate for all
other frequencies. This method also came with another important advantage;
as opposed to finite ground planes, infinite ground planes in Momentum will
not be meshed, resulting in significantly reduced simulation times.
As soon as this major issue was solved, the work of analyzing the influence
of various configurations was started all over, with the goal of achieving as
good correlation with the measurement as possible. This work focused on the
reference traces, i.e. the test traces that only consisted of a stripline with a
test port with measurement pads and a via at each end. Although different
values for the dielectric properties were tested, for the final configuration, it
was decided to use the nominal values provided by the manufacturer, as that
would typically be the only values available for a post-route simulation in a
normal design flow.
Other important decisions made regarding the simulation configuration included the use of thick conductors, instead of sheet conductors and 3d distributed
via models instead of 2d distributed or lumped models. The simulations were
9
This is known as the substrate definition in Momentum.
74
Chapter 4. Designing a test board for the purpose
0
Simulated
Measured
Magnitude [dB]
10
20
30
40
0
5
10
frequency [GHz]
15
20
Figure 4.19: Magnitude function of s21 , s12 for a 54 mm reference trace with
a stripline at layer three.
0
Simulated
Measured
Magnitude [dB]
10
20
30
40
0
5
10
frequency [GHz]
15
20
Figure 4.20: Magnitude function of s11 for the same reference trace as used
for the plot in figure 4.19.
4.7. Selecting and configuring an EM simulator
75
performed using an adaptive frequency sweep in order to minimize the number
of required frequency points for each simulation.
An example of the results for one of the test structures with a stripline at
layer three is shown in figures 4.19 and 4.20. From figure 4.19, showing the
magnitude function of the measured and simulated transfer s-parameters, s21 ,
the huge impact from the via stubs at the test ports is clearly visible. Please
note that the magnitude function here is plotted in logarithmic scale, clearly
exaggerating the differences for the very small voltage levels below -30 dB.
Still, this difference needs to be clarified.
0
Magnitude [dB]
10
20
30
40
0
Complete structure
Via at left port
Via at right port
Stripline
5
10
frequency [GHz]
15
20
Figure 4.21: |s21 | for the total simulated structure and for individual simulated
sub blocks for a stripline at layer three (stublength of 1.86 mm) plotted in
logarithmic scale.
Plotted in figure 4.21 is the simulated s21 magnitude function together with
the simulated s21 magnitude functions of the three sub-blocks that it is made
up of. Here, the two geometrically perfect via ports show very similar characteristics, resulting in two via stub resonances ending up very close in frequency,
ultimately boosting the resonance effect around this narrow frequency range.
If the stub resonance frequency for one of the ports would have been located at
another frequency, a response much closer to what had been measured could
be obtained. This was tested through simulation and an example is shown
in figure 4.22. This phenomena could be seen for traces over the whole test
board, and for the very same trace, when measured on any of the other four
test boards available, but a good explanation for this perceived correlation
76
Chapter 4. Designing a test board for the purpose
0
Magnitude [dB]
5
10
15
20
25
0
Complete structure
Via at left port
Via at right port
Stripline
5
10
frequency [GHz]
15
20
Figure 4.22: |s21 | for total simulated structure and for individual simulated
sub blocks for the case when the two via stub resonances appear at different
frequencies.
between via location and characteristics, was never found. To assume that
this was due to the variations of the manufacturing process did not seem very
likely, as quite extensively changes of the geometry would be required in order to move the resonance frequency a few gigahertz, which was confirmed
through simulations.
In a similar manner, the other single-ended reference trace, routed at layer
seven, was evaluated, followed by the corresponding differential cases, all with
results showing good agreement with the measured responses, with the exception of a slight difference in the via resonance frequencies. The magnitude
function of the single-ended case is plotted in figure 4.23. From this figure it
can also be seen how the reduced stub length clearly moves the resonance up
in frequency. This behaviour will be analyzed further in section 5.1.
4.8
A few words on TDR/TDT set-up
Now, finally, the actual analysis could begin. As was motivated in section
2.3.1, for accurate time domain modelling of a digital interconnect, it should
4.8. A few words on TDR/TDT set-up
77
0
5
Magnitude [dB]
10
15
20
25
30
35
40
0
Complete simulated
Via at left port
Via at right port
Stripline
Complete measured
5
10
frequency [GHz]
15
20
Figure 4.23: |s21 | for total simulated structure and for individual simulated
sub blocks for a stripline at layer seven (stublength of 1.192 mm).
be characterized up to approximately the inverse of the signal rise time10 . In
this thesis frequencies up to 20 GHz, corresponding to a rise time of 50 ps,
are studied. Indeed, this is a very fast signal, and one always have to question
the validity of measurements at such high frequencies. In a practical digital
application, the speed of the signals for the vast majority of traces, are no
way near the ones mentioned here. This is especially true for single-ended
interconnects, which are never used for high-speed digital signaling. Still, it
is interesting to study how accurate it is possible to simulate interconnects at
such high frequencies, even for the single-ended case, as it obviously resembles
the differential case in many ways. Please bear this in mind for the next
chapter, when perhaps the properties of a single-ended interconnect at ten
gigahertz is analyzed. But first a few words on time-domain measurements.
As have been found already, a via stub may appear to have a severe impact
on the magnitude response of the transmission parameters for a stripline interconnect. But what shape would such phenomena take in the time-domain?
Clearly, the impact will be very much signal dependent. Analyzing various
data patterns and speeds in a more statistical manner is beyond the scope of
this thesis and so is the impact of improper terminations at the circuit connections. However, once an accurate, reliable frequency model of the interconnect
10
In fact, this is also the requirement put on the s-parameters by the ADS circuit simulator, for use in a time domain simulation (unless extrapolation is used).
78
Chapter 4. Designing a test board for the purpose
is available, such effects are quickly and simply simulated for an any situation.
As an example of how various phenomenas may appear in the time domain, a
TDR/TDT approach will here be utilized. Consequently, being a well matched
50 ohm measurement, the results are very likely to appear much better than
they would in practice but, at the same time, this allows studying of nothing
but the interconnect effect.
Figure 4.24: Circuit model used for two-port TDR/TDT simulations.
For the analysis, the measured TDR/TDT data was compared to a simulated
TDR/TDT response, obtained by applying a perfect step to the s-parameter
model obtained from the Momentum simulations, a circuit model of which
is shown in figure 4.24 for the two-port case. These simulations were performed in ADS. For the rise times to be used for the simulations and practical
measurements, 50 and 100 ps were considered reasonable.
All practical TDR/TDT measurements were performed using the 86100D oscilloscope from Agilent Technologies, together with the 54754A TDR/TDT
module. The calibration were performed, using the built-in procedure, requiring a thru-, short- and load measurement. These were performed on the CS-9
calibration substrate, previously used for the VNA calibration. All measurements were performed using a time resolution of approximately 0.4 ps and
0.8 ps11 based on 64 averages for the 54 and 108 mm test structures respectively.
4.8.1
A first comparison between simulated and measured
responses
An example comparing the simulated and measured response of the forward
TDR and TDT responses for the single-ended reference trace with a stripline
at layer three are plotted here in figure 4.25.
As can be seen, the simulated TDR response, or reflection, correlates very well
with the measured response. However, a relatively large difference can be seen
for the TDT response, or transmission, appearing as a lower voltage level in
11
8 · (100 ps/div or 200 ps/div) /2048 pnts.
4.8. A few words on TDR/TDT set-up
79
Voltage [V]
0.20
0.15
0.10
0.05
0.00
0.05
T21 - Measured
T21 - Simulated
T11 - Measured
T11 - Simulated
0.2
0.4
0.6
time [ns]
0.8
Figure 4.25: TDR/TDT response for the single-ended reference trace with
50 ps rise time, where the simulated result is terminated with an ideal 50 ohm
resistance.
figure 4.25. This could be observed for all the studied traces, in other words
this phenomena was independent of the test structures and, consequently, this
difference was likely caused by incorrect calibration, simulation configuration
or measurement set-up.
To simplify the analysis, this issue was divided into to sub-problems; a transient part with a considerably lower voltage level as clearly seen in figure 4.25,
and a slightly smaller steady-state offset error, reached after a few nanoseconds
and therefore not seen in the same figure.
Initially, the lower DC level, was assumed to be due to an incorrect extrapolation of the simulated s-parameters, from the lowest simulated frequency
of 50 MHz down to DC. This was, however, ruled out through some simple
simulations, not described any further here. Neither could this be the result of
incorrect modelling of the trace resistance, as such a large voltage drop would
require a trace resistance in the order of ten ohm12 . Evidently, such high
resistance could in general be caused by the skin effect combined with surface
roughness, but was ruled out here, primary as this problem appeared inde12
The measured trace resistance is in the order of one ohm. The DC resistance extracted
from the simulated s-parameter model was found equal to 0.45 ohm, which in fact is the
same as the calculated resistance for an ideal trace with the same resistivity as for pure
copper.
80
Chapter 4. Designing a test board for the purpose
pendent of the trace length and secondary because the significant frequency
components of the signal was too low in frequency to achieve high enough
resistance.
Voltage [V]
0.20
0.15
0.10
0.05
0.00
0.050.2
T21 - TDR/TDT oscilloscope
T21 - VNA, probes incl
T21 - VNA meas, probes excl
T21 - Momentum
0.3
0.4
0.5 0.6
time [ns]
0.7
0.8
0.9
Figure 4.26: TDT response for the single-ended reference trace with 50 ps
rise time, comparing the measured result with simulated results based on
simulated and measured s-parameters.
One interesting observation could be made when the TDR/TDT response
for the measured s-parameters obtained from the VNA measurements were
put into the simulator in the same way as was done for the simulated ones.
The result of this test, as plotted in figure 4.26, indicated that taking the
probe characteristics into account the received signal would more closely resemble the measured TDT response. In fact, this was the only way found
that closely resembled the transient part of the measured TDT response and
exactly matched the DC offset (not seen in figure 4.26).
As it appears to the author, the reason for this might be the less accurate calibration, or rather normalization, method used for the TDR/TDT measurement, only including a thru measurement for the TDT port. Unfortunately,
as this procedure additionally used the oscilloscope software, with no exact
details available, this hypothesis cound not be confirmed.
Assuming this to be valid, the simulated TDR/TDT response was considered accurate enough to be used to indicate the time domain response to the
different test cases, yet to be studied.
5
Analysis of the routing effects
With a relatively good understanding of the s-parameter and TDR/TDT measurements and simulations and their accuracy, the analysis of the various test
cases could finally begin.
As was found in the previous chapter, the impact of the test ports, connecting
the test pads to the stripline under test, could be rather significant, making
it difficult to analyze the behaviour of the various stripline interconnects. To
address this issue, the idea was to base the analysis on the obtained simulated
results for these sections, as was motivated in section 4.1.1. For this analysis
to be relevant, all complete test structures should be simulated and compared to the measured s-parameters and measured TDR/TDT response. If
not stated otherwise, this was done for all traces to be studied in this chapter,
although the results are not always presented. In general, all reflection- and
transmission s-parameters showed very good agreement between measuredand simulated results up to as high as twelve gigahertz. In most of the test
cases, however, even that frequency is too high to be relevant when evaluating the signal integrity behaviour. Still it is relevant for accurate simulation
of fast edges and is consequently important when comparing measured and
simulated responses.
Note that most s-parameter magnitude plots that appear in this chapter are
plotted in linear scale, as such representation was considered more natural
from a digital point of view. Further more, for these plots, it was decided to
use a fixed y-axis scale, for easier comparison between the various cases1 .
5.1
Impact from vias
As could already be seen when the behaviour of the test ports were analyzed
in section 4.7.1, the long via stubs of the through hole vias used for the test
1
This is not the case for the TDR/TDT plots yet to come.
81
82
Chapter 5. Analysis of the routing effects
1.0
Via - L3->L4
Via - L3->L7
Stripline only
Magnitude
0.8
0.6
0.4
0.2
0.00
2
4
6
8
frequency [GHz]
10
12
Figure 5.1: |s21 | for the simulated single-ended via test cases.
Voltage [V]
0.20
0.15
0.10
0.05
0.00
0.05
T21 - Via L3->L4
T21 - Stripline only
T11 - Via L3->L4
T11 - Stripline only
0.2
0.4
0.6
time [ns]
0.8
1.0
Figure 5.2: Single-ended TDR/TDT response to an applied step with 100 ps
rise time.
board will have a significant influence on the signal integrity. On the test
board, two single-ended and two differential test cases were included for ex-
5.1. Impact from vias
83
plicit verification of this via behaviour, where the trace would change from
layer three to layer four and from layer three to layer seven, leaving stub
lengths of 1.693 mm and 1.192 mm respectively. The result of these stubs are
visible in figure 5.1, showing slightly better transmission for the via with a
shorter stub. Still, above a few gigahertz, none of the cases appears to perform
very well. However, in the time domain, for a practical digital signal, this will
not have as big influence on the transmission as the s-parameter magnitude
function may suggest. The time domain response for the worst case, i.e. for
the test case with the longest via stub, can be seen in figure 5.2, where only
the sharpness of the transmitted edge is slightly affected. This was found to
be the case even for a very fast pulse train, suggesting that transmission magnitude response may be falsely interpreted to yield a more pessimistic view
compared to what is actually the case.
1.0
Via - L3->L4
Via - L3->L7
Stripline only
Magnitude
0.8
0.6
0.4
0.2
0.00
2
4
6
8
frequency [GHz]
10
12
Figure 5.3: |s11 | for the simulated single-ended via test cases.
From the time domain response, the reflections caused by the via appears to be
a much bigger issue, adding almost 15 % of the signal level to the consecutive
bit, or bits, of a presumed digital signal. More importantly, this effect may not
only be limited to very fast multi-gigabit signals, as the effect of the reflected
signal may appear at the transmitter for a relatively long time, dependent
on the distance to the discontinuity2 . This is a very interesting observation
that tends to hold in general for the studied nets. From figure 5.3, this poor
magnitude response can be seen for the whole frequency band studied.
2
This can be compared with the example in section 2.3.6.
84
Chapter 5. Analysis of the routing effects
Looking at the TDR/TDT response as shown in figure 5.2, one may falsely
believe that this is a minor issue. Although already mentioned, it will therefore
be stressed again that these cases show the impact under ideal conditions,
with, for instance, perfect terminations, perfect applied signals and only one
single via. In practice, it is quite likely that several such small contributions,
when interacting under non-ideal conditions, in fact may ruin the signal. For
this reason, ways to mitigate these effects are still relevant to analyze.
The two main contributors for these via effects was assumed to be the long
via stubs and the capacitive coupling between the unconnected via pads and
the ground planes. This assumption was later confirmed through Momentum simulations. Based on this assumption, the following improvements were
suggested:
• Remove via pads
• Remove stub3
• Use two vias to reduce stubs
These improvements are conceptually depiced in figure 5.4.
(a) Default via.
(b) Pads removed.
(c) Stub removed.
(d) Two vias.
Figure 5.4: Suggested via improvements.
It should be noted that none of these suggestions are visionary, but fully
implementable for a typical PCB design for an additional cost. To analyze the
3
This is accomplished using back-drilling.
5.1. Impact from vias
85
1.0
Magnitude
0.8
0.6
0.4
0.2
0.00
Stub removed
Pads removed
Two vias, pads removed
Two vias
Unmodified
Stripline only
1
2
3
frequency [GHz]
4
5
Figure 5.5: Simulated result for |s21 | for the different via improvements that
were suggested.
1.0
Stub removed
Pads removed
Two vias, pads removed
Two vias
Unmodified
Stripline only
Magnitude
0.8
0.6
0.4
0.2
0.00
1
2
3
frequency [GHz]
4
5
Figure 5.6: Simulated result for |s11 | for the different via improvements that
were suggested.
86
Chapter 5. Analysis of the routing effects
impact of these suggestions, models for these vias were created and simulated
using Momentum. The results can be seen in figures 5.5 and 5.6.
Voltage [V]
0.20
0.15
0.10
T11 - Stub removed
T11 - Pads removed
T11 - Two vias, pads removed
T11 - Two vias
T11 - Unmodified
T11 - Stripline only
T21 - Stub removed
T21 - Pads removed
T21 - Two vias, pads removed
T21 - Two vias
T21 - Unmodified
T21 - Stripline only
0.05
0.00
0.05
0.2
0.4
0.6
time [ns]
0.8
1.0
Figure 5.7: TDR/TDT responses for the the different via improvements suggested.
As expected, and as can be seen from these figures, removing the via stub
completely is the most efficient approach over the whole frequency range. A
closer look at the frequency range around a few hundred megahertz up to one
gigahertz reveals that this method actually has a higher reflection than the
unmodified via. But for these frequency components, a slight mismatch will
hardly be noticable for a digital signal and from figure 5.7, it can clearly be seen
that this approach has a rather big advantage. For instance, compared to the
unmodified via, the capacitive reflection from the via with the stub removed
is reduced by more than 60 % and the duration is significantly reduced as
well. It can also be noted that the least beneficial approach is to place two
vias close to each other, as that will prolong the effect of the different via
impedance, which tend to have more impact on the signal than the stub itself.
That makes this method counterproductive and therefore it is discouraged.
The results obtained from the corresponding differential test cases are plotted
in figures 5.8 through 5.10. Although these results in principle are the same,
the performance advantage of using a differential pair is clearly visible; with
both smaller reflections and lower transmission loss.
Finally, mode conversions were also studied for all the via test cases, but under
these ideal circumstances these were neglectable.
5.2. Crosstalk behaviour
87
1.0
Magnitude
0.8
0.6
0.4
0.2
0.00
Stubs removed
Pads removed
Two via pairs, pads removed
Two via pairs
Unmodified
Stripline only
1
2
4
5
3
frequency [GHz]
6
7
8
Figure 5.8: |sdd21 | for the suggested via improvements.
1.0
Stubs removed
Pads removed
Two via pairs, pads removed
Two via pairs
Unmodified
Stripline only
Magnitude
0.8
0.6
0.4
0.2
0.00
1
2
4
5
3
frequency [GHz]
6
7
8
Figure 5.9: |sdd11 | for the suggested via improvements.
88
Chapter 5. Analysis of the routing effects
0.25
Voltage [V]
0.20
0.15
TDD11 - Stubs removed
TDD11 - Pads removed
TDD11 - Two via pairs, pads removed
TDD11 - Two via pairs
TDD11 - Unmodified
TDD11 - Stripline only
0.10
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55
time [ns]
Figure 5.10: Differential TDR responses in close-up for the suggested via
improvements.
1.0
Transmission measured
Transmission simulated
Near-end crosstalk measured
Near-end crosstalk simulated
Far-end crosstalk measured
Far-end crosstalk simulated
Magnitude
0.8
0.6
0.4
0.2
0.00
1
2
4
5
3
frequency [GHz]
6
7
8
Figure 5.11: Example showing s-parameter magnitude functions for a typical
crosstalk situation, obtained through both simulations and measurements.
5.2. Crosstalk behaviour
5.2
89
Crosstalk behaviour
The crosstalk test traces were the next group up for closer examination. As
was done for all the analyzed test traces, test data obtained from measurements and simulations were compared, in order to validate the accuracy of
the performed simulations in general and the accuracy of crosstalk simulations in particular for this case. Again, good correlation was obtained for
all the traces, indicating that Momentum simulator can reliably be used for
simulating crosstalk. An example of this correlation is plotted in figure 5.11,
for a randomly selected test structure4 .
Figure 5.12: Magnitude function of the near-end - and far-end crosstalk parameters, s31 and s41 , for the single-ended crosstalk test structures with 50 mm
crosstalk sections, plotted in logarithmic scale. For each case the near-end
level is higher than the far-end level. Distances are given as the smallest
edge-to-edge distance between the aggressor- and victim traces.
The main goal of the crosstalk analysis was to investigate how the amount of
crosstalk is dependent on the distance between the conductors and how well
this coupling can be predicted through simulation using s-parameter data. For
a steady-state sinusoidal stimulus, the amount of crosstalk will basically only
be determined by the distance between the conductors, and not by the length
4
The reflection parameter also showed good correlation in this case, but was omitted in
this figure for aesthetic reasons.
90
Chapter 5. Analysis of the routing effects
that they run in parallel nor the frequency of the stimulus5 . Therefore, when
analyzing the amount of crosstalk in this case, represented by the magnitude
function of the crosstalk s-parameters, any of the three lengths included in
the test board can be analyzed. The simulated magnitude functions of the
near-end and far-end crosstalk parameters for the test structures with 50 mm
crosstalk sections are shown in figure 5.12. As expected and motivated in
section 2.4, the near-end crosstalk is dominant. In fact, with the exception
of the broadside coupled traces, the far-end crosstalk is neglectable. For both
cases, the amount of crosstalk will clearly diminish as the distance between the
conductors increase, as indicated in this figure as the edge-to-edge distance.
Figure 5.13: Near-end and far-end crosstalk levels for the single-ended 50 mm
crosstalk sections, given as a percentage of the aggressor voltage level. For each
test case, the near-end crosstalk level is higher than the far-end counterpart.
For a typical digital signal with non-zero rise time, on the other hand, the peak
crosstalk level, will apparently also be dependent on the parallel trace length
for the crosstalk section as was described in section 2.7.1.2. The maximum,
or worst case, crosstalk level will still only be a result of the distance between
the two conductors, an example of which is shown in figure 5.13, but if that
will be reached is determined by rise- or fall time of the signal; maximum
crosstalk level will be reached if this time is shorter than the time it takes for
the signal to propagate through the crosstalk region.
5
The decaying crosstalk magnitude function is mostly due to the decaying aggressor
voltage level, which in turn is due the transmission line losses.
5.3. Evaluation of various practical routing situations
20
// 10 mm - 100 ps
// 10 mm - 500 ps
// 30 mm - 100 ps
// 30 mm - 500 ps
// 50 mm - 100 ps
// 50 mm - 500 ps
15
Crosstalk [%]
91
10
5
0
0.0
0.5
1.0
time [ns]
1.5
2.0
Figure 5.14: Single-ended near-end cross talk levels for different broadside
crosstalk section lengths, for an aggressor with 100 ps and 500 ps rise time.
This can intuitively be understood from the crosstalk transmission line model,
described in section 2.4.1, where coupling through the mutual inductances and
capacitances only will occur during changing current or voltage. This implies
that the rise time, and not the data speed, should be used as the main criterion
when putting constraints on maximum allowed parallel length, which probably
is old news.
Similar results could also be achieved for the differential crosstalk cases, but
are not presented here.
5.3
Evaluation of various practical routing
situations
Besides the important via- and crosstalk test cases, a few other test cases that
might cause signal integrity issues in a practical PCB design were analyzed.
In general, also these simulation results showed good correlation with the
measured results. However, due to very long simulation times, the test case
where a test trace was passing through a field of ground vias, as was described
in section 4.1.4, was not evaluated.
92
5.3.1
Chapter 5. Analysis of the routing effects
Non-solid reference planes
1.0
Magnitude
0.8
0.6
s21 (s.e. test case)
sdd21 (diff. test case)
s11 (s.e. test case)
sdd11 (diff. test case)
0.4
0.2
0.00
1
2
4
3
frequency [GHz]
5
6
Figure 5.15: Magnitude functions for transmission- and reflection s-parameters
for single-ended and differential non-solid ground planes test cases.
One typical practical situation is that of non-solid ground planes, where the
reference plane for a signal, for a limited distance has to be removed for
reasons explained in section 4.1.4 previously. To verify the effect of such
discontinuity for the return current, and how accurately it can be simulated,
one test case, including one single-ended trace and one differential pair, was
implemented on the test board. After establishing the simulation accuracy
for the complete structure, the magnitude functions for the reflection- and
transmission s-parameters for the stripline sections could be compared, as
shown in figure 5.15. In this figure, superior performance of the differential
pair in such situation is evident. This behaviour is also clearly reflected in the
time domain response as plotted in figure 5.16, where the differential signal,
as opposed to the single-ended counterpart, is hardly affected by the opening
in the reference plane.
5.3.2
Change of differential pair spacing
For reasons motivated in section 4.1.4, when connecting a differential pair to
a larger circuit, the spacing between the conductors within the pair may have
to be changed. Two situations may occur; either they have to be squeezed
together, increasing the coupling within pair, or they have to be splitted,
5.3. Evaluation of various practical routing situations
93
T21 (s.e. test case)
TDD21 (diff. test case)
T11 (s.e. test case)
TDD11 (diff. test case)
0.25
Voltage [V]
0.20
0.15
0.10
0.05
0.00
0.05
0.2
0.4
0.6
0.8
time [ns]
1.0
Figure 5.16: TDR/TDT response for the corresponding test cases as shown
in figure 5.15, for an applied voltage step with 100 ps rise time.
1.0
Magnitude
0.8
0.6
sdd21 - Pair splitted
sdd11 - Pair splitted
sdd21 - Decreased pair spacing
sdd11 - Decreased pair spacing
sdd21 - Straight stripline
sdd11 - Straight stripline
0.4
0.2
0.00
1
2
4
5
3
frequency [GHz]
6
7
8
Figure 5.17: Magnitude functions for transmission- and reflection s-parameters
for a situation where the pair spacing is altered.
94
Chapter 5. Analysis of the routing effects
0.25
Voltage [V]
0.20
0.15
0.10
0.05
TDD21 - Pair splitted
TDD11 - Pair splitted
TDD21 - Decreased pair spacing
TDD11 - Decreased pair spacing
TDD21 - Straight stripline
TDD11 - Straight stripline
0.00
0.05 0.1
0.2
0.3
0.4 0.5
time [ns]
0.6
0.7
0.8
Figure 5.18: Differential TDR/TDT response for two test cases where the
differential pair spacing is change, for an applied signal with 50 ps rise time.
forcing the two conductors of the pair to act individually. For the test case
corresponding to the former situation, only a small change in spacing was
used, which makes a strict comparison between the two unfair. Still, the two
situations are plotted together in figures 5.17 and 5.18. From this result it can
be concluded that splitting a differential pair should be avoided when possible,
but at the same time, if absolutely necessary it would most likely work for a
shorter section. It should be noted here that this is under perfect conditions
and for a weakly coupled pair, in other words; in practice the situation might
be different.
5.3.3
Serpentine delay line
For the serpentine delay line, included in the test board, it was found that its
impact, in terms of reflection and transmission characteristics, is neglectable
and this structure should be safe to use, even for high-speed signals. For
convenience, these results are not plotted here.
5.4. A quick comparison with a faster simulator
5.4
95
A quick comparison with a faster simulator
Thus far, the impact on signal integrity for various routing situations have
been analyzed. Methods have been developed and verified for accurate prediction of this behaviour. However, using an advanced, full-wave two-and-a-halfor three-dimensional EM field solver comes with price; it requires massive
computational resources. Consequently, this is not a general purpose solution, that for instance efficiently can be applied to a larger set of high-speed
signals in a digital design. Rather, it should be considered as a complement to
a simpler, but faster two-dimensional, or cross-sectional, field solver. Reliable
application of such simulator requires a good understanding of its limitations
to determine when use is appropriate.
Quite a few different simulators of this kind are available, and the focus may
be either on pre-route or post-route simulations. Typically, pre-route signal
integrity tools can be used in the early design phase, to analyze various design
decisions, before the layout is made, and the focus is therefore normally on
small scale, with the ability to fine tune various design parameters. Postroute simulation tools on the other hand, normally focuses on large scale,
batch simulations, that are used to validate a larger set of nets for design
errors or locate weak spots from a signal integrity point of view. For the
latter, the importance of tight integration with the layout tool is of significant
importance for efficient application. One thing these simulators normally have
in common is the ability to represent a layout by transmission line segments,
that may be coupled, and they also provide approximate via models. But
what performance can be achieved, compared to the accurate results obtained
by a sophisticated EM field solver like Momentum?
From the perspective of this thesis, this is important to understand in order
to improve efficiency, without sacrifying acccuracy when simulating critical
structures. The aim here is not to give a thorough analysis of any simulator,
but rather to give a few examples of what can be achieved and what cannot.
R 6 , which falls under the post-route
Here, for the proof of concept, HyperLynx
simulation category, will be used. This choice was basically based on the fact
that this application already had been used early on in the project, and simple
configuration.
To perform the comparison the board layout was simply imported into the
R part of HyperLynx,
R and the software was configured with the
BoardSim
same nominal material properties as was previously used for the Momentum
simulations. Thereafter, one at a time, each net to be analyzed was exported to
R from where the nets could be configured to resemble the test traces
LineSim,
simulated by Momentum, before finally simulating the s-parameters. The
6
R version 8.0 was used with the accompanying
To be more specific, HyperLynx
Eldo/ADMS simulator.
96
Chapter 5. Analysis of the routing effects
actual simulation for each section could be executed in a matter of seconds,
as opposed to the Momentum simulator in microwave mode, requiring many
hours up to days on a normal workstation computer.
5.4.1
Simulating a straight stripline
The most fundamental sub-block that requires efficient, but accurate modelling is the straight stripline section. A simulator failing to deliver good
results for this element, can probably not be expected to provide any useful information for any interconnect analysis. Thus, the analysis started by
looking closer at such a case.
1.0
Magnitude
0.8
0.6
s21 - HyperLynx
s21 - Momentum
s11 - HyperLynx
s11 - Momentum
0.4
0.2
0.00
2
4
6
8
10
frequency [GHz]
12
14
Figure 5.19: Magnitude function comparison between Momentum and
R for a 46 mm straight stripline.
HyperLynx
The results from this test is plotted in figure 5.19, showing the magnitude
function of the s-parameters for a single-ended straight stripline. As can be
R turned out to perform as well as the Momentum simuseen, HyperLynx
R
lator, indicating that the high frequency loss models used by HyperLynx
were reasonably good. Similar correlation could be found for the differential
reflection- and transmission s-parameters.
5.4. A quick comparison with a faster simulator
0
Near-end crosstalk - HyperLynx
Near-end crosstalk - Momentum
Far-end crosstalk - HyperLynx
Far-end crosstalk - Momentum
10
20
Magnitude [dB]
97
30
40
50
60
70
80
0
2
4
6
8
10
frequency [GHz]
12
14
Figure 5.20: Crosstalk simulation results, comparision between Momentum
R for crosstalk between two traces routed in the same layer,
and HyperLynx
with a edge-to-edge distance of 150 um.
5.4.2
Crosstalk simulations
The next key area for successful signal integrity simulations is probably that
of predicting coupling, or crosstalk, between traces routed close in proximity.
Again, very good correlation with the Momentum simulations was obtained,
an example of which is plotted in figure 5.20 for two single-ended traces routed
with a spacing of 150 µm at the same layer. Similar correlation could be found
for other distances, and for traces in different layers. Note that the small
deviation in frequency that can be observed is not caused by the simulator
R with respect
itself, but rather by incorrectly set trace length in HyperLynx
to the length of the structure used in Momentum.
5.4.3
Via models
Next up for a closer look was the via models. As can be seen from figure
R follows the characteristics of the
5.21, the via model used by HyperLynx
corresponding structure in Momentum high up in frequency, and this model
can be expected to perform well, even for fast signals. It was found, however,
that making changes to the via model, such as removing the via pads, as
was suggested in section 5.1, the accuracy will deteriorate. This example is
98
Chapter 5. Analysis of the routing effects
1.0
Magnitude
0.8
0.6
0.4
0.2
0.00
2
4
s21 - HyperLynx
s21 - Momentum
s11 - HyperLynx
s11 - Momentum
6
8
10
frequency [GHz]
12
14
Figure 5.21: Magnitude function comparison between Momentum and
R for a single-ended via.
HyperLynx
1.0
Magnitude
0.8
0.6
0.4
s21 - HyperLynx
s21 - Momentum
s11 - HyperLynx
s11 - Momentum
0.2
0.00
2
4
6
8
10
frequency [GHz]
12
14
Figure 5.22: The same situation as was shown in figure 5.21, but with via
pads removed.
5.4. A quick comparison with a faster simulator
99
shown in figure 5.22. But how much will this affect the time domain signal
with a 100 ps rise-time? The answer is; hardly at all, which can be seen from
figure 5.23, which is due to the fact that this deviation occurs very high up in
frequency.
0.25
Voltage [V]
0.20
0.15
0.10
0.05
0.00
0.050.1
T21 - HyperLynx
T21 - Momentum
T11 - HyperLynx
T11 - Momentum
0.2
0.3
0.4 0.5
time [ns]
0.6
0.7
0.8
Figure 5.23: Time domain response for via impact in the case plotted in figure
5.21, when a 100 ps signal is applied.
Rather good agreement could also be obtained for the differential via case. The
reflection- and transmission characteristics of such a case is shown in figure
5.24, where very good agreement can be seen as high up as five gigahertz.
R automatically
It can be noted here that this via simulation in HyperLynx,
R also provides a
were exported as two single-ended vias, although HyperLynx
R
differential via model. No coupling will occur for the vias in a HyperLynx,
regardless of the model used. The only difference of using the differential
model is that the impedance of each transmission line, as modeled in the via
model, will increase with smaller distance between the two vias. Apparently,
this was not of great importance for accurate reflections- and transmission
modeling in this case.
5.4.4
Limitations
The way this comparison with a simple field solver has been presented so far
may be deceptive, as the agreement have be shown to be good or even as
good as more sophisticated EM software, the performance of which in turn
100
Chapter 5. Analysis of the routing effects
1.0
Magnitude
0.8
0.6
0.4
0.2
0.00
2
4
sdd21 - HyperLynx
sdd21 - Momentum
sdd11 - HyperLynx
sdd11 - Momentum
6
8
10
frequency [GHz]
12
14
Figure 5.24: Comparison of the characteristics for a differential via pair, going
from layer three to layer four.
has been verifed through practical measurements, as described previously in
this chapter. One has to keep a few things in mind however. The test cases
analyzed here are close to ideal, which may be quite far from a practical
situation.
One important thing that is normally not taken into account for a tool like
R is that of partial, or non-solid, ground planes, which instead are
HyperLynx
modelled as stripline segments with the same impedance as for the ideal case,
thereby introducing an error as large as could be seen previously in figures
5.15 and 5.16, when analyzing this effect.
This is a typical example where use of a more advanced simulation tool is motivated. Generally, this will be true for all cases where the physical appearance
of the structure differs from the ideal. This may not only include physical
variations in the surrounding of a trace, but may also apply to the conductors themselves, for instance leading to a phase shift between the signals in a
differential pair.
Although not of importance for the traces studied here, mode conversions is
another phenomena, closely related to the physical nature of the traces that
did not appear to be handled properly.
6
Conclusions and future work
6.1
What have been learned so far?
In this thesis the impact various interconnect designs may have on signal
integrity have been demonstrated. For instance, the design of vias has been
proved to play a vital role for a successful high-speed design and so have nonsolid reference planes for single-ended signals. At the same time, other ways
of routing that are typical for digital designs, such as the use of the serpentine
delay line, has been proved to be rather safe to use.
These results will probably not come as a surprise to anyone with the slightest
experience within the signal integrity field and are per se not very exciting.
More interesting, however, is probably the way these results accurately and reliably could be obtained and verified. Good agreement as high up in frequency
as ten gigahertz has been shown.
When making this comparison two things should always be kept in mind;
firstly, regardless of the simulation tool used, it is just based on a model of
the real world and, secondly, what is measured is not always exactly what is
simulated, for instance due to the unavoidable impact of the used measurement equipment and board variations. Or put differently; it is rather naive
to believe that perfect correlation can be accomplished, with inaccuracies in
the model used and with tolerances and variations for the measurement itself. Understanding and awareness of the limitations for the used simulation
techniques is essential for successful application in a high-speed digital design
process. Knowledge and confidence in different techniques and what can be
expected in practice will further improve design efficiency and the likelyhood
for success. For a more complex design, where the conditions often are far
from the ideal and many tradeoffs have to be made, this may even prove
critical.
101
102
6.1.1
Chapter 6. Conclusions and future work
Simulation techniques
In this thesis it has been shown that most typical situations accurately can be
predicted using a planar three-dimensional EM field solver like Momentum,
using only nominal values for the material properties. Although possible,
this is too inefficient to be generally applicable. Instead, it is here suggested
that such simulator is used as a complement to a faster two-dimensional field
solver, that is applied wherever appropriate. If used correctly, this can be
done without sacrificing accuracy, as two-dimensional field solver software
for certain situations have been shown to perform even as good as a threedimensional field solver, but in a fraction of the time. Thus, the best approach
for achieving accurate simulation results in reasonable time is to divide the
interconnect to be analyzed into sub-blocks, from which the s-parameters are
extracted through simulations using the simulator most appropriate for the
particular sub-block. These sub-blocks can then be connected without loosing
significant accuracy in a fast simulator, as also have been shown in this report1 .
How this division should be made may not be as straight forward as for the
cases demonstrated in this report, and in general these decisions have to be
made on a case-to-case basis, based on previous verification work, similar to
the verification work shown in this report. Typically, structures with ideal
geometry, for instance straight traces with solid reference planes, are good
candidates for a two-dimensional simulation. On the other hand, traces with
non-ideal geometry, such as non-ideal reference planes and pad connections,
lend themselves better for a three-dimensional field solver for reliable results.
Strictly, by being a geometry dependent structure, vias would be expected to
fall into the latter category, but as vias are a fundamental part of any PCB
design, good enough models might be available in a two-dimensional field
R Changing the geometry
solver application, as was the case for HyperLynx.
may not always yield the expected results, as was found when removing the
R via model. For a typical design, where the
via pads from the HyperLynx
number of different via types used are rather limited, for accurate simulations
it is here suggested that a small library with these vias are created using a
three dimensional field solver. Obviously, these are just very general guidelines
and the choices made must continuously be validated, both through other
simulations and new measurements, as designs and boards evolve.
One interesting phenomena that has been mentioned in this thesis, is that of
non-ideal return currents, for instance causing crosstalk where it might least
be expected. This was not investigated in this thesis, but appears as one
thing that cannot easily be integrated into the ordinary simulation flow. Care
1
Unfortunately, it was found that this methodology is currently not well supported in
R as the simulator used for handling s-parameter blocks is very slow. This is
HyperLynx,
much better handled in ADS.
6.1. What have been learned so far?
103
should be taken to avoid such situations at all, by providing proper return
paths wherever possible.
6.1.2
Measurement methods
The validation of simulation results through measurements can preferably be
done using a VNA with microwave probes, as was the most suitable solution
found in this project. TDR/TDT can also be used for interconnect analysis,
but is considered more appropriate for troubleshooting than characterization,
mainly due to lack of accurate calibration methods, due to lower measurement
accuracy in terms of dynamic- and frequency range, and due to less versatile
form of the output data. TDR/TDT still comes with some advantages, for
instance the ease of locating discontinuities. As have been shown in this thesis,
having a s-parameter representation of an interconnect, this analysis might as
well be done in software, where much higher time resolution additionally can
be achieved. In a similar fashion, having a s-parameter representation of an
interconnect, arbitrary stimulus can be inserted.
For the VNA measurements, using a two-tier calibration process is still considered to be the most convenient approach, as it separates calibration substrateand test object measurements. The use of the LRM calibration algorithm
might be debatable, especially due to the equal match requirement. How the
accuracy will be affected when this requirement is not met have not been further investigated in this thesis, but is clearly something that should be done.
Perhaps a modification of the LRM algorithm, known as the LRRM, should
be used instead, as that algorithm only requires one match standard.
In order to use the microwave probes, the test board must be prepared for the
probing, as was the case with the test board used in this project. However,
according to the initial plan for the project, ways of analyzing a bare board
for a final product was desired. This failed because ground could not be
made accessible close enough to the signal pads of interest when using manual
methods. Using probes with larger pitch is not a solution as the high-frequency
characteristics of such probes basically were found not to be good enough2 .
Besides adding extra ground pads at appropriate distances from signal pads
of interest, there only appears to be one way to characterize the interconnects
of a PCB built for a product through probing. It should be noted that making
special signal test pads on the board is clearly not an option due to the negative
impact this will have on the interconnect, mostly due to the introduced stubeffect. Assuming the top layer to be filled with copper, leaving out the solder
mask and thereby exposing this copper for the boards to be tested, could make
2
The author would not recommend probes with anything but smaller than 750 µm
pitches and in GSG configuration.
104
Chapter 6. Conclusions and future work
probing possible. But surely, for a dense layout, it will probably not work for
every signal of interest. The clear advantage is that it will not require any
design changes. Still, the usefulness of the result from such a board with
many unterminated traces, is questionable. If this is taken into account in the
simulations, however, it is reasonable to assume that this will not pose that
much of a problem.
6.2
For the future
In this thesis methods for analyzing PCB interconnects for high-speed digital
signals have been developed. Although working methods have been proposed,
this is considered a continuous work as both techniques and designs evolve,
and additionally, new situations emerge, as have already been discussed. But
the interconnect is only part of the communication channel. For predicting
practical behaviour, equally important is the ability to model the connecting
circuits and connectors. Similar methods as found in this thesis would most
likely be extendable to also include this part of the channel. This could for instance be wafer-to-PCB characterization, where full 3d-models of bond-wires
and pins would be created. Once results from simulations and measurements
show good agreement, the simpler IBIS or IBIS AMI models can be investigated.
Additionally, it would also be interesting to characterize the impact of highimpedance probing on such interconnects, in order to allow for accurate verification of high-speed interconnects on a final product.
Clearly, a lot of issues can be identified and will require further analysis within
this field, especially as serialized interfaces are gaining ground for on-board
interfaces. Full understanding of every important aspect will allow both performance and speed to be pushed to the next level. This thesis is just a first
very small step in that direction.
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Abbreviations
ADS
Advanced Design System, electronic design automation software from Agilent Technologies
used for circuit simulations.
CM
Common Mode; the common voltage component of a differential signal, defined as the common voltage level of two nodes within the pair;
UCM = (U1 + U2 )/2. See section 2.2.
DM
Differential Mode; differential voltage component of a differential signal, defined as voltage
difference between two nodes within the pair;
UDM = U1 − U2 . See section 2.2.
Differential Time Domain Reflectometry, TDR
when a differential signal is applied to the
DUT.
Device Under Test, term used to refer to the
object that is tested, typically in a measurement assembly.
DTDR
DUT
FR-4
Flame Retardant 4; standard class of glass
reinforced epoxy materials commonly used in
PCBs as dielectric material. See also section
2.1.1.
GUI
Graphical User Interface is the part of a computer software application that allows the user
to interact with the application, typically using
clickable menus and buttons rather than text
commands.
109
110
Abbreviations
HFFR-4
Halogen Free FR-4, see FR-4.
KCL
Kirchhoff’s Current Law states that all current
entering any node in an electric circuit is equal
to the current leaving that same node.
Kirchhoff’s Voltage Law states that the sum of
all voltages in any closed loop is equal to zero.
KVL
LRM
Line-Reflect-Match, method used for VNA calibration requiring three calibration standards,
see section 3.6.1 and section 3.6.4.
MLB
Multilayer Board, PCB made up of three or
more conducting layers, see section 2.1.1.
OSM
Open-Short-Match, method used for VNA calibration, typically only used for one-port calibrations, see section 3.6.3.
PCB
Printed Circuit Board, board onto which electronic components are mounted and through
which they are interconnected to form an electronic system. See section 2.1 for a brief introduction.
Pure-Mode Vector Network Analyzer; VNA
that can apply and sense DM and CM signals
to the DUT, the advantages of which are discussed in section 2.6.2.1. See also VNA.
Printed Wiring Board, more often referred to
as printed circuit board, see PCB.
PMVNA
PWB
SMA
SOLT
TDR
TDT
SubMiniature version A, 50 ohm coaxial RF
connector with a bandwidth of 18 GHz.
Short-Open-Load-Thru, method commonly
used for VNA calibration involving four calibration standards, see section 3.6.1.
Time Domain Reflectometry is a common measurement technique employed to characterize
electrical interconnects by observing the reflected waveform, see section 2.7.1.
Time Domain Transmission, like TDR but the
transmitted signal is observed instead of the
reflected. See section 2.7.1.
Abbreviations
VNA
111
Vector Network Analyzer; instrument that
measures network parameters, typically sparameters, see section 2.7.2.
List of Figures
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
Simple PCB stack-up. . . . . . . . . . . . . . . . . . . . .
The two basic types of traces used in PCB design. . . . .
Three different via types. . . . . . . . . . . . . . . . . . .
Fourier series of trapezoidal signal. . . . . . . . . . . . . .
Frequency spectrum of trapezoidal signal. . . . . . . . . .
Electric- and magnetic fields. . . . . . . . . . . . . . . . .
Distributed transmission line model. . . . . . . . . . . . .
Lossless transmission line equivalent circuit. . . . . . . . .
Skin effect. . . . . . . . . . . . . . . . . . . . . . . . . . .
Skin effect – resistance vs. frequency. . . . . . . . . . . . .
Skin effect and surface roughness. . . . . . . . . . . . . . .
Lossy transmission line per-unit-length equivalent circuit.
Impedance discontinuity – example circuit. . . . . . . . .
Impedance discontinuity – example response. . . . . . . .
Three conductor crosstalk model. . . . . . . . . . . . . . .
Three conductor crosstalk equivalent circuit. . . . . . . .
Simple two-port network. . . . . . . . . . . . . . . . . . .
Cascaded four-ports. . . . . . . . . . . . . . . . . . . . . .
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6
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9
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18
18
19
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23
25
26
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32
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
Data management – first approach. . . . . . . . . .
R data flow. . . . . . . . . . . . . . . .
HyperLynx
Microwave probe. . . . . . . . . . . . . . . . . . . .
Probe tip – microwave probe. . . . . . . . . . . . .
Probe tip – microwave probe 2000µm. . . . . . . .
Twelve-term system error model. . . . . . . . . . .
Microwave probes 2000 µm thru test configuration.
Microwave probes 2000 µm thru test plot. . . . . .
Probe calibration – open standard measurement. .
Probe calibration – short standard measurement. .
Probe calibration – load standard measurement. .
Two-tier calibration concept. . . . . . . . . . . . .
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41
42
44
45
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47
48
49
50
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51
51
113
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114
List of Figures
3.13
3.14
3.15
3.16
Three-term system error model. . . . . . . . . .
Equivalent circuits for calibration standards. .
Probe load standard – Measured vs. eq. circuit
LRM system error model. . . . . . . . . . . . .
. . . .
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model.
. . . .
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
Single-ended crosstalk test cases. . . . . . . . . . . .
Test board – Single-ended crosstalk test traces. . . .
Test board – Differential crosstalk test traces. . . . .
Test board – via effect. . . . . . . . . . . . . . . . . .
Test board – Non-ideal current return path 1. . . . .
Test board – Non-ideal current return path 2. . . . .
Situations for differential pair under a circuit. . . . .
Test board – length match. . . . . . . . . . . . . . .
Layout of single-ended test structure. . . . . . . . .
Layout of differential test-structure. . . . . . . . . .
Test board stack-up. . . . . . . . . . . . . . . . . . .
Relative permittivity of dielectric used in test board.
Loss tangent of dielectric used in test board. . . . .
500 µm probes – extracted return loss. . . . . . . . .
500 µm probes – extracted insertion loss. . . . . . .
Circuit simulator equivalent circuit. . . . . . . . . .
Simulation sub-block verification. . . . . . . . . . . .
Simulation problem due to finite gnd planes. . . . .
Simulation vs. measurement – s21 ,s12 ref. trace. . .
Simulation vs. measurement – s11 ref. trace. . . . .
Simulation – impact of via at test port 1. . . . . . .
Simulation – impact of via at test port 2. . . . . . .
Simulation – impact of via at test port 3. . . . . . .
TDR/TDT simulation circuit. . . . . . . . . . . . . .
TDR/TDT reference trace 50 ohm. . . . . . . . . . .
TDT reference trace – Osc. vs VNA. . . . . . . . . .
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
|s21 | single-ended via test cases. . . . . . . . . . . . .
Single-ended via TDR/TDT performance. . . . . . .
|s11 | single-ended via test cases. . . . . . . . . . . . .
Suggested via improvements. . . . . . . . . . . . . .
|s21 | single-ended via improvements. . . . . . . . . .
|s11 | single-ended via improvements. . . . . . . . . .
TDR/TDT single-ended via improvements. . . . . .
|sdd21 | for via improvements. . . . . . . . . . . . . .
|sdd11 | for via improvements. . . . . . . . . . . . . .
TDR differential via improvements. . . . . . . . . . .
Crosstalk – Measurement vs. simulation. . . . . . . .
Crosstalk at different distances – frequency domain.
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List of Figures
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
Crosstalk at different distances – time domain. . .
Crosstalk for different parallel lengths. . . . . . . .
Non-solid reference plane – s-parameters. . . . . .
Non-solid reference plane – TDR/TDT. . . . . . .
Change of differential pair spacing – s-parameters.
Change of differential pair spacing – TDR/TDT. .
R stripline. . . . . . . . . . . . . . . . .
HyperLynx
R crosstalk comparison. . . . . . . . .
HyperLynx
R via – frequency domain. . . . . . . .
HyperLynx
R via – frequency domain. . . . . . . .
HyperLynx
R via – time domain. . . . . . . . . . .
HyperLynx
R differential via – frequency domain. .
HyperLynx
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. 90
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. 100
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