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 Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
A Study of clocking techniques to reduce Simultaneous
Switching Noise (SSN) in on-chip application
Master thesis performed in Electronic Devices
by Sahar Kashfolayat
Sahar Kashfolayat
LiTH-ISY-EX--11/4460--SE
03.03.2011
TEKNISKA HÖGSKOLAN
LINKÖPINGS UNIVERSITET
Department of Electrical Engineering
Linköping University
S-581 83 Linköping, Sweden
Linköpings tekniska högskola
Institutionen för systemteknik
581 83 Linköping
2 A Study of clocking techniques to reduce Simultaneous Switching Noise (SSN)
in on-chip application
Master thesis in Electronic Devices
at Linköping Institute of Technology
by
Sahar Kashfolayat
LiTH-ISY-EX--11/4460--SE
Supervisor: Behzad Mesgarzadeh
Examiner:Behzad Mesgarzadeh
Linköping 03.03.2011
3 4 Acknowledgement What is covered here is the result of what I have done as my master thesis at Department of Electrical Engineering, Electronic Devices. Herewith, I would like to express my sincere appreciation to all of those people especially at the Electronic Device who supported my thesis work. I should not forget to sincerely and deeply thank my mother for all of her non-­‐stop support, understanding and even her existence in Linkoping with all the difficulties. She was the only reason to make an impossible, possible for me. Thank you. 5 6 Table of Contents Acknowledgement ............................................................................................................ 5 1. CHAPTER 1 ................................................................................................................ 10 1. 2. 3. 4. INTRODUCTION ................................................................................................................ 10 What is SSN (Simultaneous Switching Noise) .................................................................... 10 What cause of SSN and the solution for SSN problem ....................................................... 11 Reduction by controlling intrinsic features of the circuit ................................................... 11 5. Reduction of SSN by applying different clock shapes .......................................................... 15 6. Modeling of SSN ................................................................................................................... 17 7. Analyzing of SSN ................................................................................................................... 18 8. Summary .............................................................................................................................. 18 2. CHAPTER 2 ................................................................................................................ 20 1. 2. Mathematical background ................................................................................................ 20 Slope effect on noise ........................................................................................................ 20 3. Rise/Fall time ....................................................................................................................... 20 4. Different clock shapes .......................................................................................................... 23 5. Power consumption in clocking network ............................................................................. 26 3. Chapter 3 .................................................................................................................. 29 1. 1. 2. Implementation ................................................................................................................ 29 Conventional Rectangular Clocking ................................................................................... 29 Proposed Clocking Networks ............................................................................................ 31 1. Multi-­‐Segment Clocking Network ........................................................................................ 31 2. Harmonic suppressed Clocking Network ............................................................................. 33 3. Summary .......................................................................................................................... 37 4. Chapter 4 .................................................................................................................. 38 1. 2. 3. 4. Simulation and Results ..................................................................................................... 38 Comparison between square shape clock and sinusoidal shape clock ............................... 38 Comparison between conventional clock, multi-­‐segment clock and sinusoidal clock shapes
42 Summary .......................................................................................................................... 46 5. Refrences ................................................................................................................. 47 7 To My Mother
____________________________________
8 ABSTRACT
Simultaneous Switching Noise (SSN) is one of the major problems in today highspeed circuits. Power-Ground voltage fluctuation is significantly increasing due to
! ∗ (!" !" )) noise known as Power-Ground bounce and can be one major noise source in
modern and mixed-signal circuit design.
In this thesis first SSN and its sources are studied followed by some theoretical
analysis, then we present some clock shapes that cause in SSN reduction.
In this thesis, we investigate different clocking techniques in order to reduce SSN.
The effect of rise/fall time variation, applying sinusoidal, multi-segment and harmonic
suppressed clocks have been investigated and verified by proper circuit simulations.
Multi-segment clock shape and harmonic suppression clock shape produce less noise
in comparison to conventional clock, so using them as clock of the whole system can be act
as noise reduction technique.
9 1.
CHAPTER 1 1. INTRODUCTION Several different explanations for SSN (Simultaneous Switching Noise) have been
found in literature and will be mentioned during this chapter. When several output drivers
switch at the same time, they induce a voltage change in the power lines (VDD/VSS) known
as noise. This kind of noise changes the power lines voltage from their actual values. This
noticeable shift in the ground to the value that is not 0 and in the VDD to the value that is not
an expected value for it, is known as Simultaneous Switching Noise (SSN), or ground/VDD
bounce that cause from switching activity of the clock in high frequencies.
The ground bounce voltage comes from an inductance between the device ground and
the system ground Figure 1.1 [1], and the variation of the current which is sunk by the output
will generate noise. The equation which is used for the noise is ! ∗ !" !" . The value of
!"
!" increases with the number of simultaneous switches. This phenomenon will occur,
the same in VDD and cause deviation of the value of VDD from its nominal value.
2. What is SSN (Simultaneous Switching Noise) Figure 1.1. simultaneous switching noise 10 In other words, SSN is known as a noise voltage brought on a single pin on a device
due to the switching behavior of other provoker pins, Figure 1.2 shows a system that has
three pins, when the pins are switched all together, the noise caused by switching pins is
induced to the other non-switching pins [1].
Figure 1.2. System with three switching pins Simultaneous switching noise (SSN) has become a most important problem especially
in high-speed digital design, and it happens when so many electrical devices switch on or off
simultaneously, this change of voltage is happened so fast less; therefore high-speed devices
and digital circuits produce high frequency noise in their frequency range in which their
elements working.
One of the main goals of today integrated circuit design is having circuits and devices
as fast as possible. For having this high range of speed, high frequencies are needed and also
a large number of inputs and outputs are required. Although high frequencies give the
designers this opportunity to have fast chips, more simultaneous switching noise will be
injected into the circuit especially to the power lines. As everything in our world has trade
off, so finding the ways to have fast noiseless chips is one of the main concepts of designing
digital circuits these days and the designers should put so much effort on it to optimize the
digital circuits as much as possible.
3. What cause of SSN and the solution for SSN problem Techniques that reduce the simultaneous switching noise are very important also worth to
be studied because they would be major hidden spots of designer’s mind of high speed circuit
these days.
4. Reduction by controlling intrinsic features of the circuit There are some basic and fundamental features of the circuit can cause producing
SSN noise, like: bonding wires, bonding pads, traces, pins. These factors cause to generate a
way between the circuits on chip and on board. Resistance, capacitance and inductance of
that path decide the functionality and performance of the system [2].
The longest bonding wires in the circuit are placed at the corners and because they are
11 long, they have largest inductance and resistance, as it explained before parasitic elements
can cause more noise in power lines. In real circuits, having these noisy elements are
inevitable because every circuit consists of so many wires and the effect of SSN can not be
neglected, but with optimize designing these unwanted noise source elements could be reach
to small value as possible, because of this reason bonding wires should be used as short as
possible and usage of long wires should be avoided for SSN reduction and better
functionality of the circuits [2].
Let see another view of switching noise is as follows:
When sharp charging or discharging currents flow through the bond wires of power
lines (VDD/VSS), voltage drops in the bond wires are occurred, large switching noise at
power lines will happen in several simultaneous switches [2].
SSN reduction can be done as shown in Figure 1.3 by increasing the number of pins
that cause at least linearity of SSN [2].
Figure 1.3. Multiple pins and pads
One of the effective ways for SSN reduction is using decoupling capacitors for
decoupling different parts of especially digital circuit. The main purpose of these helpful
capacitors is to reduce the effect of noise. Figure 1.4 shows these decoupling capacitors.
“On-chip decoupling capacitors cause less current spikes from going through inductors of
power lines” [2]. One of the powerful solution for reducing noise, or it is better to say SSN
reduction is using decoupling capacitors in the circuit.
These on chip decoupling capacitors should be large enough to be satisfactory. It is
also good to know that off-chip decoupling capacitors are helpful in SSN reduction like onchip decoupling capacitors. The placement of decoupling capacitors is also more crucial than
its usage in the circuit. They should be placed close to the noise sources, because in these
12 critical places decoupling capacitors could be more helpful and more effective [2]. Another
design factor for the designers to get better result in SSN reduction is to limit the SSN to the
specific value. The value of SSN should be less than the threshold voltage for the trustworthy
operation [2].
Figure 1.4. Effect of decoupling capacitor in noise reduction
The device ground is linked to the ground of the system and between them there are series of
inductors, consist of bond wire, trace and pin which is shown in Figure 1.5 [3].
Leff=L bond wire+L trace+L pin
And the voltage drop should be as follows:
V=Leff di/dt 13 Figure 1.5. Parasitic inductances Ground and VDD noise are very critical in terms of noise, but circuits usually tend to
have more noise margin near the high level 1 than near the low level 0 and because of this in
most cases ground bounce (VSS bounce) is more crucial to study and also is considered more
often [3].
Another effective technique that is used for reducing SSN is split power plane as seen
in Figure 1.6, and by best via positioning, better functionality in terms of noise can be gained
[4].
14 Figure 1.6. Split power plane as SSN reduction technique 5. Reduction of SSN by applying different clock shapes The main technique for reducing SSN that will be explained in this thesis is using
different clock shapes. As it is discussed before, the switching activity of the main clock in
digital circuit can cause the power lines noise, so by optimizing the shape of the clock,
suppression in simultaneous switching noise will be obtained, but on the other hand finding
an appropriate clock shape could be very complicated task and should take so much time to
find optimized system clock.
There are two approaches in changing the shape of the clock:
As mentioned earlier in this chapter, fast switching can cause more simultaneous
switching noise. It is better to say that, smoother edges of the clock may decrease the effect
of noise. In other words, increasing the rising/falling times of an ideal square shape clock
makes the clock edges smoother and as a result of this change in clock shaping, less noise
generation in power lines will be happened. Having the smoother edges of the clock will
improve the functionality of the digital circuit by decreasing the noise component in power
lines.
Second approach is to use the sinusoidal clock shape. It is obvious that by using
15 sinusoidal clock, the amount of simultaneous switching noise in power lines will be
suppressed [7]. An ideal multi segment clock and harmonic suppression clock which are
shown in figures Figure 1.7 Figure 1.8 respectively are other examples of the two approaches
which mentioned as SSN reduction technique in this chapter that will be explained in the
following chapters with more details [6], [8]. In the first technique smoothing the edges of the
clock by increasing the rise and fall times of the clock will play an important role in amount
of noise which is injected into the VDD and VSS lines. First clock shape is the mixture of
triangular shape and rectangular shape (different rise and fall times), latter figures would be
the mixture of rectangular shape and sinusoidal and both clock shapes for sure can suppress
the noise in power lines.
Figure 1.7. An ideal multi-­‐segment clock shape
Figure 1.8. Harmonic suppression clock 16 6. Modeling of SSN The main target of the PDN (Power Delivery Network) design is to model the
simultaneous switching noise in the greatest way. Power delivery network will illustrate the
simultaneous switching noise in the power lines. Many studies on power delivery modeling
in system level have been done; however an accurate and resourceful high-frequency system
SSN simulation methodology has not been reported because of complexity of the system
power distribution and difficulty to make precise high-frequency models together with buffer,
package, board and connection [5].
The most reliable and safe model should be get from the fixed layout of the circuit
and the model that is used in this thesis for investigating SSN as shown in Figure 1.9 consists
of:
Capacitor, inductor and resistor in the simplest way
Figure 1.9. Simplest PDN network And as it is seen it is almost the simplest model of power delivery network. There are so
many arrangement methods of power delivery network like lumped model. Finding the exact
PDN network of the circuit is not possible without looking at the layout of the circuit is such
a complicated task, finding the model that is as close as possible to the actual model would be
what the designer try to get. By having the model that is near to the real model the result of
the circuit would be more reliable.
17 The role of modeling is very important, by changing a little bit of power delivery
network the deviation from the actual values will happen, because the elements of the circuit
that shows the SSN noise are nothing than the simple power delivery network elements.
By developing a more accurate SSN model, the ability to find the better design
methods for understanding more about SSN and also find the ways to decrease this unwanted
noise will be grown, and the circuit functionality will be achieved by decreasing
simultaneous switching noise.
7. Analyzing of SSN Knowing the concept of SSN and its modeling in a suitable way is very important but
the most important part in studying the simultaneous switching noise is measuring it or in
other words knowing the analysis method of noise.
The best way to analyze the frequency component is FFT (Fast Fourier Transform)
but as it is clear the FFT is an averaging algorithm, so it may not be the best way to find the
impact of SSN.
A sinusoidal wave (whether peak or RMS) is a better approximation of determining
the impact of SSN. So in this thesis the peak to peak (max swing) voltage of the VDD/VSS
that is shown by an appropriate power delivery network in power lines is a goal. More swing
in power lines means more simultaneous switching noise. So SSN reduction technique is
finding ways to decrease maximum noise swing in power lines. SSN initiates from the
activity of the clock and causes the drop in power lines voltage so the main focus should be
on clocking activity especially clock shapes.
8. Summary A short review of SSN (simultaneous switching noise) were presented and studied in
this chapter. The main causes of SSN and also the role of its modeling in controlling this
power lines noise were described and studied, and it was proved that the best way to see the
effect of simultaneous switching noise is to model it in the proper way. It is clear that the
more accurate model, will give us more reliable result of noise. As mentioned in this chapter
the most accurate model is only derived from the fixed layout model of the digital circuit.
Analyzing the SSN is as important as modeling it or even more, the best way for
analyzing this kind of noise is looking at maximum swing of both VDD and VSS, another
way for analyzing it is looking at the RMS value of the voltages of the power lines. But in
this thesis the focus is on maximum noise swing in the power lines or in other words less
swing means less noise effect in power lines and the cure for noise problem of the digital
18 circuit is just finding the ways to minimize the swing as much as possible.
Also some ways of SSN reduction were studied in this chapter, like decoupling
capacitors, splitting the power planes and finally reducing the noise by focusing on clock
shapes. By increasing the rise/fall time of square shape clock or using the sinusoidal wave,
noise in power lines will be decreased. All of these assumptions with more details will be
explained and discussed in the coming chapters.
19 2.
CHAPTER 2 1. Mathematical background Ground and VDD bounce is an important part of noise in nowadays digital circuit but in
the past there was not this much need to concern about SSN because of slow edge rates that
were used in the past. Any designer working with high edge rate devices must know the
features of this noise in another word he /she should be able to optimize it.
This chapter will discuss some mathematical background that are related to the clock
shapes and it is also necessary to know these mathematical background before starting to
analyze the effect of different clock shapes on the simultaneous switching noise. Through this
chapter I am going to compare the noise of different clock shapes mathematically before
relying on the simulation results of those clock shapes.
Maximum swing of the power lines voltage is the key to calculate the noise of power
lines that is cause by the switching activity of the clock.
The frequency is used in this thesis is 1GHZ in 65nm technology and the simplest
mathematical background of two main clock shapes; square shape with different rise/fall
times and an ideal sinusoidal shape will be studied
2. Slope effect on noise As explained in many different ways, the main source of simultaneous switching
noise is switching of the circuit clock. There are so many clock shapes which can be used to
run the circuit and each of these clock schemes can produce different values of maximum
noise swing in power lines that is known as simultaneous switching noise.
3. Rise/Fall time The main concept which is studied through this chapter is comparing the effect of
20 different rise/fall time of an ideal square shape on the simultaneous switching noise by
mathematical function.
The simplest way for modeling simultaneous switching noise is modeling it by at least
one simple inductor as in Figure 2.1.
Vdd
L
Circuit
L
Figure 2.1. Simple inductor
The voltage drop that is known as SSN will be determined by: ! ∗ (!" !"))
An ideal square shape and an ideal sinusoidal shape will be studied through this thesis
in general form and one specific example for each of them will be discussed in details in the
next chapter.
Figure 2.2 shows three different square clock shapes. Their difference derives from
changing the rise/fall time. It is clear from the figures that by increasing the rise and fall
times the edges start to enter into their smooth or relaxed mode.
21 2 1 0 0 5 10 15 20 25 0 5 10 15 20 25 20 25 2 1 0 1.5 1 0.5 0 0 5 10 15 Figure 2.2. Square shape clocks with different rise/fall times
If we assume that the slope of the current in one of these clocks is K, the value for SSN noise
(! ∗ (!" !" )) is as follow:
! = ! ∗ ! (3-­‐1)
Another clock shape which is used for noise reduction is sinusoidal clock shape is shown
in figure 2.3.
1.5 1 0.5 0 -­‐0.5 0 1 2 3 4 5 6 7 -­‐1 -­‐1.5 Figure 2.3. Sinusoidal shape clock
22 If we assume A as the peak value for the current of sinusoidal clock, we can find the
noise as follow:
! = ! ∗ !"#$%
(V=! ∗ (!" !" ))=> ! = ! ∗ ! ∗ ! ∗ !"#$% => (in maximum case) !"#$% = 1 so, ! =!∗!∗!
The clock frequency which is used in this thesis is 1GHZ with 65 nm technology and
as a result maximum swing of the voltage should be 1.1 which starts from 0 and reach to 1.1.
As calculated in the previous paragraph, the noise for sinusoidal clock shape and for an ideal
clock shape with different rise and fall times is ! = ! ∗ ! ∗ ! and (! ∗ ! ) respectively. The assumption starts with (! ∗ ! ) > (! ∗ ! ∗ ! ) that we assume the noise for square
shape is more than an ideal sinusoidal shape.
! > ! ∗ ! =>
!.!!!
!",!
> 1.1 ∗ 2 ∗ !" ∗ 1! (3-2)
!", ! < 160!"#$ . In other words for !", ! > 160!"#$ the square shape will have almost
better result in SSN noise means less (! ∗ (!" !")).
By increasing the rise/fall time of an ideal square shape, based on ! = (1.1-0) /!", !
circuit clock has less steep or in other words relaxed edges.
Sinusoidal clock shape also can increase the functionality of the circuit by decreasing
the SSN noise in compare with square shape with lower rise and fall time and in small rise
and fall times the sinusoidal clock shape can be used instead of square shape in terms of
simultaneous switching noise.
4. Different clock shapes 1. Multi-­‐segment clock Another clock shape is used in this thesis for noise reduction in VDD and VSS (power
lines) is multi-segment digital clock as an example of an ideal square clock shape with
different rise/fall time. Effect of this clock shape in electromagnetic interfere was studied [6].
Figure 2.4 and Figure 2.5 show two-segment digital clock that has two different rise
times and two different fall times in ideal and non-ideal forms respectively. In an ideal form
of the multi-segment clock shape, it could be seen from the figure that rise and fall times in
its sharp edges are very small almost zero and the equation (2.1) can be used for
implementing this shape of clock
23 0.5 +
!
!
0<!≤
!
!
f(t)=
(3-3)
!
│!│
for large !
Figure 2.4. An ideal two-­‐segment clock shape ’
24 Figure 2.5. Non ideal two-­‐segment clock shape
Let explain more about the effect of edges of the system clock. It is clear from the
mathematical background which was explained in the beginning of this chapter, higher value
of rise and fall times has excellent effect on reducing noise in VDD and VSS lines. There is a
direct relation between rise / fall time and performance of the circuit in terms of noise. By
having relaxed edges in the circuit clock we would definitely have less noise swing in the
power lines that is known as noise which is initiated from simultaneous activity of the clock.
2. Harmonic suppressed clock Next clock scheme which is used as digital clock is harmonic suppressed clock that is
shown in Figure 2.7 [8]. This shape of system clock would be to some extent the mixture of
sinusoidal clock and multi-segment clock both together which is shown in Figure 2.6 as a
pure harmonic suppressed clock. This clock shape is generated by three transistors will be
expressed through details in the next chapter. The equation (2.2) that is used for
implementing this clock scheme by three transistors would be like below:
!!!
f(t)=
!!!
0
!
n2Π<│t│<n2Π+Π/3
Π/2 - Π/6+ nΠ<│t│<Π/2 +Π/6+ nΠ
(3-4)
2Π/3 + n2Π<│t│< n2Π+ Π/2
25 Figure 2.6. Pure harmonic suppressed clock
¤
¤
Figure 2.7. Harmonic suppressed clock
The simulation results which will be presented in the chapter (4) will show that the
power lines simultaneous switching noise will be decreased by using harmonic suppressed
clock as the system clock more than sinusoidal clock or an ideal square shape clock lines.
5. Power consumption in clocking network One of the important concepts in functionality of the circuit which is worth to take so
much focus on is power consumption of the clocking network. Several studies for designing
the network with less power consumption have been done by clock network designers. There
would always be short circuit power in digital circuit and all the designers main effort should
be around decreasing this unwanted power consumption in clocking network. The variation
of the short circuit power is mainly caused by applying different types of clock network as
the system clock [6].
Short circuit power for an inverter clocked by square shape waveform has been
26 formulated by [8].
!!" =
!
!"
(!!! − 2!! )! .
!!
!
(3-6)
where Psc is the short circuit power dissipation, α is the gain factor of a MOS transistor and it
is assumed to be identical for NMOS and PMOS, tr is the rise (fall) time of the clock, T is the
period of the clock, Vdd is the power supply, and Vt is the threshold voltage for the transistor
and here it is assumed to be identical for NMOS and PMOS transistors [7].
So far we have discussed the ideal two segments clock signal. The practical multi
segment clock signal has finite rise/fall time. The comparison between short circuit power
consumption of multi-segment clock and conventional clock (non-ideal square shape) is
calculated by equation 2.3.
!!",!"#!
!!",!"#$
!
=!! −
!
!! !!!
!!!
!!! !!! !!! !
!.!!!! !!!
(3-7)
By substituting α = 0.5 the ratio reduces to
!!",!"#!
!!",!"#$
!
= 0.5 1 + !! (3-­‐8) !
It is clear from the figure 2.5, K1>K2, so short circuit current would be decreases in compare
to the conventional clock with relaxed edges. In other words sharper K1 would generate less
amount of short circuit power. However sharper edges would generate more noise in the
power lines [8].
2.3 Summary
Any scientific work needs to have powerful mathematical or theoretical background
that would be necessary to understand the whole work without going through it by details
especially for circuit designers whose working is designing the circuit and estimating the
value of the circuit elements, this chapter introduce some theoretical background and
knowing them before starting the implementation, helps to have better understanding of the
content. Multi-segment clock, harmonic suppressed clock, square shape clock with different
rise/fall time and sinusoidal clock were studied through this chapter and some mathematical
background was presented. The comparison between the effects of these different clock
shapes on simultaneous switching noise was declared and the conventional clock and multisegment clock were compared with each other in terms of SSN generation and short circuit
power consumption in loads connected to them [6].
In this chapter, the powerful effect of relaxed edges and less steep in rising and falling
edges of the system clock on SSN was studied. This powerful effect can compensate the
weak point of the system clock which is called simultaneous switching noise. Several
approaches were presented during this chapter that overcome noise effect in power lines. The
27 multi-segment clock and harmonic suppressed were observed, which can be used as cure for
noise problem and can be named SSN reduction techniques. According to the theoretical
information which is presented in this chapter the best way for SSN reduction is optimizing
the shape of the clock. Although increasing rise and fall time will produce better performance
of the circuit in terms of noise, triangular clock shape would not that much suitable for digital
circuits which work in high speed and high frequencies, so finding other types of clock which
are acceptable in high frequencies and also reduce noise in power lines would be all the
major hidden spot of today’s high speed circuit designers.
Multi-segment clock and harmonic suppressed clock are two types of clock that can be
mentioned during this thesis as effective SSN reduction techniques. Performance of the
circuit consists of several parameters. Two of the most important factors which can play an
important role in performance of the circuits are noise in power lines and short circuit power.
The circuit should be designed such that both noise generation and power consumption are
minimized but designing an optimized circuit clock which consume as less as possible power
and also produce less noise in power lines would be such a complicated and time consuming
task for the designers.
28 3.
Chapter 3 1. Implementation In this chapter the implemented circuit will be investigated. The investigated parts are
conventional clock, multi-segment clock shape and harmonic suppression clock. First of all
the brief introduction of each of these clock schemes will be reviewed and then the operation
of the some main elements of these circuit which were implemented through previous works
[6], [8] will be presented and finally, the comparison between them and advantages and
disadvantages of these clock usage will be defined through this.
After mathematical analysis of each shape of the clock that gives us general information
about that specific clock shape, going through details of implementation of each clock would
be definitely a proper approach for understanding of the performance of that clock and its
effect on noise and other intrinsic features of the circuit.
Clock distribution network design actually is a challenging task for high speed circuit
designers and should be one of the main responsibilities of the circuit designers before
designing the other parts of the circuit because it may be much difficult to design an
appropriate clock after designing the whole circuit, so clever designers put so much effort on
designing clock network before starting the design of other parts because the clock acts as the
feeder of the whole circuit.
1. Conventional Rectangular Clocking In the previous chapter, an ideal rectangular shaped clock was reviewed with sharp edges
that make the clock as ideal as possible. In reality, the shape of a conventional clock is not
ideal rectangular shape so for having a practical clock or in other words more real shape of
the clock that the circuit need, the conventional clock which is shown in Figure 3.1 is
utilized.
One way of generating a real square shape clock is using chain of inverters, as shown
29 in 3.1. This chain of inverters which form the main body of conventional clock should be
designed such that the output of the last stage of the inverters in the chain generates, an
acceptable rise/fall times that make the circuit be ready to work [9].
Figure 3.1. Conventional buffer-­‐driven clocking
Conventional clock shape has been studied well in literature [9] and it is good to
mention that there are many ways for designing this shape of clock. Conventional clock
shape is one of the simplest clock shapes and all the methods of designing it, is almost easy to
implement and also easy to be understood. In this thesis chain of inverters would be preferred
for making the conventional clock.
As mentioned in the previous paragraph, the design of inverters in forming the
conventional clock is a simple model of the network but the distribution of the clock as a
clock network would not be that much simple and maybe consists of so many buffers like in
H-tree network [6].
For the simple conventional clock with cascaded inverters simplicity of the clock in one
hand and consuming more power as major part of the circuit performance on the other hand
is definitely make us more aware of the trade off in this shape of clock
There are many ways for designing the conventional clock shape signal, the purpose of
all of them is optimization of some of the features like power consumption, silicon area, skew
and keep them in their acceptable ranges [9].
30 2. Proposed Clocking Networks Like the conventional clock network that should be designed by the designer before
designing the whole circuit, multi-segment clock and harmonic suppression clock which will
be explained in this section should be designed before designing the whole circuit and the
need of pre-designing the clock would be as crucial as the designing the whole circuit or even
more.
1. Multi-­‐Segment Clocking Network Generating a multi-segment clock [6] shape was introduced briefly by just some
mathematical function in chapter 2. But in this chapter the implementation of multi-segment
clock network will be discussed in more details.
For better understanding of the clock network and generating the specific wave form,
not only the mathematical or theoretical background is needed but also more specific
knowledge about the implementation and details of the clock performance would be
necessary to be realized and investigated.
Some considerations that should be taken into account during the implementation of
a multi segment clock network that is shown in the Figure 3.2 are symmetrical wave and the
trigger point which is set to half of the supply voltage (A/2) [6].
Figure 3.2. An ideal multi-­‐segment clock
Figure 3.3 shows a possible implementation of a clock generator which produces a
multi-segment clock. Each of the elements plays specific role in the circuit and by the help of
all them, the circuit can work in a proper way and also generate the wave which is resemble
to the Figure 3.2.
31 Figure 3.3. Architecture of the multi segment clocking network [6]
It is valuable to explain the operation of the circuit in the simplest words. In this circuit
there is a main buffer which is linked to the load and also some auxiliary buffers. These
buffers role is to switch the edges of the clock. When these buffers are on or off they can
make the edges of the clock sharp or smooth respectively. In this circuit, the buffers are
controlled by the extracted signals which come from a sinusoidal input. Another point that is
good to be mentioned in this section is that, these auxiliary buffers are almost fully on or off
[6].
Let us explain more about the main purpose of using auxiliary buffers. Auxiliary
buffers can form two-segment clock wave by the help of decision circuit. As shown in Figure
3.3, auxiliary buffers come along with a block which is named Decision circuit and as it is
clear from its name, this block decides either auxiliary buffer will be in the circuit as one of
the circuit elements or not [6]. Figure 3.4 shows what is inside the decision circuit and
auxiliary buffers. Auxiliary buffers are not simple buffers, because the gates of PMOS and
NMOS transistors are not connected. In this case, these extra buffers are not always included
in the circuit architecture or it is better to say, they are not always on. When these buffers are
on, they inject more power to the main buffer to make it more powerful for charging and
32 discharging and cause fast charge and discharge or in other words, help the main buffer in
fast charging and discharging processes. As seen in Figure 3.4 the decision circuit decides by
its transmission gates when it is the time for the auxiliary buffers to be on to make fast
switches or to be off to make slow switches in charge and discharge modes [6].
Figure 3.4. Implementation of two-­‐segment clock network
2.
Harmonic suppressed Clocking Network
Another shape of clock which is introduced to be used as simultaneous switching
noise reduction technique in this thesis is harmonic suppressed clock that is the reformed
version of RF outphasing amplifier using a class-D stage with harmonic suppression which
reduces the 3rd and 5th harmonic [8]. We have reused that circuit from RF application into
digital application. It is an acceptable alternative as an appropriate system clock for reducing
noise in power lines.
Some general and mathematical information about the clock waveform was introduced
briefly in chapter (2). In this chapter, we discuss the details by introducing the internal parts
33 of the circuit and the function of its main elements to understand which electrical elements
could be play roles for generating this clock shape and what inside the circuit is.
Figure 3.5 shows the drain voltage of both PMOS and NMOS transistors which are
named TA and TB, respectively as it is shown in Figure 3.6. The way can be used for
reducing noise is to generate the voltage of the drain of both transistors as shown in Figure
3.8 and the need for an extra transistor would be inevitable for this specific generation. This
additional transistor (Tc) which comes along with capacitor Cc can serve our purpose for
having the wave like Figure 3.8 and the whole circuit which is responsible for this generation,
consists of three necessary and inevitable transistors as seen in Figure 3.7 [8].
Figure 3.5. Drain voltage Figure 3.6. Inverter as a main part of the harmonic suppressed clock
34 .
Figure 3.8. Harmonic suppression wave of drain voltage
Figure 3.7. Circuit with extra transistor for generating harmonic suppression wave
These three transistors should be driven separately. input signal is named Vdrv and it
is different for three transistors and it is shown in shown in Figure 3.9 and the final
waveform which is suppressed the harmonic and noise will be derived by the circuit which is
shown in Figure 3.10. The working process of the circuit is as follows: the output stage is
nothing than the drain connection of three transistors which are named TA, TB, TC
respectively, that would be pull up to VDD through TA or pull down to ground through TB
and the TC will starts working when both TA and TB is in relaxed mode means none of them
drives the drain node. In this step TC connects its capacitor to the drain node and the period
of being turned on for TC will be twice per cycle [8]. The role of the elements which are
inside the circuit is going to be explained briefly in the following paragraph.
35 Figure 3.9. Driven signals for harmonic suppression clock network Figure 3.10. Whole circuit with buffers for driving the circuit
by pulling up the drain node to VDD by TA, the capacitance of the drain should be
charged. But in the off mode of the transistor TA, two situations would be happened. First
assumption is that the transistor TC is off, then that Cd capacitance should be discharged
through the resistance RL (load). Another assumption is like that the transistor TC is on, in
this case there will be charge distribution between the capacitance (Cc) that comes along with
the on transistor TC and capacitance of the drain Cd. Another assumption happens when
transistor B pull down the drain to ground and two situations would be happened, first
situation is when transistor TC is off and second is when transistor TC is on. In the latter
situation again distribution of charge between capacitances will be happened. This
capacitance of the transistor Cc is charge and discharge alternately or in other words the role
36 of this capacitance is to make the step in the drain voltage in half of the VDD or in almost
(VDD/2) and the average current through TC becomes zero as VC is fixed to the value of
VDD/2. Large capacitor Cc>>Cd must be used to make the VC stable during the charge and
discharge periods of the drain capacitance [8], by increasing the frequency of the clock and
changing the size of the transistor this step shaped voltage would be change to sinusoidal step
shaped and can be used for noise reduction process. The simulation results which confirm the
idea of noise reduction will be explained in the next chapter.
3. Summary
In this chapter, different clock shapes were explained through details and the
implementation of each circuit of these clocks that were conventional clock, multi-segment
clock and harmonic suppressed clock was reviewed. The main purpose of using these clock
shapes instead of conventional clock as the clock of the whole system would be reducing the
noise of the power lines which is initiated from switching activity of. In other words, using
two or more rise and fall times or harmonic suppressed clock will give us this ability to have
better performance of the circuit in terms of simultaneous switching noise. The idea of
improving noise by applying different clock shapes will be proved by results which are
derived from real simulation through the next chapter.
37 4.
Chapter 4 1.
Simulation and Results The main focus of this chapter is to investigate the main points of the results which
were derived by circuit simulations. The technology that is used for simulation is CMOS 65
nm ST technology and the frequency in which all the simulations are done, is 1GHZ. The
trigger point is almost 50% of the supply voltage in this technology. Conventional clock,
multi-segment clock and harmonic suppression clock which were studied in the previous
chapter are going to enter to the comparison section by simulation in this chapter.
Furthermore, a comparison between simulation results and mathematical analysis (presented
in chapter 2) is presented in this chapter.
The load of the clock network in this thesis is 144 D-Flip-Flopes (DFF). The
arrangement of the 144 DFF is something like parrarell arrangement which is shown in
Figure 4.1 and each of the 144 DFF is connected to the clock of the circuit in the direct way.
All of them connected to the same input and as all of the DFFs are the same, just one of their
outputs can be used as the output of the circuit to see the proper functionality [6].
Figure 4.1. Arrangment of 144 DFF as the load
2.
Comparison between square shape clock and sinusoidal shape clock First comparison that is shown in this section is comparison between different rise and
38 fall times of the same square shape clock to see the effect of different steeps of the square
shape clock on power lines noise and also on the power consumptions. The simulation that is
shown in the Figure 4.2 illustrate 2 different noise results by showing the swing of the power
lines voltage that derives from 2 different rise/fall time square shape clock. The result of
these simulation is illustrated in table 4.1 comes along with Figure 4.3 and Figure 4.4 and 4.5,
first two figures illustrate the simulation result in noise in VDD and VSS respectively and the
third one is going to illustrate the power consumption. The mathematical part that was
studied in chapter 2 approved that smoothing the edges makes the functionality of the circuit
more better in terms of noise (less maximum voltage swing in the power lines) but the power
consumption that cause from short circuit power in the edges, would have little increment
that means the trade of between noise reduction and short circuit current and cause from short
circuit power in edges.
Table4.1. Effect of rise/fall time in power lines noise rise/fall time
max noise swing in max noise swing in
power(mW)
vdd(mV)
vss(mV)
20ps
359.11
346.128
0.932
60ps
269.36
255.468
0.940
100ps
253.64
242.4
0.991
120ps
244.58
235.747
1.020
160ps
234.82
236.638
1.120
180ps
233.62
235.518
1.176
39 Figure 4.2. Analyzing the SSN by applying 2 different square shape clocks 40 max swing vdd(mV) 400 350 300 250 200 150 100 50 0 20ps 60ps 100ps 120ps 160ps 180ps Figure 4.3. Effect of rise/fall times in VDD noise max swing vss(mV) 400 350 300 250 200 150 100 50 0 20ps 60ps 100ps 120ps 160ps 180ps Figure 4.4. Effect of rise/fall times in VSS noise power(mW) 1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.000 20ps 60ps 100ps 120ps 160ps 180ps Figure 4.5. Effect of rise/fall time in power consumption 41 The result of the simulation is shown in the Figure 4.6 shows the effect of sinusoidal
clock shape as a system clock on noise and the values in the table 4.2 approve that sinusoidal
shape give us this chance to have less noise than square shape.
Figure 4.5. SSN analyzing by applying sinusoidal shape clock Table4.2. SSN and power consumption analyzing by applying sinusoidal clock VDD noise
VSS noise
Power consumption
210.88
211.75
1.61
3.
Comparison between conventional clock, multi-­‐segment clock and sinusoidal clock shapes In this part we are going to compare the simulation result of three different clock shapes:
conventional clock, multi-segment clock and harmonic suppression clock which are shown in
Figures 4.7, 4.8, 4.9 respectively. Applying each of these signals as the system clock, would
definitely effect on functionality of the circuit in both noise and power consumption which
42 are the most important factors for analyzing the functionality of the circuit is illustrated in
table 4.3.
Figure 4.6. Conventional clock shape Figure 4.8. Multi-­‐segment clock shape Figure 4.9. Harmonic suppression clock 43 Table 4.3. Different clock types effect on noise and power consumption Maximum swing
VDD(mV)
clock types
maximum swing
VSS(mV)
power
consumption(mW)
conventional clock
263.7
265.06
1.048
multi segment clock
160.74
177.123
1.192
harmonic
clock
162.34
161.53
2.127
suppressed
If we focus more on the values in the above table which is derived from the
simulations of the circuit with different clock types, we can realize that multi-segment clock
and harmonic suppression clock both can overcome the problem of simultaneous switching
noise by decreasing the voltage swing in the power lines. The better illustration of clock
effects on VDD and VSS noise can be shown in figure 4.10 and figure 4.11 respectively.
maximum swing VDD(mV) 300 250 200 150 100 263.7 160.74 162.34 50 0 convenZonal mulZ clock segment clock harmonic suppressed clock Figure 4.10. VDD noise in different clock schemes
44 maximum swing VSS
(mV) 300 250 265.06 200 150 177.123 161.53 100 50 0 convenZonal mulZ segment harmonic clock clock suppressed clock Figure 4.11. VSS noise in different clock schemes
power consumpYon
(mW) 2.5 2.0 2.127 1.5 1.0 0.5 1.048 1.192 0.0 convenZonal mulZ segment clock clock harmonic suppressed clock Figure 4.12. Power consumption in different clock schemes The previous results make us sure about the idea that relaxing the edges would improve the
functionality of the circuit in terms of noise. Another fact should be well focused is power
consumption. An optimized circuit should not only be as much as noiseless but also should
consume less power. The power consumption calculated from the multiplication of VDD
current by 1.1 (VDD voltage), can be an important part of circuit functionality which is seen
in Figure 4.12.
45 There is a trade of between the power consumption and generating noise in power lines for
both multi-segment clock and harmonic suppression clock shapes. Using these clock shapes
reduce the effect of SSN or decrease the maximum noise swing in power lines but on the
other hand increase the power consumption for the load. If we want to explain this effect in
simple words we have to mention, that effect is mainly caused by short circuit current which
is more dominant in harmonic-suppression clock and multi-segment clock because of their
shapes. These clocks waves consists of more than two steps or more than one step during
their rising and falling edges respectively, changing the steep in their edges consume more
power in compare to conventional clock . Short circuit power in sharp edges would be less
than relaxed edges and by increasing the rise/fall times the short circuit power will be
increased.
4.
Summary The simulation results of using different clocks were shown in this chapter by tables,
figures and explanations with more details. Different clock shapes have different effects on
both simultaneous switching noise and power consumption. Among three clock shapes which
were studied in this chapter harmonic suppression clock and multi-segment clock shapes
have better result in terms of noise or in other words reduce the SSN noise but the power
consumption in the load will increase by using these clocks as the system clock. We have to
be careful in using these clock shapes, conventional clock could be an acceptable clock if
power consumption is our target but if reducing noise in power lines is our goal using multisegment and harmonic suppression clock would be the best option.
Optimizing the shape of the harmonic suppression clock and multi-segment clock can cause
less power consumption (short circuit power) in power lines. Finding the way to have a
circuit with less noise in power lines and also less power consumption could be the main goal
of today’s digital circuit design and should be the done by clever circuit designers.
46 5.
Refrences 1. http://www.altera.com/literature/hb/qts/qts_qii52018.pdf (29.03.2011) 2. http://www.ee.ryerson.ca/~fyuan/ssn.pdf (29.03.2011) 3. http://www.actel.com/documents/SSN_AN.pdf (29.03.2011) 4. Jongbae Park; Hyungsoo Kim; Youchul Jeong; Jingook Kim; Jun So Pak; Dong Gun Kam; Joungho Kim; , "Modeling and measurement of simultaneous switching noise coupling through signal via transition," Advanced Packaging, IEEE Transactions on , vol.29, no.3, pp.548-­‐559, Aug. 2006 5. high frequency simulatneous switching output noise simulation
6. Iman Esmaeil Zadeh, A Study and Implementation of On-Chip EMC Techniques,
Advanced Level Thesis LiTH-­‐ISY-­‐EX-­‐-­‐10/4412-­‐-­‐SE, Linköping Studies in Science and Technology, Jan. 2011.
7. Mesgarzadeh Behzad , Esmaeil Zadeh Iman, Alvandpour Atila, “A Multi-­‐Segment Clock Signal for Low-­‐EMI Clock Distribution ” , IEEE International Conference on Electronics, Circuits and Systems, ICECS, Athena, Greece. 8. Jonas Fritzin, Christer Svensson, Atila Alvandpour, "A Class-­‐D Outphasing RF Amplifier with Harmonic Suppression in 90nm CMOS", IEEE European Solid-­‐State Circuits Conference (ESSCIRC), pp. 310-­‐313, Seville, Spain, September 14-­‐16 2010. 9. A.chandrakasan, Jan M. Rabaey and B.Nikolic. Digital integrated circuit.Prentice-­‐Hall, second edition, 2003. 47