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B GB 707L 7E SD
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B GB 707L 7E SD as a B roa dba nd Lo w
Noi s e A m pl i fer fo r mo bi l e an al og TV
appl i c a ti o ns
Appl i c ati o n N ote A N 232
Revision: Rev. 1.0
2010-08-03
RF and P r otec ti on D evi c es
www.BDTIC.com/infineon
BDTIC
Edition 2010-08-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
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BGB707L7ESD
BGB707L7ESD as TV LNA
Application Note AN232
Revision History: 2010-08-03
Previous Revision: Rev. x.x (previous)
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Subjects (major changes since last revision)
BDTIC
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HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
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MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
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of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™
of Diodes Zetex Limited.
Last Trademarks Update 2009-10-19
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Application Note AN232, Rev. 1.0
3 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
List of Content, Figures and Tables
Table of Content
1
Introduction ........................................................................................................................................ 5
2
Summary of Measurement Results .................................................................................................. 6
3
Schematic Diagram ............................................................................................................................ 7
4
Measured Graphs ............................................................................................................................... 8
5
Evaluation board and layout Information ...................................................................................... 11
6
Potential Performance Enhancements .......................................................................................... 12
Appendix 1: ESD protection circuit for system level ESD robustness .......................................................... 13
Author
16
BDTIC
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Classical Three-Band Tuner ................................................................................................................ 5
Silicon Tuner ........................................................................................................................................ 5
Schematic Diagram .............................................................................................................................. 7
Gain ...................................................................................................................................................... 8
Noise Figure ......................................................................................................................................... 8
Matching ............................................................................................................................................... 9
Matching – Smith Chart ........................................................................................................................ 9
Isolation .............................................................................................................................................. 10
Picture of Evaluation Board with connector description ..................................................................... 11
PCB Layer Information ....................................................................................................................... 11
Gain vs. current consumption ............................................................................................................ 12
NF vs. current consumption ............................................................................................................... 12
ESD test pulse according to system level specification IEC61000-4-2 – Contact Discharge 15kV .. 13
Smart 2-step ESD protection approach based on external and internal ESD protection structure ... 14
Standard ESD protection topology with optional ESD resistor, blocking capacitor and a serial
inductor ............................................................................................................................................... 15
List of Tables
Table 1
Table 2
Table 3
Summary of Measurement Results ...................................................................................................... 6
Bill-of-Materials..................................................................................................................................... 7
1dB compression point and IP3 ......................................................................................................... 10
www.BDTIC.com/infineon
Application Note AN232, Rev. 1.0
4 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Introduction
1
Introduction
Over the last few years there has been a clear trend in television to move from the classical TV-set out to more
mobile platforms like notebooks, cell phones and PDAs. Especially the introduction of digital terrestrial television
in many countries and the more and more evolving hand-held television standards like DVB-H and T-DMB
support this evolution.
With television going mobile the antennas are getting smaller, resulting in a loss in antenna gain. It requires an
additional LNA with low noise figure to keep up a good reception of the TV signal, no matter if the TV tuner’s RF
frontend uses the classical three-band tuner (Figure 1) or the more space saving silicon tuner (also called
double conversion tuner or up-down converter, Figure 2). Particularly the silicon tuner has the need for and
external LNA as tuner ICs in general tend to have high noise figures and the silicon tuner approach doesn’t
implement any prestages including an RF MOSFET.
BDTIC
The application for BGB707L7ESD shown in this document was designed for use in mobile TV applications
having electrically short (telescope) antennas. The low current consumption of the LNA makes it ideal for mobile
applications while still offering a good input compression point compared to this low current. The use of short
antennas relaxes the requirements for linearity anyway.
Being located directly after the antenna an LNA needs to be protected from ESD strikes. BGB707L7ESD’s builtin ESD protection of 2kV HBM at all pins (3kV at the RF input pin) helps a lot in meeting this requirement.
In case of even higher protection levels being needed additional ESD protection using an Infineon TVS diode is
highly recommended. For more details on ESD protection please refer to Appendix 1.
VHF low 47 ... 160MHz
LNA
RF Input
VHF high 160 ... 470MHz
Tuner IC
ESD
Protection
UHF 470 ... 860MHz
RF MOSFETs
Figure 1
Classical Three-Band Tuner
SAW
GSM
Rejection
LNA
Demod
ESD
Protection
VGA
Mixer
VCO 1
Mixer
VCO 2
Si-Tuner
Figure 2
Si_Tuner.vsd
Silicon Tuner
www.BDTIC.com/infineon
Application Note AN232, Rev. 1.0
5 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Summary of Measurement Results
2
Summary of Measurement Results
All data was measured in a 50Ω system.
Table 1
Summary of Measurement Results
Vcc = Vctrl = 3.0V, at room temperature.
Parameter
Symbol
Value
Unit
Note/Test Condition
Frequency Range
Freq
47-862
MHz
DC Voltage
Vcc
3.0
V
DC Current
Icc
2.9
mA
Gain
G
12.6 – 13.7
dB
See Figure 4
Noise Figure
NF
1.3 – 1.8
dB
See Figure 5
RLin
4
dB
See Figure 6
RLout
9
dB
See Figure 6
IRev
24.5
dB
See Figure 8
IP1dB
-7.5
dBm
See Table 3
IIP3
-11
dBm
See Table 3
BDTIC
Input Return Loss
Output Return Loss
Reverse Isolation
Input 1dB compression point
rd
Input 3 order intercept point
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Application Note AN232, Rev. 1.0
6 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Schematic Diagram
3
Schematic Diagram
BDTIC
Figure 3
Table 2
Schematic Diagram
Bill-of-Materials
Value
Unit
Size
Manufacturer
Comment
C1
330
pF
0402
various
DC blocking
C2
47
nF
0402
various
RF bypass
C3
330
pF
0402
various
DC blocking
C4
47
nF
0402
various
RF bypass
C5
330
pF
0402
various
DC blocking
L1
470
nH
0603
Tayio Yuden LK1608
RF choke
R1
12
kΩ
0402
various
Current adjustment
R2
1
kΩ
0402
various
Feedback, matching
R3
180
Ω
0402
various
Stability, output matching
Q1
BGB707L7ESD
Symbol
TSLP-7-1 Infineon Technologies
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Application Note AN232, Rev. 1.0
7 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Measured Graphs
4
Measured Graphs
All data displayed here was measured in a 50Ω system. Vcc = Vctrl = 3.0V
Gain
15
DB(|S(2,1)|)
14.5
BDTIC
14
13.5
13
12.5
12
40
100
900
Frequency (MHz)
Figure 4
Gain
Noise Figure
2.2
2
NF (dB)
1.8
1.6
1.4
1.2
1
50
Figure 5
350
Frequency (MHz)
650
850
Noise Figure
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Application Note AN232, Rev. 1.0
8 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Measured Graphs
Matching
DB(|S(1,1)|)
0
DB(|S(2,2)|)
-2
-4
-6
BDTIC
-8
-10
-12
40
100
900
Frequency (MHz)
Matching
Matching in Smith Chart
0.8
S(1,1)
1.0
Figure 6
2.
0
6
0.
S(2,2)
Swp Max
870MHz
0.
4
0
3.
0
4.
5.0
0.2
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0
0.2
10.0
-10.0
2
-0.
-4
.0
-5.
0
-3
.0
Figure 7
.0
-2
-1.0
-0.8
-0
.6
.4
-0
Swp Min
40MHz
Matching – Smith Chart
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Application Note AN232, Rev. 1.0
9 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Measured Graphs
Isolation
-22
DB(|S(1,2)|)
-22.5
-23
-23.5
BDTIC
-24
-24.5
-25
40
100
900
Frequency (MHz)
Figure 8
Table 3
1
Isolation
1dB compression point and IP3
1
Frequency / MHz
Input compression point / dBm
Input IP3 / dBm
50
-7.5
-11
150
-8
-11
250
-7.5
-11
450
-7
-10.5
800
-6.5
-10.5
Test condition: -35dBm / tone, ∆f=1MHz
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Application Note AN232, Rev. 1.0
10 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Evaluation board and layout Information
5
Evaluation board and layout Information
Cadj
GND
Vctrl
Vcc
BDTIC
RFin
RFout
boardandpins.vsd
Figure 9
Picture of Evaluation Board with connector description
Note: The pin “Cadj” may be used to adjust the IC’s current quickly by connecting an external resistor decade.
Prior to doing this R1 has to be removed. If the board is intended to be used as received, please leave this
pin open.
Figure 10
PCB Layer Information
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Application Note AN232, Rev. 1.0
11 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Potential Performance Enhancements
6
Potential Performance Enhancements
It is possible to increase gain and to reduce noise figure by increasing the current consumption of the IC.
The data displayed here was acquired using a noise figure meter. This is the reason why the gain curves are
not as smooth as they would have been when using a network analyzer.
BDTIC
Figure 11
Gain vs. current consumption
Figure 12
NF vs. current consumption
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Application Note AN232, Rev. 1.0
12 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Potential Performance Enhancements
Appendix 1: ESD protection circuit for system level ESD robustness
Introduction
With the advancement in miniaturization of semiconductor structures, ESD handling capability of the devices is
becoming a concern. Increasing ESD handling capability of the I/O ports costs additional chip size and affects
the I/O capacitance significantly. This is very important for high frequency devices, especially when high linearity
is required. Therefore, tailored and cost effective ESD protection devices can be used to build up an ESD
protection circuit. To handle ESD events during assembly, devices normally have on-chip ESD protection
according to the device level standards e.g. “Human Body Model” JEDEC 22-A-115. To fulfill the much more
stringent system level ESD requirements according to IEC61000-4-2 as shown in Figure 13, the external ESD
protection circuit has to handle the majority of the ESD strike. The best external ESD protection is achieved
using a TVS diode assisted by additional passive components.
BDTIC
m6
ESD_current, A
60
Reference Pulse
15kV contact discharge
according IEC61000-4-2
40
m6
time=1.507nsec
ESD_current=57.68 A
m7
time=30.01nsec
ESD_current=29.43 A
m7
m8
20
m8
time=60.01nsec
ESD_current=15.18 A
0
0
20
40
60
80
100
120
140
160
180
200
time, nsec
Figure 13
ESD test pulse according to system level specification IEC61000-4-2 – Contact Discharge
15kV
Some examples of RF applications addressed by the Infineon ESD protection proposal are given below:
• FM Radio (76 MHz -110 MHz)
• WLAN 802.11b/g/n (2.4 GHz, Tx ~ +20 dBm)
• Bluetooth (2.4 GHz, Tx ~ +20 dBm)
• Automatic Meter Reading, AMR (900 MHz, TX ~ +20 dBm)
• Remote Keyless Entry, RKE (315 MHz - 434 MHz - 868 MHz - 915 MHz, Tx~13 dBm)
• GPS (1575 MHz, Rx only but can be affected by RF interferer)
For an ESD protection device tailored for medium power RF signals (=< +20 dBm), following requirements are
essential:
1. RF requirements
a) Bidirectional characteristic to handle DC free signals without clipping / signal distortion
b) A highly symmetrical behavior of the ESD device for positive and negative voltage swings is mandatory to
keep the power level of even Harmonics low
c) Breakdown voltage of 5 V-10V, to avoid signal distortion at high RF voltage swing applied at the TVS
diode, located close to the antenna
d) High linearity
e) Low leakage current and stable diode capacitance vs. RF voltage swing
f) Ultra low diode capacitance is mandatory
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Application Note AN232, Rev. 1.0
13 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Potential Performance Enhancements
2. ESD requirements
a) Lowest dynamic resistance Rdyn to offer best protection for the RFIC; Rdyn is characterized by
Transmission Line Pulse (TLP) measurement
b) Very fast switch-on time (<<1nsec) to ground the initial peak of an ESD strike according to IEC61000-4-2
c) No performance degradation over a large number of ESD zaps (>1000)
Two-step ESD Protection approach
General structure for a 2-step ESD approach according to Figure 14 enables to split the entire ESD current
between the internal and external ESD protection device. The external device is much more robust and handles
the majority of the ESD current. To avoid any impact on the RF behavior of the system and to minimize non
linearity effects, the TVS diode should possess an ultra low device capacitance.
Therefore the bi-directional (symmetrical) Infineon TVS Diode ESD0P2RF is well suited, which provides a diode
capacitance as low as 0.2 pF and a Rdyn of only 1 Ohm. ESD robustness can be improved one step more by
adding a small serial resistor between the external TVS diode and the RF amplifier input. A resistor of ~2.2 Ohm
is a good compromise between additional ESD performance and insertion loss. The TVS diode ESD0P2RF in
combination with the 2.2 Ohm ESD resistor would incur less than 0.23dB insertion loss up to 3 GHz.
BDTIC
Figure 14
Smart 2-step ESD protection approach based on external and internal ESD protection
structure
For further ESD improvement it is highly recommend to add a serial capacitor (C1). The capacitor cuts off most
of the high energy created by the ESD strike. For better ESD robustness, C1 should be as small as possible,
but has to match to the intended application frequency as well. For a broadband ESD protection
(80MHz…3GHz) C1 should be about 100pF…150pF. Optional matching can be implemented with a serial
inductor L1 for a dedicated frequency. In combination with L1, C1 can be reduced significantly which improves
the ESD performance.
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Application Note AN232, Rev. 1.0
14 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Potential Performance Enhancements
BDTIC
Figure 15
Standard ESD protection topology with optional ESD resistor, blocking capacitor and a
serial inductor
www.BDTIC.com/infineon
Application Note AN232, Rev. 1.0
15 / 17
2010-08-03
BGB707L7ESD
BGB707L7ESD as TV LNA
Author
Author
Dietmar Stolz, Staff Engineer of Business Unit “RF and Protection Devices”
BDTIC
www.BDTIC.com/infineon
Application Note AN232, Rev. 1.0
16 / 17
2010-08-03
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AN232