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SFX-424G Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Applications SONET / SDH / ATM DWDM / FDM FEC (Forward Error Correction) Features • • • • • • • • Bulletin Revision Date SG124 03 10 May 2011 3.3V High Precision PLL Jitter Generation OC-192 Compliant Surface Mount Accepts up to 4 Inputs from an External MUX Inputs Compatible with CMOS/LVDS/LVPECL Frequency Translation up to 800 MHz Alarm detection for Loss of Lock/ Loss of Reference condition ROHS Compliant General Description The SFX-424G is a high precision frequency translator that translates up to four inputs from 8 kHz to 100MHz, to output frequencies between 8 MHz and 800 MHz. The SFX-424G supports all major FEC rates such as 15/14, 255/237 etc. SFX-424G is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SFX-424G provides a jitter filtered, wander following output signal synchronized to a superior Stratum or peer input reference signal. Table 1 Absolute Maximum Rating Symbol Parameter Vcc VI Ts Power Supply Voltage (OptionD) Input Voltage Storage Temperature (OptionF) Storage Temperature (OptionA) Parameter fIN Input Frequencies fOUT Output Frequencies (LVPECL)19.44 M Output Frequencies (LVCMOS) Vcc Supply Voltage (3.3 VDC) ICC Supply Current - LVCMOS INPUT VIH VIL LVPECL INPUT VIH VIL LVCMOS OUTPUT (Option A) LVPECL OUTPUT (Option F) VOH VOL TR/TF Rise/Fall Time @20% to 80% SYM Output Symmetry JGEN1 Jitter Generation RMS (12 kHz - 20 MHz) JGEN2 Jitter Generation RMS (12 kHz - 20 MHz) JTRAN Jitter Transfer APR Input Frequency Tracking TOP Operating Temperature F = C = SSB Phase Noise (for SFX-424G-DFF-A10Z only) at 10Hz offset at 100Hz offset at 1kHz offset at 10kHz offset at 100kHz offset at 1MHz offset at 10MHz offset 0/ OFF Phase Offset NOTES: 1.0 155.52 MHz 2.0 156.25 MHz Minimum Nominal Maximum Units Notes -0.3 -0.2 -55 -40 - - - - 4.0 Vcc +0.3V 125 85 Volts Volts °C °C Minimum Nominal Maximum Units Notes 8 k - 8 M 3.13 60 - 800 M - 3.3 - 100 M Hz 130 M 3.46 mA 2 -0.3 - - VCC 0.8 Volts Volts 1.49 0.86 - - TYP. LVCMOS 2.72 2.125 Volts Volts 2.275 - - 45 - - - 0.6 0.35 1.68 1.5 55 - V V ns % ps 1.0 - 0.50 - ps 2.0 - ±40 -40 0 - - - - - - - - - - - - -57 -92 -120 -138 -150 -157 -160 5 0.1 85 70 -45 -80 -110 -135 -145 -147 -150 15 dB ppm °C °C dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ns 3.0 Specifications Table 2 Symbol The SFX-424G includes a lock detect alarm output. The PLL control voltage is brought out through a 470 kΩ resistor and can be used to determine when the pull range limits are reached. The LVPECL outputs may be put into the tri-state high impedance condition for external testing purposes by asserting a high signal to the Enable/Disable pin. Parts are assembled using high temperature solder to withstand surface mount reflow process. This product is compliant with all required ROHS specifications. Hz Hz Volts 4.0 3.0 GR-253-CORE, Sec. 5.6.2.1.2 4.0 For other models and frequencies, consult factory. Data Sheet #: SG124_SFX-424G Page 2 Rev: 03 Date: 05/10/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Functional Block Diagram Figure 1 LD (Pin 10) 470 kΩ VMON (Pin 5) FIN (Pin 13) Frequency Loop Divider Filter 0.01 µF OSC FOUT (Pin 8) CFOut (Pin 9) Frequency 10 kΩ SEL0 (Pin 1) Divider Microprocessor SEL1 (Pin 2) 10 kΩ OD (Pin 6) Pin Description Table 3 PIN #SYMBOL 1 SEL0 2 3 4 5 6 7 8 9 10 11 12 13 14 SEL1 GND VMON OD GND FOUT CFOUT LD GND GND FIN VCC I/O I Level LVTTL Function Input Frequency Select .* 10kΩ Pull down resistor I GND O I GND O O O GND GND I VCC LVTTL Supply Analog LVCMOS Supply LVPECL or LVCMOS LVPECL or GND LVCMOS Supply Supply LVPECL or LVCMOS Supply Input Frequency Select .* 10kΩ Pull down resistor Ground Missing VCXO Control VoltageUnder locked conditions VMON should be > 0.3V and <3.0V. The Input Frequency may be out of range if the voltage is outside of this voltage range. Output Disable Disable = Logic 1 Enable = Logic 0 or No Connect Ground Frequency Output Complementary Frequency Output Note: For the LVCMOS Option, this connection is tied to GND Lock Detect Locked = Logic 1 Loss of Signal = Logic 0 Ground Ground Input FrequencyNote: Input is AC coupled for handling either LVCMOS or LVPECL input signals Power Supply Voltage (3.3V ±5%) Data Sheet #: SG124_SFX-424G Page 3 Rev: 03 Date: 05/10/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Output Load and Power Supply Filtering Recommendations Figure 2 * It is highly recommended * that either a linear regulator or bypass capacitors be used. Typical values would be 10 uF, 0.1 uF, 100 pF. * * Only Required for Option F VCC -2 VDC LD (Pin 10) 470 kΩ (Pin 13) REF 3 50Ω (Pin 5) FIN REF 1 REF 2 VMON Frequency Loop Divider Filter 0.01 µF 50Ω FOUT OSC (Pin 8) CFOUT (Pin 9) REF 4 Frequency SEL0 10 kΩ (Pin 1) Divider Microprocessor SEL1 (Pin 2) 10 kΩ OD (Pin 6) Package Dimensions Recommended Footprint Dimensions Figure 3 Figure 4 1.905 [0.075] mm (in) 19.81 .780 5.84 .230 .060 Sq. Typ. 13.72 .540 Bottom View R 0.51 .020 12.19 .480 CL 6.223 [0.245] 12.446 [0.490] 20.32 .800 2.54 .100 3.048 [0.120] 4.29 .169 7.620 [0.300] Data Sheet #: SG124_SFX-424G CL 15.240 [0.600] Page 4 Rev: 03 2.540 [0.100] Date: 05/10/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 5 Temperature 260°C 260°C 220°C 180°C 150°C 120°C 0 120 S Max. Time 10 S 60 S Max. 360 Sec. Max. Meets IPC/JEDEC J-STD-020C Data Sheet #: SG124_SFX-424G Page 5 Rev: 03 Date: 05/10/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Standard Frequencies 8 kHz 16 kHz 64 kHz 1.024 MHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 13.0000 MHz 16.3840 MHz 10.24 MHz 19.4400 MHz 20.4800 MHz 26.0000 MHz 27.0000 MHz C D E F H J K L M N O P R T W 38.8800 MHz 44.7360 MHz 204.80 MHz 51.84 MHz 61.44 MHz 77.76 MHz 82.944 MHz 112.00 MHz 139.2640 MHz 155.5200 MHz 166.6286 MHz 622.0800 MHz 666.5143 MHz 156.25 MHz Input Freq not listed Output Freq not listed X Y Z 0 1 2 3 4 5 6 7 8 9 A S S Ordering Information SFX-424G- X X X - X X X X Output Frequency (Options L - A) See standard frequencies chart above. * If the desired frequency is not listed, Please Consult a sales representative for availabilty of additional frequencies. Supply Voltage D = 3.3 VDC ±5% Output Logic A = LVCMOS F = Comp. LVPECL Input Frequency (Options C - 3) See standard frequencies chart above. * If the desired frequency is not listed, Please Consult a sales representative for availabilty of additional frequencies. Temperature Range C = 0˚C to 70˚C F = -40˚C to 85˚C D = 0˚C to 85˚C Input Logic A = LVCMOS F = LVPECL Number of Input Frequencies 1: 2: 3: 4: 1 2 3 4 Input Input Input Input Frequency Frequencies Frequencies Frequencies Data Sheet #: SG124_SFX-424G Page 6 Rev: 03 Date: 05/10/11 © Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Revision Revision Date Note P00 P01 P02 P03 P04 P05 00 01 02 03 6/30/06 2/6/07 3/1/07 6/7/07 1/22/08 9/19/08 12/09/08 06/17/09 04/06/11 05/10/11 Preliminary Release Added Solder Profile Added Mechanical Drawing Updated Solder Profile Updated Output Frequency Range Added Input Frequency Range to Tbl. 2 Change from Preliminary to Release Jitter Change Standard Frequency Updates & Temp Range & Solder Profile update Added phase noise example spec & edited Package Dimensions