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OPA454
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High-Voltage (100V), High-Current (50mA)
OPERATIONAL AMPLIFIERS, G = 1 Stable
FEATURES
DESCRIPTION
1
• WIDE POWER-SUPPLY RANGE:
±5V (10V) to ±50V (100V)
• HIGH OUTPUT LOAD DRIVE: IO > ±50mA
• WIDE OUTPUT VOLTAGE SWING: 1V to Rails
• INDEPENDENT OUTPUT DISABLE OR
SHUTDOWN
• WIDE TEMPERATURE RANGE: –40°C to +85°C
• SO-8 PACKAGE
2
APPLICATIONS
•
•
•
•
•
•
•
•
TEST EQUIPMENT
AVALANCHE PHOTODIODE:
High-V Current Sense
PIEZOELECTRIC CELLS
TRANSDUCER DRIVERS
SERVO DRIVERS
AUDIO AMPLIFIERS
HIGH-VOLTAGE COMPLIANCE CURRENT
SOURCES
GENERAL HIGH-VOLTAGE
REGULATORS/POWER
The OPA454 is a low-cost operational amplifier with
high voltage (100V) and relatively high current drive
(50mA). It is unity-gain stable and has a
gain-bandwidth product of 2.5MHz.
The OPA454 is internally protected against
over-temperature conditions and current overloads. It
is fully specified to perform over a wide power-supply
range of ±5V to ±50V or on a single supply of 10V to
100V. The status flag is an open-drain output that
allows it to be easily referenced to standard
low-voltage logic circuitry. This high-voltage op amp
provides excellent accuracy, wide output swing, and
is free from phase inversion problems that are often
found in similar amplifiers.
The output can be independently disabled using the
Enable/Disable Pin that has its own common return
pin to allow easy interface to low-voltage logic
circuitry. This disable is accomplished without
disturbing the input signal path, not only saving power
but also protecting the load.
Featured in a small exposed metal pad package, the
OPA454 is easy to heatsink over the extended
industrial temperature range, –40°C to +85°C.
sutatS
galF
Table 1. OPA454 RELATED PRODUCTS
+V
PRODUCT
)D/E( elbasiD/elbanE
OPA445
-NI
VO
454APO
NI+
nommoC elbasiD/elbanE
)moC D/E(
V-
(1)
(1)
DESCRIPTION
80V, 15mA
OPA452
80V, 50mA
OPA547
60V, 750mA
OPA548
60V, 3A
OPA549
60V, 9A
OPA551
60V, 200mA
OPA567
5V, 2A
OPA569
5V, 2.4A
The OPA445 is pin-compatible with the OPA454, except in
applications using the offset trim, and NC pins other than
open.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
OPA454
SO-8
DDA
OPA454
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage
VS = (V+) – (V–)
Signal Input Terminals, Voltage
(2)
OPA454
UNIT
120
V
(V–) – 0.3 to (V+) + 0.3
V
Signal Input Terminals, Current (2)
±10
mA
E/D to E/D Com Voltage
+5.5
V
Output Short-Circuit
(3)
ISC
Operating Temperature
TJ
Storage Temperature
Junction Temperature
ESD Rating:
(1)
(2)
(3)
TJ
Continuous
–55 to +125
°C
–55 to +125
°C
+150
°C
Human Body Model (HBM)
4000
V
Charged Device Model (CDM)
500
V
Machine Model (MM)
150
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should
be current limited to 10mA or less.
Short-circuit to ground.
PIN ASSIGNMENT
DDA PACKAGE
SO-8 PowerPAD
(TOP VIEW)
)nommoC elbasiD/elbanE( moC D/E
)elbasiD/elbanE8( D/E
1
)1(
DAPrewoP
-NI
7 +V
k2niS taeH
no detacoL(
NI+ )edis3mottob
6TUO
V-
(1)
2
4
galF s5utatS
PowerPAD is internally connected to V–. Soldering the PowerPAD to the printed circuit board (PCB) is always
required, even with applications that have low power dissipation.
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OPA454
www.ti.com ....................................................................................................................................... SBOS391A– DECEMBER 2007 – REVISED DECEMBER 2008
ELECTRICAL CHARACTERISTICS: VS = ±50V
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP (1) = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±0.2
±4
mV
±1.6
±10
µV/°C
25
100
µV/V
±1.4
±100
pA
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
VOS
(2)
IO = 0
dVOS/dT
vs Power Supply
PSRR
VS = ±4V to ±60V, VCM = 0V
INPUT BIAS CURRENT
Input Bias Current
IB
vs Temperature
See Typical Characteristics
Input Offset Current
IOS
±0.2
±100
pA
en
300
nV/√Hz
35
nV/√Hz
NOISE
Input Voltage Noise Density, f = 10Hz
Input Voltage Noise Density, f = 10kHz
f = 0.01Hz to 10Hz
Current Noise Density, f = 1kHz
in
15
µVPP
40
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection
VCM
CMRR
Linear Operation
(V–) + 2.5
See Note
VS = ±50V, –25V ≤ VCM ≤ +25V
100
146
(3)
(V+) – 2.5
V
dB
VS = ±50V, –45V ≤ VCM ≤ +45V
100
147
dB
Over Temperature
VS = ±50V, –25V ≤ VCM ≤ +25V
80
88
dB
Over Temperature
VS = ±50V, –45V ≤ VCM ≤ +45V
72
82
dB
Differential
1013 || 10
Ω || pF
Common-Mode
1013 || 9
Ω || pF
130
dB
112
dB
115
dB
106
dB
102
dB
84
dB
INPUT IMPEDANCE
OPEN-LOOP GAIN
Open-Loop Voltage Gain (4)
AOL
(V–) + 1V < VO < (V+) – 1V,
RL = 49kΩ, IO = ±1mA
100
(V–) + 1V < VO < (V+) – 1V,
RL = 49kΩ, IO = ±1mA
(V–) + 1V < VO < (V+) – 2V,
RL = 4.8kΩ, IO = ±10mA
100
(V–) + 1V < VO < (V+) – 2V,
RL = 4.8kΩ, IO = ±10mA
(V–) + 2V < VO < (V+) – 3V,
RL = 1880Ω, IO = ±25mA
(V–) + 2V < VO < (V+) – 3V,
RL = 1880Ω, IO = ±25mA
(1)
(2)
(3)
(4)
80
TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
See typical characteristic curve, Offset Voltage Drift Production Distribution (Figure 14).
Typical range is (V–) + 1.5V to (V+) – 1.5V.
Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE (5)
Gain-Bandwidth Product
GBW
Slew Rate
SR
Small-Signal
2.5
MHz
G = ±1, VO = 80V Step, RL = 3.27kΩ
13
V/µs
35
kHz
Full-Power Bandwidth (6)
Settling Time: ±0.1% (7)
G = ±1, VO = 20V Step
3
µs
Settling Time: ±0.01% (7)
G = ±5 or ±10, VO = 80V Step
10
µs
VS = +40.6V/–39.6V, G = ±1,
f = 1kHz, VO = 77.2VPP
0.0008
%
Total Harmonic Distortion + Noise
(8)
THD+N
OUTPUT
Voltage Output Swing From Rail (9)
VO
Continuous Current Output, dc
RL = 49kΩ, AOL ≥ 100dB, IO = 1mA
(V–) + 1
(V+) – 1
RL = 4.8kΩ, AOL ≥ 100dB, IO = 10mA
(V–) + 1
(V+) – 2
V
RL = 1880Ω, AOL ≥ 80dB, IO = 26mA
(V–) + 2
(V+) – 3
V
Depends on Circuit Conditions
Maximum Peak Current Output, Current
Limit (10)
V
See Figure 6
IO
+120/–150
mA
+140/–170
mA
200
pF
See Figure 5
Ω
Output Capacitance
18
pF
Feedthrough Capacitance (11)
150
fF
Enable → Disable
6
µs
Disable → Enable
4
µs
Over-Current Delay (13)
15
µs
10
µs
Alarm (status flag high)
+150
°C
Return to Normal Operation (status flag low)
+130
Over Temperature
Capacitive Load Drive (5)
CLOAD
Open-Loop Output Impedance
RO
Output Disabled
STATUS FLAG PIN (Referenced to E/D Com) (12)
Status Flag Delay
Over-Current Recovery Delay
Junction Temperature
(13)
TJ
Output Voltage (5)
Normal Operation
RL = 100Ω During Thermal Overdrive,
Alarm
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
4
°C
E/D Com + 2
(V+) – 2.5
V
V
See Typical Characteristic curves.
See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 12).
See the Applications Information section, Settling Time.
Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curve Total Harmonic
Distortion + Noise vs Temperature (Figure 30 and Figure 31) for additional power levels.
See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 11).
Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).
Measured using Figure 1.
100kΩ pull-up resistor to (V+). E/D common to (V–). Status flag indicates an over temperature or over-current condition.
See Typical Characteristic curves for current limit behavior.
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www.ti.com ....................................................................................................................................... SBOS391A– DECEMBER 2007 – REVISED DECEMBER 2008
ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
PARAMETER
CONDITIONS
MIN
Pin Open or Forced High
TYP
MAX
UNIT
E/D Com + 2.5
E/D Com + 5
V
E/D Com
E/D Com +
0.65
V
E/D (ENABLE/DISABLE) PIN
E/D Pin, Referenced to E/D Com Pin (14) (15)
High (output enabled)
VSD
Low (output disabled)
VSD
Pin Forced Low
Output Disable Time
4
µs
Output Enable Time
3
µs
E/D COM PIN
Voltage Range
(V–)
(V+) – 5
V
POWER SUPPLY
Specified Range
VS
±50
Operating Voltage Range
±5
Quiescent Current
IQ
Quiescent Current in Shutdown Mode
V
±50
V
IO = 0
3.2
4
mA
IO = 0, VE/D = 0.65V
150
210
µA
TEMPERATURE RANGE
Specified Range
TA
–40
+85
°C
Operating Range
TA
–55
+125
°C
Thermal Resistance, Junction-to-Case (16)
θJC
SO-8 PowerPAD (17)
Thermal Resistance, Junction-to-Ambient
SO-8 PowerPAD (17)
(14)
(15)
(16)
(17)
10
°C/W
24/52
°C/W
θJA
See typical characteristic curve, IENABLE vs VENABLE (Figure 46).
High enables the outputs.
TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
Lower value is for land area of 1-inch × 1-inch, 2-oz copper. Upper value is for exposed-pad sized area of 1-oz copper.
xxx
xxx
+50V
E/D
VOUT
RL
50kW
100VPP
10kHz
E/D Com
-50V
Figure 1. Feedthrough Capacitance Circuit
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
PHASE MARGIN vs TEMPERATURE
081
07
Fp03 = C
°)
061
L
V0 =
V54+ =
56
041
021
VMC =V5
-4
VMC
VMC
°
06
001
esahP
55
08
06
,Bd( esahP ,niaG pooL-nepO
001
Rk78.4 =
02 DAOL
Fp05 =
DC
AOL
V0 =0 VMC
0
-2
1
1.0
01
05
Fp001 = C
niaG
W
) ( nigraM esahP
04
Fp002 = C
L
L
54
04
521
)zH( ycneuqerF
001
57
05
5
-7
0
-5
5
-2
52
)C ( erutarepmeT daP lamrehT desopxE
°
Figure 2.
Figure 3.
UNITY-GAIN BANDWIDTH
vs TEMPERATURE
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
8.3
M1
W
6.3
k001
4.3
2.3
V0 =
0.3
k01
VMC
k1
8.2
V54 =
6.2
V54 =
4.2
)zHM( htdiwdnaB
VMC
VMC
001
-
) ( ecnadepmI tuptuO pooL-nepO
01
2.2
Fp002 dna ,Fp001 .Fp03 = C
0.2
1
001
57
05
5
-7
L
0
-5
5
-2
52
M01
)C ( erutarepmeT daP lamrehT desopxE
M1
k00
k1
°
Figure 4.
OPEN-LOOP GAIN vs PEAK-LOAD CURRENT
041
k84 =
)cd( V0
94
01 =
Am1 =
V S =V5
±1
ALO
001
09
ROL
DA
TV
UO
I
TUO
VS=V
±4
08
W
±
±
09
k8.4 = R
)cd( V0984 ,V84+ =
Am01 ot Am9.9+ =
)Bd(
ALO
OPEN-LOOP GAIN vs TEMPERATURE
011
011
)Bd(
Figure 5.
021
021
07
TV
UO
W
L
-
I
TUO
-
07
k88.1 = R L
W
009 = R L
W
,VU7O4+ = )c)cdd( (VV78
-44 ,
T
TV
U5
O4+ =
06
Am52 = TUO
I
±Am25 ot Am05 =
I
TUO
06
05
0
521
)Am( I kaeP
L
001
57
05
5
-572
0
-5
0
-
5
-2
)C ( erutarepmeT daP lamrehT desopxE
Figure 6.
6
k01
)zH( ycneuqerF
031
V S =V0
±5
5
01
041
031
01
1
001
°
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
POWER-SUPPLY AND COMMON-MODE
REJECTION RATIO vs TEMPERATURE
COMMON-MODE REJECTION RATIO vs FREQUENCY
140
120
120
100
PSRR and CMRR (dB)
PSRR
CMRR (dB)
100
80
VCM = -45V
60
40
VCM = +45V
80
60
100
1k
10k
100k
1.3MHz, CMRR
20
1M
VCM = +45V
VCM = -45V
0
-75
0
10
100kHz, CMRR
40
20
1
1kHz, CMRR
10kHz, CMRR
10M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Exposed Thermal Pad Temperature (°C)
Figure 8.
Figure 9.
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(Measured When Status Flag Transitions From Low to High)
140
50
120
49
100
48
VOUT (V)
PSRR (dB)
-55°C
80
60
47
+85°C
+125°C
+25°C
-47
40
-48
20
-49
0
-50
-55°C
1
10
100
1k
10k
100k
1M
0
20
30
40
IOUT (mA)
Figure 10.
Figure 11.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
DDA PACKAGE OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
120
Population
80
50
Average = 111mV
Standard Deviation = 142mV
VOUT = ±49V
RL = 4.8kW
IOUT = ±10mA
100
Output Voltage (VPP)
10
Frequency (Hz)
60
40
20
0
0
50
100
150
200
250
300
-4000 -3000 -2000 -1000
Frequency (kHz)
0
1000
2000
3000
4000
Offset Voltage (mV)
Figure 12.
Figure 13.
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
OFFSET VOLTAGE
DRIFT PRODUCTION DISTRIBUTION
SOLDER-ATTACHED, VOS TC SHIFT
Average = 0.34mV/°C
Standard Deviation = 0.44mV/°C
10
2.0
9
1.6
8
1.2
7
0.8
6
0.4
5
0
4
Offset Voltage Drift (mV/°C)
-0.4
3
-0.8
2
-1.2
1
-1.6
0
-2.0
Population
Population
Average = 1.57mV/°C
Standard Deviation = 0.84mV/°C
Output Voltage Shift (mV/°C)
Figure 14.
Figure 15.
DDA PACKAGE, SOLDER-ATTACHED, VOS SHIFT
OFFSET VOLTAGE WARMUP
(60 Devices)
200
Average = 48mV/°C
Standard
Deviation = 28mV/°C
Population
Offset Voltage (mV)
150
100
VS = ±50V
PowerPAD Attached
9in ´ 12in 0.062
Layer Metal PCB FR10
50
0
-50
-100
-200
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-150
100s/div
Offset Voltage Shift (mV)
Figure 16.
Figure 17.
QUIESCENT CURRENT PRODUCTION DISTRIBUTION
QUIESCENT CURRENT vs SUPPLY VOLTAGE
3.25
3.20
IQ (mA)
Population
3.15
3.10
3.05
3.00
3.9
3.8
3.6
3.7
3.5
3.4
3.3
2.90
3.2
3.1
3.0
2.9
2.8
2.6
2.7
2.5
2.95
0
20
30
40
50
60
70
80
90 100 110 120
Total Supply Voltage (V)
Quiescent Current (mA)
Figure 18.
8
10
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
SHUTDOWN CURRENT vs TEMPERATURE
4.0
200
5 Typical Units Shown
3.8
Shutdown Current (mA)
3.6
IQ (mA)
3.4
3.2
3.0
2.8
2.6
2.4
180
160
140
120
2.2
2.0
-75
-50
0
-25
25
50
75
100
100
-75
125
-50
-25
0
25
50
75
100
Exposed Thermal Pad Temperature (°C)
Exposed Thermal Pad Temperature (°C)
Figure 20.
Figure 21.
INPUT BIAS CURRENT vs TEMPERATURE
125
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
20
100
15
10
10
IB (pA)
IB (pA)
5
0
-5
1
Common-Mode Voltage Range
-10
-15
0.1
-75
-50
-25
0
25
50
75
100
-20
-50 -40 -30
125
-20 -10
0
10
20
30
40
Exposed Thermal Pad Temperature (°C)
VCM (V)
Figure 22.
Figure 23.
CURRENT LIMIT vs TEMPERATURE
STATUS FLAG VOLTAGE vs TEMPERATURE
(E/D Com Connected to V–) (1)
200
50
8
7
RP = 20kW, IP = 5mA
180
6
VFLAG to V-
ILIMIT (mA)
Sourcing
160
140
5
4
RP = 50kW, IP = 2mA
3
RP = 100kW, IP = 100mA
2
120
1
Sinking
100
-75
-50
-25
0
25
50
75
100
125
RP = 200kW, IP = 50mA
0
-75
Exposed Thermal Pad Temperature (°C)
Figure 24.
(1)
-50
-25
0
25
50
75
100
125
Exposed Thermal Pad Temperature (°C)
Figure 25.
See Figure 57 in the Applications Information section.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
MAXIMUM POWER DISSIPATION
vs TEMPERATURE WITH MINIMUM ATTACH AREA
SLEW RATE vs TEMPERATURE
2.0
16
SO-8 PowerPAD:
TJ(max) = +125°C
15
14
Slew Rate (V/ms)
Dissipation (W)
1.5
1.0
0.5
TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA]
qJA = +52°C/W, SO-8 PowerPAD
(1in ´ 0.5in [25.4mm x 12.7mm]
Heat-Spreader, 1oz Copper)
TJ = +25°C + (1.93W ´ 52°C/W) = +125°C
0
-50
-25
0
25
50
13
12
11
G = +1
VS = ±45V
VIN = 80V Step
RLOAD = 4.8kW
10
9
75
100
8
-75
125
-50
-25
0
25
50
75
100
125
Exposed Thermal Pad Temperature (°C)
Exposed Thermal Pad Temperature (°C)
Figure 26.
Figure 27.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
0.01Hz TO 10Hz INPUT VOLTAGE NOISE
100
5mV/div
Voltage Noise (nV/ÖHz)
1000
10
1
10
100
1k
10k
20s/div
100k
Frequency (Hz)
THD + N (%)
0.035
Figure 29.
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
0.0030
G = +10
RI = 4.75kW
VPK = 38.6V
0.0025
0.030
0.025
VS = -55, +55
0.020
THD + N (%)
0.040
Figure 28.
G = +1
RI = 4.75kW
VPK = 38.6V
VS = +41.6, -40.6
0.0020
0.0015
VS = +40.6,
-39.6
0.0010
VS = -49, +50
0.0005
0.015
0
0.010
10
100
1k
10k
100k
10
Figure 30.
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
VIN
VIN
G = +1
TC = +105°C
CLOAD = 50pF
VCM = +30V
RF = 10kW
500mV/div
500mV/div
G = +1
TC = +60°C
CLOAD = 50pF
VCM = +30V
RF = 10kW
VOUT
VOUT
Time (1ms/div)
Time (1ms/div)
Figure 32.
Figure 33.
LARGE-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
TC = +125°C
TC = -55°C
50mV
VIN (200mV/div)
VOUT (400mV/div)
TC = +25°C
G = +2
TC = +100°C
CLOAD = 100pF
VCM = +40V
RF = 10kW
VIN
VOUT
G = +1
CLOAD = 100pF
VCM = 0V
RF = 0W
Time (500ns/div)
Time (2.5ms/div)
2.0
1.5
Figure 34.
Figure 35.
STEP RESPONSE
GAIN PEAKING vs CLOAD
(G = +1, VCM = 0V) (2)
180
G = +1
G = +2
140
0.5
Peaking (%)
VOUT (V)
1.0
0
-0.5
TC = -55°C
TC = +25°C
120
TC = +85°C
100
TC = +125°C
80
60
-1.0
-1.5
RF = 0 W
RF = 10kW
160
RF = 10kW
CLOAD = 100pF, 125°C
VCM = +40V
-2.0
40
20
0
0
1ms/div
100
200
300
400
500
CLOAD (pF)
Figure 36.
(2)
Figure 37.
See Application section, Unity-Gain Noninverting Configuration.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
GAIN PEAKING vs CLOAD
(G = +2, RF = 10kΩ, VCM = 0V)
30
CF = 0pF
CF = 2.5pF
CF = 5pF
25
GAIN OF +1 vs FREQUENCY (3)
10
TC = -55°C
TC = +25°C
CL = 200pF
6
20
TC = +85°C
15
TC = +125°C
10
CL = 100pF
4
Gain (dB)
Peaking (%)
TA = +25°C
8
2
0
5
-2
0
RF = 10kW, CF = 50pF
RF = 0W
-4
-5
0
100
200
300
400
500
10k
CLOAD (pF)
10
100k
1M
10M
Frequency (Hz)
Figure 38.
Figure 39.
GAIN OF +2 vs FREQUENCY (4)
SETTLING TIME, POSITIVE STEP
(20V Step, Gain = 1, RF = 10kΩ) (5) (6)
0.08
20
TA = +25°C
CL = 500pF
8
0.06
15
0.04
10
0.02
5
VIN (V)
4
CL = 50pF
2
V2 (Noninverting)
0
-5
-2
-10
CF = 0pF
CF = 2.5pF
CF = 5pF
-4
0
0
-0.02
VIN
-0.06
-15
-0.08
-20
-6
10k
100k
1M
10M
-0.04
Voltage at V1 and V2 (V)
V1 (Inverting)
6
Gain (dB)
CL = 50pF
-6
Time (1ms/div)
Frequency (Hz)
Figure 40.
(3)
(4)
(5)
(6)
12
Figure 41.
See Application section Unity-Gain Noninverting Configuration.
See Application section Unity-Gain Noninverting Configuration.
See the Settling Time section.
The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
SETTLING TIME, NEGATIVE STEP
(20V Step, Gain = 1, RF = 10kΩ) (7) (8)
15
0.06
VIN
10
0.04
5
0.02
0
V2 (Noninverting)
0
-0.02
-5
-10
-0.04
V1 (Inverting)
Voltage at V1 and V2 (V)
VIN (V)
ENABLE RESPONSE TIME
0.08
20
OUT
20V/div
Status Flag
50V/div
Enable
-0.06
-15
5V/div
-0.08
-20
Time (1ms/div)
Time (1ms/div)
Figure 42.
Figure 43.
DISABLE RESPONSE TIME
ENABLE RESPONSE
20V/div
OUT
OUT
20V/div
50V/div
50V/div
Status Flag
Enable
5V/div
Enable
Status Flag
5V/div
Time (1ms/div)
Time (1ms/div)
Figure 44.
Figure 45.
IENABLE vs VENABLE
ENABLE/DISABLE THRESHOLD vs TEMPERATURE
10
1.00
0.95
Threshold (V)
IENABLE (mA)
0
-40°C
-10
+25°C
+85°C
0.90
0.85
0.80
-20
0.75
-30
0
(7)
(8)
1
2
3
4
5
0.70
-75
-50
-25
0
25
50
VENABLE (V)
Temperature (°C)
Figure 46.
Figure 47.
75
100
125
See the Settling Time section.
The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
ILIMIT SHOWING FLAG DELAY
(TP = +125°C) (9)
ILIMIT SHOWING FLAG DELAY
(TP = +25°C) (10)
60
200
60
150
VFLAG
150
50
40
100
40
50
20
100
50
IOUT
30
0
20
-50
-50
10
-100
-100
0
0
IOUT (mA)
30
VFLAG (V)
50
IOUT (mA)
VFLAG (V)
VFLAG
IOUT
10
0
-150
RP = 100kW
RP = 100kW
-10
-150
-10
-200
10ms/div
10ms/div
Figure 48.
Figure 49.
ILIMIT SHOWING FLAG DELAY
(TP = –55°C) (11)
APPLY LOAD
(25mA Sink Response)
1.6
50
100
40
50
+125°C
+85°C
+25°C
-55°C
1.4
OPA454
1.0
VOUT (V)
IOUT
IOUT (mA)
VFLAG (V)
1.2
30
0
20
-50
10
-100
0
-150
0
-200
-0.2
+50V
0.988VPP
0.01Hz
-
150
VFLAG
2Hz
2ms Pulse
+
60
-50V
Mercury
Wetted
Relay
0.8
0.6
0.4
0.2
RP = 100kW
-10
10ms/div
Figure 50.
Figure 51.
REMOVE LOAD
(25mA Sink Response)
APPLY LOAD
(25mA Source Response)
0.2
0
0
-0.2
-0.2
-0.4
-0.4
VOUT (V)
0.2
-0.6
-0.8
-
OPA454
-50V
-1.6
+50V
0.988VPP
0.01Hz
OPA454
+
-1.4
-1.0
-
-1.2
+125°C
+85°C
+25°C
-55°C
-0.8
+50V
0.988VPP
0.01Hz
-1.0
-0.6
2Hz
2ms Pulse
-1.2
Mercury
Wetted
Relay
-1.4
2Hz
2ms Pulse
+
VOUT (V)
10ms/div
-50V
Mercury
Wetted
Relay
+125°C
+85°C
+25°C
-55°C
-1.6
10ms/div
10ms/div
Figure 52.
Figure 53.
(9) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(10) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(11) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
14
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
REMOVE LOAD
(25mA Source Response)
1.6
+125°C
+85°C
+25°C
-55°C
1.4
1.2
RL = 1.8kW
VOUT
0.6
OPA454
2Hz
2ms Pulse
-50V
Flag
20V/div
-
0.8
V+
+50V
0.988VPP
0.01Hz
+
VOUT (V)
1.0
POWER ON
Mercury
Wetted
Relay
0
0.4
Delay in V- is due to
test equipment.
Power supplies may be
applied in any sequence.
0.2
0
-0.2
V-
20ms/div
10ms/div
Figure 54.
Figure 55.
POWER OFF
V+
RL = 1.8kW
20V/div
VOUT
Flag
0
V20ms/div
Figure 56.
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APPLICATIONS INFORMATION
Figure 57 shows the OPA454 connected as a basic
noninverting amplifier. The OPA454 can be used in
virtually any ±5V to ±50V op amp configuration. It is
especially useful for supply voltages greater than
36V.
Power-supply terminals should be bypassed with
0.1µF (or greater) capacitors, located near the
power-supply pins. Be sure that the capacitors are
appropriately rated for the power-supply voltage
used.
+V
IP
F 1.0 m
+V
R
)1(
RP
1
+V
-NI
R
+1 = G
R
2
R
1
TV
UO
R
V-
L
V-
Pull-up resistor with at least 10µA (choose
RP = 1MΩ with V+ = 50V for IP = 50µA).
LOWERING OFFSET VOLTAGE AND DRIFT
Figure 57. Basic Noninverting Amplifier
Configuration
,tfirD ,V 5 ,tesffO woL
pmA pO gnioreZ-fleS ,C /V 50.0° m
V/V9.4 = ts1 niaG
ts1 , R 1
k01 W
The OPA454 can be used with an OPA735 zero-drift
series op amp to create a high-voltage op amp circuit
that has very low input offset temperature drift. This
circuit is shown in Figure 58.
pmA pO egatloV-hgiH
V/V54.9 = dn2 niaG
m
ts1 , R
k1.93
Some applications do not require equal positive and
negative output voltage swing. Power-supply voltages
do not need to be equal. The OPA454 can operate
with as little as 10V between the supplies and with up
to 100V between the supplies. For example, the
positive supply could be set to 90V with the negative
supply at –10V, or vice-versa (as long as the total is
less than or equal to 100V).
The OPA454 has increased protection against
damage caused by excessive voltage between op
amp input pins or input pin voltages that exceed the
power supplies; external series resistance is not
needed for protection. Internal series JFETs limit
input overload current to a non-destructive 4mA, even
with an input differential voltage as large as 120V.
Additionally, the OPA454 has dielectric isolation
between devices and the substrate. Therefore, the
amplifier is free from the limitations of junction
isolation common to many IC fabrication processes.
TV
UO
D/E
The OPA454 may be operated from power supplies
up to ±50V or a total of 100V with excellent
performance. Most behavior remains unchanged
throughout the full operating voltage range.
Parameters that vary significantly with operating
voltage are shown in the Typical Characteristics.
INPUT PROTECTION
sutatS
galF
454APO
NI+
VNI
moC D/E
VF 1.0 m
(1)
2
POWER SUPPLIES
dn2 , R 1
k01 W
2
dn2 , R 2
k5.48
W
W
+V
V05+ ,egatS dn2
+V
V5+ ,egatS ts1
egatS dn2
egatS ts1
TV
UO
TV
UO
454APO
egatS dn2 , A 2
537APO
DR
AOL
k01 W
egatS ts1 , A 1
V1 = V G
xaM ,V9.4 egatS ts1
VV5 ,egatS ts1
±
VP1P =
TUV
PNI
TV
UO
VV±
05 ,egatS dn2
-
xaM ,) VP2P9( V64 egatS dn2
TV
UO
±
±
Figure 58. Two-Stage, High-Voltage Op Amp Circuit With Very Low Input Offset Temperature Drift
16
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INCREASING OUTPUT CURRENT
R
The OPA454 drives an output current of a few
milliamps to greater than 50mA while maintaining
good op amp performance. See Figure 7 for
open-loop gain versus temperature at various output
current levels.
In applications where the 25mA output current is not
sufficient to drive the required load, the output current
can be increased by connecting two or more
OPA454s in parallel, as Figure 59 shows. Amplifier
A1 is the master amplifier and may be configured in
virtually any op amp circuit. Amplifier A2, the slave, is
configured as a unity-gain buffer. Alternatively,
external output transistors can be used to boost
output current. The circuit in Figure 60 is capable of
supplying output currents up to 1A, with the
transistors shown.
R
1
2
) 1(
RS
01 W
RETSAM
15
A4APO
4
VNI
)1(
RS
01 W
4
25
A4APO
R
EVA LS
L
(1) RS resistors minimize the circulating current that always flows
between the two devices because of VOS errors.
Figure 59. Parallel Amplifiers Increase Output
Current Capability
UNITY-GAIN NONINVERTING
CONFIGURATION
When in the noninverting unity-gain configuration, the
OPA454 has more gain peaking with increasing
positive common-mode voltage and increasing
temperature. It has less gain peaking with more
negative common-mode voltage. As with all op amps,
gain peaking increases with increasing capacitive
load. A resistor and small capacitor placed in the
feedback path can reduce gain peaking and increase
stability.
R
R
1
2
V05+
NPN
,49112LJM ,C92PIT
1823LJM ,30051EJM
CF
-NI
)1(
3
+V
TV
UO
VNI
)2(
R
02 W
R4
2.0 W
454APO
NI+
L
V-
R5
2.0 W
L
TUR
O
R
L
I
) 3(
VO V =
-
IL
PNP
,39112LJM ,C03PIT
A2031LJM ,40051EJM
V0
-5
(1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7V and –0.7V.
(2) Op amp VOUT swings from +47V to –48V.
(3) VO swings from +44.1V to –45.1V at IL = 1A.
Figure 60. External Output Transistors Boost Output Current Greater Than 1A
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INPUT RANGE
0.6
-4
5.05
+V
C 52+ = T A
°
C 52+ = T A
5.6
-4
°
0.7
-4
5.7
-4
TV
UO
k05 = R S
0.8
-4
5.8
-4
)V( egaVtlo
The OPA454 is specified to give linear operation with
input swing to within 2.5V of either supply. Generally,
a gain of +1 is the most demanding configuration.
Figure 61 and Figure 62 show output behavior as the
input swings to within 0V of the rail, using the circuit
shown in Figure 64. Figure 63 shows the behavior
with an input signal that swings beyond the specified
input range to within 1V of the rail, also using the
circuit in Figure 64. Notice that the beginning of the
phase reversal effect may be reduced by inserting
series resistance (RS) in the connection to the
0016
positive input. Note that VOUT does not 0swing
all the
way to the opposite rail.
W
0.9
-4
TV
UO
0= RS
VNI
5.9
-4
zHk1 = f
W
0.0
-5
V-
5.0
-5
040
02
08
)s ( emiT
m
Figure 63. Output Voltage With Input Voltage
Down To (V–) + 1V
0.05
VNI
5.94zHk1 = f
TV
UO
k05 = R S
RF
k01 W
W
0.94
5.84
)V( egatloV
V05+ = +V
0.84
TV
UO
0= RS
5.74
R S 454APO
0.74
040
02
VNI
08
)s ( emiT
W
Figure 64. Input Range Test Circuit
OUTPUT RANGE
0.6
-4
C 52+ = T A
5.6
-4
°
TV
UO
0= RS
W
5.7
-4
TV
UO
k05 = R S
0.8
-4
5.8
-4
)V( egaVtlo
V05 =- V -
L
m
Figure 61. Output Voltage With Input Voltage Up
To V+
0.7
-4
TV
UO
R
k8.4
W
W
0.9
-4
5.9
-4
zHk1 = f
0.0
-5
V5.0
-5
040
VNI
02
The OPA454 is specified to swing to within 1V of
either supply rail with a 49kΩ load while maintaining
excellent linearity. Swing to the rail decreases with
increasing output current. The OPA454 can swing to
within 2V of the negative rail and 3V of the positive
rail with a 1.88kΩ load. The typical characteristic
curve, Output Voltage Swing vs Output Current
(Figure 11), shows this behavior in detail.
08
)s ( emiT
m
Figure 62. Output Voltage With Input Voltage
Down To V–
18
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Figure 65 shows the nonlinear relationship of AOL and
output voltage. As Figure 65 shows, open-loop gain is
lower with positive output voltage levels compared to
negative voltage levels. Specifications in the
Electrical Characteristics table are based upon the
average gain measured at both output extremes.
The circuit in Figure 66 is used to measure the
settling time response. The left half of the circuit is a
standard, false-summing junction test circuit used for
settling time and open-loop gain measurement. R1
and R2 provide the gain and allow for measurement
without connecting a scope probe directly to the
summing junction, which can disturb proper op amp
function by causing oscillation.
noitcnuF a si ALO
C 52+ = T P
The right half of the circuit looks at the combination of
both inverting and noninverting responses. R5 and R6
remove the large step response. The remaining
voltage at V2 shows the small-signal settling time that
is centered on zero. This test circuit can be used for
incoming inspection, real-time measurement, or in
designing
compensation
circuits
in
system
applications.
°
-|)
08R
81L =vid/VmW1 ,
0R
09Lv=id/VmW2 ,
V(| +NI ) -V(
fo
TV
UO
SETTLING TIME
Bd47
k78.4 = R Lvim
d/V 00W2 ,
05
04
0
-053
0
-4
0
-031
0
-2
Bd98
Bd601
NI
Lna
OPEN-LOOP GAIN LINEARITY
0
-1
Table 2. Settling Time Measurement Circuit
Configuration Using Different Gain Settings for
Figure 66
02
)V( egatloV tuptuO
GAIN
Figure 65. Differential Input Voltage (+IN to –IN)
versus Output Voltage
esnopseR gnitrevnI
V ,ereH derusaeM
COMPONENT
1
5
10
R1 (Ω)
10k
2k
1k
R3 (Ω)
10k
2k
1k
R7 (Ω)
10k
4k
9k
R8 (Ω)
∞
1k
1k
VIN (VPP)
20
16
8
1
R
1
R
3
R2
k01 W
hR
toB4 fo noitanibmoC
k01 W
dna gnitrevnI
V ,sesnopseR gnitrevninoN
-NI
454APO
NI+
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R5
k01 W
R
R
7
8
2
R6
k01 W
A1
TV
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454APO
A2
-NI
NI+
VNI
Figure 66. Settling Time Test Measurement Circuit
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
+V
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RP
DDVD
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THERMAL PROTECTION
Figure 68 shows the thermal shutdown behavior of a
socketed OPA454 that internally dissipates 1W.
Unsoldered and in a socket, θJA of the DDA package
is typically +128°C/W. With the socket at +25°C, the
output stage temperature rises to the shutdown
temperature of +150°C, which triggers automatic
thermal shutdown of the device. The device remains
in thermal shutdown (output is in a high-impedance
state) until it cools to +130°C where it again is
powered. This thermal protection hysteresis feature
typically prevents the amplifier from leaving the safe
operating area, even with a direct short from the
output to ground or either supply. The rail-to-rail
supply voltage at which catastrophic breakdown
occurs is typically 135V at +25°C. However, the
absolute maximum specification is 120V, and the
OPA454 should not be allowed to exceed 120V under
any condition. Failure as a result of breakdown,
caused by spiking currents into inductive loads
(particularly with elevated supply voltage), is not
prevented by the thermal protection architecture.
041
04
+V
-NI
cigoL V5
D/E
021
TV
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001
0
TV
UO
454APO
V-
0
-2
08
)V(
moC D/E
0
-4
06
TV
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NI+
02
0
-6
04
0
-8
02
VLF
GA
00
-1
V)ylppuS pmA pO evitageN(
0001
0
02
-1
0040
002
)sm(
k01 W
CURRENT LIMIT
20
0
-2
008
006
Figure 67. ENABLE and E/D Com
Figure 24 and Figure 48 to Figure 50 show the
evaW erauqS zH01
current limit behavior of the OPA454. Current limiting
is accomplished by internally limiting the drive to the
output transistors. The output can supply the limited
current continuously, unless the die temperature rises
to +150°C, which initiates thermal shutdown. With
adequate heat-sinking, and use of the lowest possible
supply voltage, the OPA454 can remain in current
limit continuously without entering thermal shutdown.
Although qualification studies have shown minimal
parametric shifts induced by 1000 hours of thermal
shutdown cycling, this mode of operation should be
VLF
GA
If left disconnected, E/D Com is pulled near V–
(negative supply) by an internal 10µA current source.
When left floating, ENABLE is held approximately 2V
above E/D Com by an internal 1µA source. Even
though active operation of the OPA454 results when
the ENABLE and E/D Com pins are not connected, a
moderately fast, negative-going signal capacitively
coupled to the ENABLE pin can overpower the 1µA
pull-up current and cause device shutdown. This
behavior can appear as an oscillation and is
encountered first near extreme cold temperatures. If
the enable function is not used, a conservative
approach is to connect ENABLE through a 30pF
capacitor to a low impedance source. Another
alternative is the connection of an external current
source from V+ (positive supply) sufficient to hold the
enable level above the shutdown threshold. Figure 67
shows a circuit that connects ENABLE and E/D Com.
Choosing RP to be 1MΩ with a +50V positive power
supply voltage results in IP = 50µA.
avoided to maximize reliability. It is always best to
provide proper heat-sinking (either by a physical plate
or by airflow) to remain considerably below the
thermal shutdown threshold. For longest operational
life of the device, keep the junction temperature
below +125°C.
)V(
ENABLE AND E/D Com
V5.2+
k001
V05+
RP
M1 W
+V
-NI
galF
VLF
GA
TV
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45I+4APO
N
TV
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moC D/E
V-
526 W
V0
-5
Figure 68. Thermal Shutdown
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POWER DISSIPATION
HEATSINKING
Power dissipation depends on power supply, signal,
and load conditions. For dc signals, power dissipation
is equal to the product of the output current times the
voltage across the conducting output transistor,
PD = IL (VS – VO). Power dissipation can be
minimized by using the lowest possible power-supply
voltage necessary to assure the required output
voltage swing.
Power dissipated in the OPA454 causes the junction
temperature to rise. For reliable operation, junction
temperature should be limited to +125°C, maximum.
Maintaining a lower junction temperature always
results in higher reliability. Some applications require
a heatsink to assure that the maximum operating
junction temperature is not exceeded. Junction
temperature can be determined according to
Equation 1:
For resistive loads, the maximum power dissipation
P
+
T
=
T
q
A
J
D
A
J
(1)
occurs at a dc output voltage of one-half the
power-supply voltage. Dissipation with ac signals is
Package thermal resistance, θJA, is affected by
lower because the root-mean square (RMS) value
mounting techniques and environments. Poor air
determines heating. Application Bulletin SBOA022
circulation and use of sockets can significantly
explains how to calculate or measure dissipation with
increase thermal resistance to the ambient
unusual loads or signals. For constant current source
environment. Many op amps placed closely together
circuits, maximum power dissipation occurs at the
also increase the surrounding temperature. Best
minimum output voltage, as Figure 69 shows.
thermal performance is achieved by soldering the op
amp onto a circuit board with wide printed circuit
The OPA454 can supply output currents of 25mA and
traces to allow greater conduction through the op
larger. Supplying this amount of current presents no
amp leads. Increasing circuit board copper area to
problem for some op amps operating from ±15V
approximately 0.5in2 decreases thermal resistance;
supplies. However, with high supply voltages, internal
however, minimal improvement occurs beyond 0.5in2,
power dissipation of the op amp can be quite high.
as shown in Figure 70.
Operation from a single power supply (or unbalanced
power supplies) can produce even greater power
For additional information on determining heatsink
dissipation because a large voltage is impressed
requirements, consult Application Bulletin SBOA021
across the conducting output transistor. Applications
(available for download at www.ti.com).
with high power dissipation may require a heatsink, or
heat spreader.
06
R2
k01 W
1
05
° )WqA/JC (
W
V1
04
V05+
-NI
03
+V
TV
UO
454APO
NI+
R
k001
3
W
02
VV0
-5
R
k9.9
R5
001 W
4
W
01
V2
0.3
5.2
0.2
IL
1
2
5
5.1
R
0.1
0
0
zo 2 ,) sehcni( aerA reppoC
L
V([) =R/ILR1( ] R2/)- V
k1/) V
V
W( 1= 2 -
egnaR egatloV ecnailpmoC
5.0
,ecnatsiseR lamrehT
R
k001
2
Figure 70. Thermal Resistance versus Circuit
Board Copper Area
-
NOTE: R1 = R3 and R2 = R4 + R5.
Figure 69. Precision Voltage-to-Current Converter
with Differential Inputs
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OPA454
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THERMALLY-ENHANCED PowerPAD
PACKAGE
The OPA454 comes in an SO-8 PowerPAD version
that provides an extremely low thermal resistance
(θJC) path between the die and the exterior of the
package. This package features an exposed thermal
pad. This thermal pad has direct thermal contact with
the die; thus, excellent thermal performance is
achieved by providing a good thermal path away from
the thermal pad.
The OPA454 SO-8 PowerPAD is a standard-size
SO-8 package constructed using a downset
leadframe upon which the die is mounted, as
Figure 71 shows. This arrangement results in the
lead frame being exposed as a thermal pad on the
underside of the package. The thermal pad on the
bottom of the IC can then be soldered directly to the
PCB, using the PCB as a heatsink. In addition,
plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB.
This architecture enhances the OPA454 power
dissipation capability significantly, eliminates the use
of bulky heatsinks and slugs traditionally used in
thermal packages, and allows the OPA454 to be
easily mounted using standard PCB assembly
techniques. NOTE: Because the SO-8 PowerPAD is
pin-compatible with standard SO-8 packages, the
OPA454 is a drop-in replacement for operational
amplifiers in existing sockets. Soldering the
PowerPAD to the PCB is always required, even with
applications that have low power dissipation.
Soldering the device to the PCB provides the
necessary thermal and mechanical connection
between the leadframe die pad and the PCB.
)yollA reppoC( emarfdaeL
)nociliS( CI)yxopE( hcattA eiD
daP eiD emarfdaeL
)citsalP( dnuopmoC dloeMgakcaP eht fo esaB ta desopxE
)yollA reppoC(
.weiv noitces-ssorc DAPrewoP 8-OS )a
Figure 71. Cross-Section View of a PowerPAD Package
22
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OPA454
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PowerPAD LAYOUT GUIDELINES
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
must be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other
heat-dissipating device. Soldering the PowerPAD to
the PCB is always required, even with applications
that have low power dissipation. Follow these steps
to attach the device to the PCB:
1. The PowerPAD must be connected to the most
negative supply voltage on the device, V–.
2. Prepare the PCB with a top-side etch pattern.
There should be etching for the leads as well as
etch for the thermal pad.
3. Use of thermal vias improves heat dissipation,
but are not required. The thermal pad can
connect to the PCB using an area equal to the
pad size with no vias, but externally connected to
V–.
4. Place recommended holes in the area of the
thermal pad. Recommended thermal land size
and thermal via patterns for the SO-8 DDA
package are shown in the thermal land pattern
mechanical drawing appended at the end of this
document. These holes should be 13 mils
(.013in, or 0.3302mm) in diameter. Keep them
small, so that solder wicking through the holes is
not a problem during reflow. The minimum
recommended number of holes for the SO-8
PowerPAD package is five.
5. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These vias help dissipate the heat
generated by the OPA454 IC. These additional
vias may be larger than the 13 mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered; thus, wicking is not a
problem.
6. Connect all holes to the internal power plane of
the correct voltage potential (V–).
7. When connecting these holes to the plane, do not
use the typical web or spoke via connection
methodology. Web connections have a high
thermal resistance connection that is useful for
slowing the heat transfer during soldering
operations, making the soldering of vias that have
plane connections easier. In this application,
however, low thermal resistance is desired for the
most efficient heat transfer. Therefore, the holes
under the OPA454 PowerPAD package should
make the connections to the internal plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
8. The top-side solder mask should leave the
terminals of the package and the thermal pad
area exposed. The bottom-side solder mask
should cover the holes of the thermal pad area.
This masking prevents solder from being pulled
away from the thermal pad area during the reflow
process.
9. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
10. With these preparatory steps in place, the
PowerPAD IC is simply placed in position and run
through the solder reflow operation as any
standard
surface-mount
component.
This
preparation results in a properly installed part.
For detailed information on the PowerPAD package,
including thermal modeling considerations and repair
procedures, see technical brief SLMA002 PowerPAD
Thermally-Enhanced Package, available for download
at www.ti.com.
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
TYPICAL APPLICATIONS
Figure 72 and Figure 73 illustrate the OPA454 in a programmable voltage source and a bridge circuit,
respectively.
V59+
F 1.0 m
k3.54
Am2-0
1188CAD
W
-NI
ro
1187CAD
+V
454APO
NI+
CAD stcetorP
gniwelS gniruD
V19+ ot V0 =
TV
UO
R
VF 1.0 m
L
V
-5
Figure 72. Programmable Voltage Source
R1
k1 W
R3
k01 W
R2
k9 W
R4
k01 W
V05+
V05+
-NI
+V
RETSAM
VNI
V
±4
+V
TV
UO
454APO
NI+
V-
A1
oT pU
V591
ozeiP
latsyrC
-NI
TV
UO
)1(
454APO
A2
V-
V0
-5
EVA LS
NI+
V0
-5
(1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing
the Slave amplifier.
Figure 73. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals
24
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Figure 74 uses three OPA454s to create a
high-voltage instrumentation amplifier. VCM ± VSIG
must be between (V–) + 2.5V and (V+) – 2.5V. The
maximum supply voltage equals ±50V or 100V total.
V+
V1
OPA454
A1
Figure 75 uses three OPA454s to measure current in
a high-side shunt application. VSUPPLY must be
greater than VCM. VCM must be between (V–) + 2.5V
and (V+) – 2.5V. Adhering to these restrictions keeps
V1 and V2 within the voltage range required for linear
operation of the OPA454. For example, if V+ = 50V
and V– = 50V, then V1 = +47.5V (maximum) and
V2 = –47.5V (minimum). The maximum supply
voltage equals ±50V, or 100V total.
R4
VR2
R5
V+
VSIG
OPA454
(1)
A3
R1
VOUT
R2
VR6
V+
See Figure 76 and Figure 79 for example circuits that
use the OPA454 in an output voltage boost
configurations in three and six op amp output stages,
respectively.
R7
OPA454
A2
V2
VCM
VOUT = (1 + 2R2/R1) (V2 - V1)
V-
(1) The linear input range is limited by the output swing on the
input amplifiers, A1 and A2.
Figure 74. High-Voltage Instrumentation Amplifier
RSHUNT
V+
VSUPPLY
Plus
or
Minus
V1
Load
OPA454
A1
(1)
R4
VR2
R5
V+
OPA454
R1
VOUT
(2)
A3
R2
VR6
V+
R7
OPA454
A2
V2
(1)
VOUT = (1 + 2R2/R1) (V2 - V1)
V-
(1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers.
(2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
Figure 75. High-Voltage Instrumentation Amplifier for Measuring High-Side Shunt
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OPA454
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+100V
+100V
10kW
10kW
+100V
+100V
100kW
V01
V04
OPA454
V-
190kW
OPA454
A4
A1
10kW
100kW
V+
V+
10kW
V-
200kW
100kW
V+
VLOAD = +97V, -98V
(195VPP)
VOUT
OPA454
100kW
A3
VIN
V+
OPA454
A6
RLOAD
3.75kW
V-
VLOAD = +97V, -98V
(195VPP)
VOUT
RLOAD
3.75kW
V-
VIN
10kW
10kW
100kW
100kW
V05 V+
OPA454
A5
V02 V+
OPA454
A2
V-
V100kW
100kW
-100V
-100V
-100V
-100V
a) Noninverting, G = +20V/V
b) Inverting, G = -20V/V
Figure 76. Output Voltage Boost With +97V, –98V (195VPP) Across Load Connected to Ground (3 Op Amp
Output Stage, see Figure 77 and Figure 78)
100
100
50
40
25
VOUT (V)
Voltage (V)
VOUT
60
VLOAD
0
-25
6
80
V01
4
VIN
2
20
0
0
VIN (V)
75
-20
V02
-2
-40
-50
-60
-4
-75
-80
Time (10ms/div)
Time (20ms/div)
Figure 77. 195VPP On 3.75kΩ Load to Ground
20kHz, Uses 3 OPA454s, 100V Supplies
26
-6
-100
-100
Figure 78. 3.75kΩ Load to Ground
G = +20, 3 OPA454s, 100V Supplies
(Note SR of 18V/µs, which is slightly higher than
the specified 13V/µs due to tracking of the
power-supply voltage)
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+100V
+100V
10kW
10kW
+120V
+120V
100kW
100kW
V+
V+
OPA454
OPA454
A1
10kW
A4
V-
190kW
V100kW
(+97V, -98V)
10kW
100kW
RLOAD
7.5kW
V+
200kW
V+
(-98V, +97V)
OPA454
OPA454
A3
A6
VLOAD
(±195V, 390VPP)
V-
V-
10kW
10kW
VIN
100kW
100kW
V+
V+
OPA454
OPA454
A2
A5
V-
V100kW
100kW
-100V
-100V
-100V
-100V
Figure 79. Output Voltage Boost With ±195V (390VPP) Across Bridge-Tied Load (6 Op Amps, see
Figure 80 and Figure 81)
200
VLOAD
6
200
150
150
50
0
VIN
VOUT
2
50
0
0
-50
-50
-100
-100
-150
-150
4
VIN (V)
100
VOUT (V)
VOUT (V)
100
-2
-4
-200
-200
-6
Time (10ms/div)
Time (20ms/div)
Figure 80. 390VPP Across 7.5kΩ Load
20kHz, Uses 6 OPA454s, 100V Supplies
Figure 81. 7.5kΩ Load
G = +20, 6 OPA454s, 100V Supplies
(Note SR of 34V/µs, which is significantly higher
than the specified 13V/µs due to tracking of the
power-supply voltage)
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OPA454
SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008 ....................................................................................................................................... www.ti.com
R1
25kW
A red light emitting diode (LED) was used to generate
Figure 84.
R2
25kW
V1
VOUT = V2 - V1
OPA454
R3
25kW
Gain of the avalanche photodiode (APD) is adjusted
by changing the voltage across the APD. Gain starts
to increase when reverse voltage is increased beyond
130V for this APD diode. Figure 85 shows this
structure.
R4
25kW
41
V6
V2
21
TV
UO
01
Figure 82. High-Voltage Difference Amplifier
8
VEL
D
V0
This section describes four different applications
utilizing high compliance voltage current sources with
differential inputs. Figure 69 and Figure 83 illustrate
the different applications.
4
VEL
D
HIGH-COMPLIANCE VOLTAGE CURRENT
SOURCES
2
)V(
)V
vid
O
T/UV1(
6
0
-2
V
-2
vid/sm5
Figure 84. Avalanche Photodiode Circuit
k52 W
k52 W
V1
454APO
A1
k52 W
k52 W
R
V2
454APO
A2
daoL
1
V
2 ( = IO
IO
R/)- V
Figure 83. Differential Input Voltage-to-Current
Converter for Low IOUT
28
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R7
10kW
R1
90kW
+100V
+100V
R2
1kW
V+
V+
OPA454
OPA454
A1
R4
100kW
A2
+100V
V-
V-
VOUT = 100 ´ RSENSE ´ ID
V+
OPA454
+
V1
Gain Adjust Voltage
2.5V to 9.5V
RSENSE
100W
VOUT
V-
+100V
+100V
R8
198kW
R3
1kW
V+
OPA454
A4
R9
4.9kW
A3
V-
R5
100kW
LM4041D
Adjusted for 2.0V
100W
APD
LED
R10
3.1kW
VLED
-200V
Example Circuit For Reverse Biasing APD
(130V to 280V, max)
Advanced Photonix, Inc.
SD 036-70-62-531
Digi-Key
SD 036-70-62-531
Figure 85. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp
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29
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA454AIDDA
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA454AIDDAG4
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA454AIDDAR
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA454AIDDARG4
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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www.BDTIC.com/TI
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA454AIDDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.4
5.2
2.1
8.0
www.BDTIC.com/TI
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA454AIDDAR
SO PowerPAD
DDA
8
2500
346.0
346.0
29.0
www.BDTIC.com/TI
Pack Materials-Page 2
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
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