Download MAX1888 Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies General Description

19-2189; Rev 1; 2/02
Low-Cost Integrated Offset Logic
for Notebook CPU Power Supplies
Features
♦ Simple, Low-Cost Offset Voltage Control
for CPU Core Power Supplies
♦ IMVP II Logic Interface
♦ 3V to 5.5V Supply Voltage
♦ Low 30µA (max) Supply Current
♦ 8-Pin µMAX Package
Ordering Information
Applications
CPU Core Supplies for Intel IMVP II Notebook
Computers
PART
MAX1888EUA
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
8 µMAX
Pin Configuration
Minimal Operating Circuit
TOP VIEW
INPUT
SUPPLY
POS
VCC
OFFSET
ADJUST
MAX1888
NEG
LOWVOLTAGE
LOGIC
INPUTS
DPSLP
BSM
PERF
PSM
SUS
BOM
GND
OPEN-DRAIN
DECODER
OUTPUTS
DPSLP
1
8
PERF
2
7
BSM
SUS
3
6
PSM
GND
4
5
BOM
MAX1888
VCC
µMAX
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1
MAX1888
General Description
The MAX1888 is a three-input decoder with three opendrain outputs. It is used with the MAX1718 or a similar
DC-to-DC controller to offset the CPU core voltage in
notebook computers. Designed to interface with lowvoltage logic, the MAX1888 can program the controller
for three independent offsets. The circuit is extremely
low cost and is available in an 8-pin µMAX package.
MAX1888
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +6V
PERF, SUS, DPSLP, BOM, PSM, BSM to GND ........-0.3V to +6V
Continuous Power Dissipation
8-Pin µMAX (derate 4.5mW/°C above +70°C) ...........362.0mW
Extended Operating Temperature.......................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = +5V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
POWER SUPPLY
Supply Voltage Range (VCC)
3.0
BIAS
Quiescent Supply Current (VCC)
All inputs = 0
All inputs = 1.5V
< 0.01
1
10
30
µA
LOGIC AND I/Os
Logic Input High Voltage
(PERF, SUS, DPSLP),
Hysteresis = 40mV (typ)
Logic Input Low Voltage
(PERF, SUS, DPSLP),
Hysteresis = 40mV (typ)
3V < VCC < 5.5V
Output Leakage Current
(BOM, BSM, PSM)
V
0.4
V
3V < VCC < 5.5V
Logic Input Current
Output On-Resistance
(BOM, BSM, PSM)
1.2
0.3
-1
ILOAD = 5mA
1
20
ILOAD = 5mA, 3V < VCC < 5.5V
V(pin) = 5V
50
100
< 0.01
1
µA
Ω
µA
DYNAMICS
Propagation Delay
2
Falling edge, 1.5V to 0V step in 2ns
700
Rising edge, 0 to 1.5V step in 2ns
70
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ns
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
SUPPLY CURRENT VS. TEMPERATURE
MAX1888toc01
0.1
C
D
TA = +25°C
30
8
VCC = 4.5V
15
0
3.5
4.0
4.5
5.0
5.5
10
-40
-15
35
60
85
3.0
35
3.5
4.0
4.5
5.0
5.5
VCC (V)
SWITCHING CHARACTERISTICS
(OUTPUT TRANSITIONS INTO A 10kΩ LOAD)
SWITCHING CHARACTERISTICS
(OUTPUT TRANSITIONS INTO A 10kΩ LOAD)
MAX1888 toc05
MAX1888 toc06
MAX1888 toc04
40
10
TEMPERATURE (°C)
VCC (V)
A = ALL INPUTS = 1.5V
B = ALL INPUTS = 3.3V
C = ALL INPUTS = 5V
D = ALL INPUTS = 0.4V
OUTPUT RON VS. TEMPERATURE
25
20
VCC = 3.3V
3.0
TA = -40°C
4
0.01
0.001
TA = +85°C
35
12
RON (Ω)
1
VCC = 5V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
B
40
MAX1888 toc02
A
10
A
VCC = 3.3V
A
30
RON (Ω)
OUTPUT RON VS. SUPPLY VOLTAGE
16
MAX1888 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
100
25
20
VCC = 3.3V
B
VCC = 5V
VCC = 5V
15
B
VCC = 5V
VCC = 3.3V
10
-15
-40
10
35
60
20ns/div
85
400ns/div
A = VIN, 1V/div
B = VOUT, 1V/div
A = VIN, 1V/div
B = VOUT, 1V/div
TEMPERATURE (°C)
Pin Description
PIN
NAME
1
DPSLP
2
PERF
3
SUS
Suspend-Mode (Deeper Sleep) Control Digital Input
4
5
GND
Ground
BOM
Open-Drain Output for Battery Operating Mode (BOM)
FUNCTION
Deep-Sleep Mode Control Digital Input
Performance-Mode Offset Control Digital Input
6
PSM
Open-Drain Output for Performance Sleep Mode (PSM)
7
BSM
Open-Drain Output for Battery Sleep Mode (BSM)
8
VCC
Supply Voltage
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3
MAX1888
Typical Operating Characteristics
(Circuit of Figure 1, logic high = 1.5V, VOUT = 1.3V, TA = +25°C, unless otherwise noted.)
MAX1888
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
TTable 1. Truth Table
INPUTS
MODE
OUTPUTS
DPSLP
PERF
SUS
BSM
PSM
Deeper Sleep
X
X
H
Hi-Z
Hi-Z
Hi-Z
Battery Sleep
L
L
L
L
Hi-Z
Hi-Z
Performance Sleep
L
H
L
Hi-Z
L
Hi-Z
Battery Operating
H
L
L
Hi-Z
Hi-Z
L
Performance
H
H
L
Hi-Z
Hi-Z
Hi-Z
Detailed Description
The MAX1888 is a three-input decoder with three opendrain outputs. It is used with the MAX1718 DC-to-DC
controller to offset the CPU core voltage in notebook
computers. The MAX1718 has two dedicated inputs
(POS and NEG) that simplify the task of offsetting its
output voltage. Specifically, the output voltage shifts by
an amount equal to the difference between POS and
NEG multiplied by a scale factor that depends on the
DAC code (refer to the MAX1718 data sheet). The voltage between the POS and NEG inputs can be set with
a programmable voltage-divider using the MAX1888 to
connect the bottom resistor of the divider to ground
(see Figure 1.)
VOUT
NEG
TO
MAX1718
5V INPUT
POS
VCC
MAX1888
LOWVOLTAGE
LOGIC
INPUTS
DPSLP
BSM
PERF
PSM
SUS
BOM
OPEN-DRAIN
DECODER
OUTPUTS
GND
Logic Characteristics
The Intel mobile processor specifications require independent offset to the CPU core voltage for battery
sleep mode (BSM), performance sleep mode (PSM)
and battery-operating mode (BOM). No offsets are
required for the deeper-sleep mode (DPSLP) and performance mode (PERF). Table 1 explicitly describes
the logical operation of the decoder.
The decoder’s inputs may come from system-level
logic or directly from the CPU. To interface with lowvoltage logic, the MAX1888’s input logic thresholds are
designed with an input-logic high voltage of 1.2V (min)
and an input-logic low voltage of 0.3V (max). The logic
inputs also include 40mV (typ) hysteresis to improve
noise immunity.
The output on-resistance is guaranteed to be less than
100Ω over the entire supply voltage and temperature
range. When loaded with a total pullup resistance
greater than 10kΩ, the open-drain output resistance
causes less than 1% error in impedance. If the offset
voltage is set to 5% of the regulated output voltage,
then the effect of the impedance error on the output
voltage is approximately 0.05%, which is negligible in
most applications.
The MAX1888 has rising- and falling-edge propagation
delays of 70ns (typ) and 700ns (typ), respectively.
Since transition times for CPU core voltage are typically
much longer than these intervals, such delays are negligible. Note the time constant of the rising edge in the
output voltage is set by the capacitance of the opendrain output transistor and the load impedance (see
the Typical Operating Characteristics).
Figure 1. Simplified Application Circuit; Also Used for
Obtaining Characterization Data; Offset Voltage is a
Percentage of the Output Voltage.
4
BOM
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Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
C8
0.1µF
2
10
SHUTDOWN
25
VCC
24
R2
100kΩ
R3
100kΩ
5V INPUT
23
22
21
VDD
V+
BST
TON
D0
DH
D2
SUSPEND
INPUT
DECODER
R4
62kΩ
MAX1718
D3
DL
D4
ZMODE
18
SUS
S0
8
S1
FB
16
R18
24.9kΩ
SUMIDA
CEP125#4712-TO11
C4
6 x 270µF, 2V
PANASONIC SP
EEFUE0E271R
D2
CENTRAL
SEMICONDUCTOR
CMSH5-40
FDS7764A
Q2
OUTPUT
0.6V TO 1.75V
NEG
CC
BSM
PSM
BOM
5
C7
0.1µF
DPSLP
PERF
SUS
GND
R11
26.7kΩ
R12
15.8kΩ
1
2
3
LOGIC
INPUTS
4
R13
82.5kΩ
13
5V
REF
ILIM
8
MAX1888
7
4
R10
1kΩ
POS
5V INPUT
VCC
6
VGATE
12
R8
0.004Ω
15
C5
0.22µF
11
L1
0.68µH
27
TIME
C6
47pF
6
28
5
7
3
2x
IRF7811A
Q1
2x
19
REF
26
C2, 25V, X5R
5 x 10µF
D1
CMPSH-3
C3
0.1µF
LX
BATT 7V TO 24V
1
D1
GND
MUX CONTROL
C1
0.22µF
17
9
VCC
SKP/SDN
MAX1888
R1
20Ω
OVP
14
20
R5
100kΩ
POWER-GOOD
OUTPUT
R19
27.4kΩ
Figure 2. Typical Application Circuit
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5
MAX1888
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
Supply Current
VREF
The MAX1888 needs no shutdown control. The circuit
consumes virtually no current (I(VCC) < 1µA) when all
the logic inputs are 0V, and less than 30µA when all the
logic inputs are 1.5V. In general, the supply current
increases with supply voltage and decreases with the
logic input voltage. For a given supply voltage, the supply current decreases with temperature (see the
Typical Operating Characteristics).
Applications Information
Figure 2 shows a typical CPU core supply application
using the MAX1888 and the MAX1718. The voltage
dividers are set to obtain negative offsets of 1%, 3%,
and 5% of the output voltage for battery-operating
mode (BOM), battery sleep mode (BSM), and performance sleep mode (PSM), respectively. The offset voltage is given by the following equation:
VOFFSET = K (VPOS − VNEG )
where K is the DAC code-dependent scale factor (refer
to Table 3 in the MAX1718 data sheet). The offset voltage in each mode is:
VOFFSET, BOM = − K
VOFFSET, BSM = − K
VOFFSET, PSM = − K
R10
R10 + R13
R10
R10 + R11
R10
R10 + R12
TO
MAX1718
5V INPUT
POS
VCC
MAX1888
LOWVOLTAGE
LOGIC
INPUTS
DPSLP
BSM
PERF
PSM
SUS
BOM
OPEN-DRAIN
DECODER
OUTPUTS
GND
Figure 3. Using the MAX1888 to Set the Offset Voltage
Independent of VOUT
The MAX1888 can be inserted in the feedback path of
any regulator to offset the output voltage. An external
reference greater than the feedback set point is needed to affect negative offsets. The basic arrangement is
shown in Figure 4.
VOUT
VREF
VOUT
VOUT
5V INPUT
VFB
VOUT
Note that divider ratio in each mode must be adjusted
for a given DAC code. The circuit in Figure 2 assumes
VOUT = 1V with K = 0.84 and R10 = 1kΩ. The resulting
values for R11, R12, R13 in the divider are 26.7kΩ,
15.8kΩ, and 82.5kΩ, respectively. Please note that
these offsets are provided as an example only. Contact
Intel for specific offset requirements.
The circuits in Figures 1 and 2 set the offset voltage as
a percentage of the output voltage. Alternatively, the
offset can be set as independent of the output voltage
by biasing the POS and NEG inputs from a fixed reference voltage (see Figure 3).
6
NEG
VCC
MAX1888
LOWVOLTAGE
LOGIC
INPUTS
DPSLP
BSM
PERF
PSM
SUS
BOM
OPEN-DRAIN
DECODER
OUTPUTS
GND
Figure 4. Inserting the MAX1888 into the Feedback Path of Any
Regulator to Shift Output Voltage
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Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
Chip Information
TRANSISTOR COUNT: 170
PROCESS: CMOS
Package Information
4X S
8
E
ÿ 0.50±0.1
8
INCHES
DIM
A
A1
A2
b
H
c
D
e
E
H
0.6±0.1
1
L
1
α
0.6±0.1
S
BOTTOM VIEW
D
MIN
0.002
0.030
MAX
0.043
0.006
0.037
0.014
0.010
0.007
0.005
0.120
0.116
0.0256 BSC
0.120
0.116
0.198
0.188
0.026
0.016
6∞
0∞
0.0207 BSC
8LUMAXD.EPS
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MILLIMETERS
MAX
MIN
0.05
0.75
1.10
0.15
0.95
0.25
0.36
0.13
0.18
2.95
3.05
0.65 BSC
2.95
3.05
4.78
5.03
0.41
0.66
0∞
6∞
0.5250 BSC
TOP VIEW
A1
A2
e
A
α
c
b
L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0036
REV.
J
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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MAX1888
Layout Guidelines
Most applications do not drive the MAX1888 with high
frequency signals with ultra-fast transition times.
Therefore, the layout requirements are minimal. Keep
the resistive voltage-divider traces away from noisy
nodes and terminate the dividers through the MAX1888
to quiet analog ground. Place a 0.1µF decoupling
capacitor close to the device.