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Download MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches EVALUATION KIT AVAILABLE
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EVALUATION KIT AVAILABLE MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches General Description The MAX15066/MAX15166 current-mode, synchronous, DC-DC buck converters deliver an output current up to 4A with high efficiency. The devices operate from an input voltage of 4.5V to 16V and provides an adjustable output voltage from 0.606V to 90% of the input voltage. The devices are ideal for distributed power systems, notebook computers, nonportable consumer applications, and preregulation applications. The devices feature a PWM mode operation with an internally fixed switching frequency of 500kHz (MAX15066) and 350kHz (MAX15166) capable of 90% maximum duty cycle. The devices automatically enter skip mode at light loads. The current-mode control architecture simplifies compensation design and ensures a cycle-by-cycle current limit and fast response to line and load transients. A high gain transconductance error amplifier allows flexibility in setting the external compensation, simplifying the design and allowing for an all-ceramic design. The synchronous buck regulators feature internal MOSFETs that provide better efficiency than asynchronous solutions, while simplifying the design relative to discrete controller solutions. In addition to simplifying the design, the integrated MOSFETs minimize EMI, reduce board space, and provide higher reliability by minimizing the number of external components. Additional features include an externally adjustable softstart, independent enable input and power-good output for power sequencing, and thermal shutdown protection. The devices offer overcurrent protection (high-side sourcing) with hiccup mode during an output shortcircuit condition. The devices ensure safe startup when powering into a prebiased output. The MAX15066/MAX15166 are available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wafer-level package (WLP) and are fully specified from -40NC to +85NC. Applications Features S Integrated 40mΩ (High-Side) and 18.5mΩ (Low-Side) RDS-ON Power MOSFETs S High Efficiency Up to 96% (5V Input and 3.3V Output) Up to 93% (12V Input and 3.3V Output) S Continuous 4A Output Current S ±1% Output Accuracy Over Load, Line, and Temperature S 4.5V to 16V Input Voltage Range S Adjustable Output Voltage Range from 0.606V to (0.9 x VIN) S Fixed 500kHz (MAX15066) and 350kHz (MAX15166) Switching Frequencies S Programmable Soft-Start S Stable with Low-ESR Ceramic Output Capacitors S Safe Startup Into Prebiased Output S Enable Input and Power-Good Output S Cycle-by-Cycle Overcurrent Protection S Fully Protected Against Overcurrent (Hiccup Protection) and Overtemperature S Automatic Skip Mode During Light Loads S VDD LDO Undervoltage Lockout S 2mm x 2mm, 16-Bump (4 x 4 Array), 0.5mm Pitch WLP Ordering Information appears at end of data sheet. Typical Application Circuit INPUT 4.5V TO 16V IN EN VDD Distributed Power Systems 1.8V/4A OUTPUT LX MAX15066 MAX15166 FB Preregulators for Linear Regulators PGOOD Home Entertainment (TV and Set-Top Boxes) SS Network and Datacom BST COMP GND Servers, Workstations, and Storage For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. www.BDTIC.com/maxim 19-5224; Rev 4; 5/13 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches ABSOLUTE MAXIMUM RATINGS IN to GND...............................................................-0.3V to +18V EN to GND...................................................-0.3V to (VIN + 0.3V) LX to GND.............. -0.3V to the lower of +18V and (VIN + 0.3V) LX to GND (for 50ns).....-1V to the lower of +18V and (VIN + 0.3V) PGOOD to GND.......................................................-0.3V to +6V VDD to GND.............. -0.3V to the lower of +6V and (VIN + 0.3V) COMP, FB, SS to GND......................... -0.3V to the lower of +6V and (VDD + 0.3V) BST to LX ................................................................-0.3V to +6V BST to GND ...........................................................-0.3V to +24V BST to VDD ............................................................-0.3V to +18V LX RMS Current (Note 1) ................................................ 0 to 9A Converter Output and VDD Short-Circuit Duration ........................................... Continuous Continuous Power Dissipation (TA = +70NC) 16-Bump WLP (derate 20.4mW/NC above +70NC) Multilayer Board ........................................................1500mW Thermal Resistance (θJA) (Note 2)...............................23.6NC/W Operating Temperature Range .......................... -40NC to +85NC Junction Temperature (Note 3) .......................................+150NC Continuous Operating Temperature at Full Current (Note 3).................................................+105NC Storage Temperature Range ........................... -65NC to +150NC Soldering Temperature (reflow)..................................... +260NC Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed the device’s package power dissipation. Note 2: Package thermal resistances were obtained based on the MAX15066/MAX15166 evaluation kit. Note 3: Continuous operation at full current beyond +105NC can degrade product life. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 12V, CVDD = 1FF, CIN = 22FF, TA = TJ = -40NC to +85NC, typical values are at TA = TJ = +25NC, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STEP-DOWN CONVERTER Input Voltage Range VIN Quiescent Current IIN Shutdown Input Supply Current 4.5 16 V 1.1 2 mA VEN = 0V 2 6 FA VEN rising 0.7 V 70 mV Not switching ENABLE INPUT EN Shutdown Threshold Voltage VEN_SHDN EN Shutdown Voltage Hysteresis VEN_HYST EN Lockout Threshold Voltage VEN_LOCK EN Lockout Threshold Hysteresis VEN_LOCK_ EN Input Current VEN rising 1.7 1.9 2.1 200 HYST V mV IEN VEN = 12V 0.8 2.6 5 FA VPGOOD_TH VFB rising 0.54 0.56 0.585 V POWER-GOOD OUTPUT PGOOD Threshold PGOOD Threshold Hysteresis PGOOD Output Low Voltage PGOOD Leakage Current VPGOOD_ 15 HYST VPGOOD_ OL IPGOOD IPGOOD = 5mA, VFB = 0.5V 35 VPGOOD = 5V, VFB = 0.7V mV 100 mV 100 nA ERROR AMPLIFIER Error-Amplifier Transconductance 2 gMV 1.6 mS Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, CVDD = 1FF, CIN = 22FF, TA = TJ = -40NC to +85NC, typical values are at TA = TJ = +25NC, unless otherwise noted.) (Note 4) PARAMETER Error-Amplifier Voltage Gain SYMBOL CONDITIONS MIN TYP MAX UNITS 612 mV +100 nA 5.5 FA 90 AVEA 600 FB Set-Point Accuracy VFB FB Input Bias Current IFB VFB = 0.5V or 0.7V SS Current ISS VSS = 0.45V, sourcing SS Discharge Resistance RSS ISS = 10mA, sinking 606 -100 dB SOFT-START 4.5 5 6 I 9 S 0.68 V CURRENT SENSE Current Sense to COMP Transconductance gMC COMP Clamp Low VFB = 0.7V PWM CLOCK Switching Frequency fSW Maximum Duty Cycle DMAX MAX15066 MAX15166 450 315 500 350 550 385 kHz 90 % Minimum Controllable On-Time 150 ns Slope Compensation Ramp Valley 840 mV 667 mV Slope Compensation Ramp Amplitude VSLOPE Extrapolated to 100% duty cycle INTERNAL LDO OUTPUT (VDD) VDD Output Voltage VDD IVDD = 1mA, VIN = 6.5V to 16V 4.75 5.1 5.45 IVDD = 1mA to 25mA, VIN = 6.5V 4.75 5.1 5.45 30 90 VDD Short-Circuit Current VIN = 6.5V VDD LDO Dropout Voltage IVDD = 5mA, VDD drops by 2% VDD Undervoltage Lockout Threshold VDD Undervoltage Lockout Hysteresis VUVLO_TH VDD rising, LX starts switching 3.7 VUVLO_ mA 100 mV 4.1 V 3.9 150 HYST V mV POWER SWITCH LX On-Resistance High-Side Switch Source Current-Limit Threshold High-side switch, ILX = 0.4A 40 Low-side switch, ILX = 0.4A 18.5 IHSCL 7.7 A Low-Side Switch Zero-Crossing Current-Limit Threshold 0.21 A High-Side Switch Skip Sourcing Current-Limit Threshold 0.58 A LX Leakage Current BST Leakage Current BST On-Resistance 5.5 mI VBST = 21V, VIN = VLX = 16V 0.01 VBST = 5V, VIN = 16V, VLX = 0V 0.01 VBST = 21V, VIN = VLX = 16V IBST = 5mA 0.01 FA 10 I Maxim Integrated www.BDTIC.com/maxim FA 3 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, CVDD = 1FF, CIN = 22FF, TA = TJ = -40NC to +85NC, typical values are at TA = TJ = +25NC, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HICCUP PROTECTION 21 x Soft-Start Time Blanking Time THERMAL SHUTDOWN Thermal Shutdown Threshold Rising Thermal Shutdown Hysteresis 160 NC 20 NC Note 4: Specifications are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and characterization. Typical Operating Characteristics (VIN = 12V, VOUT = 1.8V, CVDD = 1FF, CIN = 22FF, COUT = 47FF, TA = +25NC (Figure 1, MAX15066), unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (MAX15066) 80 VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V 60 VOUT = 5.0V 50 80 VOUT = 1.8V VOUT = 2.5V 70 100 VOUT = 1.2V MAX15066 toc03 VOUT = 3.3V 90 EFFICIENCY (%) EFFICIENCY (%) 90 70 100 90 EFFICIENCY (%) VOUT = 5.0V MAX15066 toc02 VOUT = 3.3V MAX15066 toc01 100 EFFICIENCY vs. LOAD CURRENT (MAX15066) EFFICIENCY vs. LOAD CURRENT (MAX15066) VOUT = 3.3V 80 VOUT = 2.5V VOUT = 1.8V 70 VOUT = 1.2V 60 60 50 50 VIN = 5V 40 0 0.1 0.2 0.4 0.3 0.5 0.5 1.0 1.5 2.5 3.0 3.5 4.0 0 95 0.4 0.6 0.8 1.0 ILOAD (A) MAX15066 toc05 MAX15066 toc04 100 90 0.2 LOAD-TRANSIENT RESPONSE (MAX15066) EFFICIENCY vs. LOAD CURRENT (MAX15066) EFFICIENCY (%) 2.0 ILOAD (A) ILOAD (A) VOUT 100mV/div AC-COUPLED VOUT = 3.3V VOUT = 2.5V 85 VOUT = 1.8V 80 VOUT = 1.2V ILOAD 1A/div 0A 75 VIN = 5V 70 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 100µs/div ILOAD (A) 4 Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.8V, CVDD = 1FF, CIN = 22FF, COUT = 47FF, TA = +25NC (Figure 1, MAX15066), unless otherwise noted.) LOAD-TRANSIENT RESPONSE (MAX15066) LOAD-TRANSIENT RESPONSE (MAX15066) MAX15066 toc07 MAX15066 toc06 VOUT 100mV/div AC-COUPLED VOUT 100mV/div AC-COUPLED IOUT 2A/div IOUT 2A/div 0A 100µs/div 100µs/div EFFICIENCY (5V) vs. OUTPUT CURRENT (MAX15166) EFFICIENCY (12V) vs. OUTPUT CURRENT (MAX15166) VOUT = 1.2V 80 VOUT = 0.9V VOUT = 1.8V VOUT = 2.5V 70 MAX15066 toc09 90 EFFICIENACY (%) 90 EFFICIENACY (%) 100 MAX15066 toc08 100 80 VOUT = 1.2V VOUT = 2.5V 70 VOUT = 3.3V VOUT = 3.3V VIN = 5.0V 60 0 1 VOUT = 0.9V VOUT = 1.8V 2 3 VIN = 12.0V 60 0 4 1 2 3 4 OUTPUT CURRENT (A) OUTPUT CURRENT (A) LOAD-TRANSIENT RESPONSE (MAX15166) LOAD REGULATION MAX15066 toc10 MAX15066 toc11 0.6 VIN = 12V VOUT = 0.9V dl/dt = 1A/µs COUT = 4 x 47µF (SEE FIGURE 2 FOR OTHER VALUES) 40µs/div OUTPUT CHANGE (%) 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ILOAD (A) Maxim Integrated www.BDTIC.com/maxim 5 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.8V, CVDD = 1FF, CIN = 22FF, COUT = 47FF, TA = +25NC (Figure 1, MAX15066), unless otherwise noted.) 606.8 606.6 606.2 606.0 605.8 605.6 1A LOAD 515 FREQUENCY (kHz) 606.4 FB (mV) 525 MAX15066 toc12 607.0 MAX15066 toc13 SWITCHING FREQUENCY vs. INPUT VOLTAGE (MAX15066) FB SET POINT vs. TEMPERATURE TA = +85°C TA = +25°C 505 495 TA = -40°C 605.4 485 605.2 605.0 475 -15 10 35 60 85 4.5 6.5 TEMPERATURE (°C) 12.5 14.5 16.5 5 MAX15066 toc14 2.0 L = 2.2µH NO LOAD EN = 0V 4 SUPPLY CURRENT (µA) 1.8 INPUT CURRENT (mA) 10.5 SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE INPUT CURRENT vs. INPUT VOLTAGE (MAX15066) 1.6 1.4 3 2 1 1.2 0 1.0 4.5 6.5 8.5 10.5 12.5 14.5 16.5 4.5 6.5 8.5 10.5 12.5 14.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN WAVEFORM 16.5 MAX15066 toc17 MAX15066 toc16 3.0 2.8 SUPPLY CURRENT (µA) 8.5 INPUT VOLTAGE (V) MAX15066 toc15 -40 VEN 10V/div VOUT 1V/div 2.6 ILOAD 2A/div 2.4 2.2 VPGOOD 5V/div 2.0 -40 -15 10 35 60 85 1ms/div TEMPERATURE (°C) 6 Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.8V, CVDD = 1FF, CIN = 22FF, COUT = 47FF, TA = +25NC (Figure 1, MAX15066), unless otherwise noted.) SWITCHING BEHAVIOR (MAX15066) OUTPUT SHORT-CIRCUIT WAVEFORM MAX15066 toc19 MAX15066 toc18 VOUT 2V/div VLX 10V/div 0V VSS 1V/div 0V VOUT AC-COUPLED 10mV/div 0V IIN 0.5A/div 0A IL 2A/div IOUT 0A 10A/div 0A 20ms/div 1µs/div SOFT-START WAVEFORM SKIP MODE WAVEFORM (MAX15066) MAX15066 toc20 MAX15066 toc21 IL 2A/div VOUT AC-COUPLED 20mV/div VOUT 1V/div VLX 10V/div 0V VPGOOD 5V/div ILOAD 2A/div 0A VEN 10V/div 400µs/div 40µs/div SOFT-START TIME vs. CAPACITANCE 100.0 SOFT-START TIME (ms) STARTUP INTO PREBIAS (NO LOAD) MAX15066 toc22 1000.0 MAX15066 toc23 VOUT 1V/div 0V IL 1V/div 10.0 0A 1.0 0.1 1 10 100 CSS (nF) 0A ILOAD 2A/div 0V VEN 10V/div 1000 400µs/div Maxim Integrated www.BDTIC.com/maxim 7 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.8V, CVDD = 1FF, CIN = 22FF, COUT = 47FF, TA = +25NC (Figure 1, MAX15066), unless otherwise noted.) MAXIMUM LOAD CURRENT vs. TEMPERATURE (VIN = 12V) (MAX15066) STARTUP INTO PREBIAS (4A LOAD) MAX15066 toc24 MAX15066 toc25 10 L = 2.2µH 0V ILOAD 5A/div 0A IL 5A/div 0A VOUT = 1.8V 8 VOUT = 2.5V 7 6 VOUT = 5.0V 5 VEN 10V/div 0V VOUT = 1.2V 9 MAXIMUM LOAD CURRENT (A) VOUT 1V/div VOUT = 3.3V MAXIMUM CURRENT IS LIMITED BY THERMAL SHUTDOWN OR CURRENT LIMIT 4 -40 400µs/div -15 10 35 60 85 TEMPERATURE (°C) MAXIMUM LOAD CURRENT vs. TEMPERATURE (VIN = 5V) (MAX15066) JUNCTION TEMPERATURE vs. AMBIENT TEMPERATURE (VIN = 12V, L = 2.2uH, LOAD CURRENT = 4A) (MAX15066) 7 110 6 VOUT = 2.5V MAX15066 toc27 MAXIMUM LOAD CURRENT (A) VOUT = 1.2V JUNCTION TEMPERATURE (°C) L = 2.2µH VOUT = 1.8V 120 MAX15066 toc26 8 VOUT = 3.3V 5 VOUT = 2.5V 100 MAXIMUM CURRENT IS LIMITED BY THERMAL SHUTDOWN OR CURRENT LIMIT 90 VOUT = 3.3V 80 VOUT = 1.2V VOUT = 5V 70 VOUT = 1.8V 60 50 4 40 -40 -15 10 35 60 25 85 35 TEMPERATURE (°C) 45 55 65 85 75 AMBIENT TEMPERATURE (°C) JUNCTION TEMPERATURE vs. AMBIENT TEMPERATURE (VIN = 5V, L = 2.2µH, LOAD CURRENT = 4A) (MAX15066) MAX15066 toc28 120 JUNCTION TEMPERATURE (°C) 110 100 VOUT = 2.5V 90 VOUT = 3.3V 80 VOUT = 1.2V 70 VOUT = 1.8V 60 50 40 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (°C) 8 Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Pin Configuration TOP VIEW (BUMPS ON BOTTOM) + GND GND IN IN A1 A2 A3 A4 LX LX LX VDD B1 B2 B3 B4 BST I.C. I.C. EN C1 C2 C3 C4 PGOOD FB COMP SS D1 D2 D3 D4 WLP Pin Description BUMP NAME A1, A2 GND A3, A4 IN Power-Supply Input. Input supply range is from 4.5V to 16V. Connect A3 and A4 together as close as possible to the device. Bypass IN to GND with a minimum 22FF ceramic capacitor as close as possible to the device. B1, B2, B3 LX Inductor Connection. Connect an inductor between LX and the regulator output. LX is high impedance when the device is in shutdown mode. Connect all LX nodes together as close as possible to the device. B4 VDD Internal 5V LDO Output. VDD powers the internal analog core. Connect a minimum of 1FF ceramic capacitor from VDD to GND. C1 BST High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.01FF capacitor. BST is internally connected to the VDD regulator through a pMOS switch. C2, C3 I.C. Internal Connection. Leave unconnected. EN Enable Input. Connect EN to GND to disable the device. Set EN to above 1.9V (typ) to enable the device. EN can be shorted to IN for always-on operation. C4 FUNCTION Ground. Connect A1 and A2 together as close as possible to the device. D1 PGOOD Power-Good Output. PGOOD is an open-drain output that goes high impedance when VFB exceeds 0.56V (typ). PGOOD is internally pulled low when VFB falls below 0.545V (typ). PGOOD is internally pulled low when the device is in shutdown mode, VDD is below the UVLO threshold, or the device is in thermal shutdown. D2 FB Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set the output voltage from 0.606V to 90% of VIN. D3 COMP D4 SS Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to GND (see the Compensation Design section). Soft-Start Timing Capacitor Connection. Connect a capacitor from SS to GND to set the startup time (see the Setting the Soft-Start Time section). Maxim Integrated www.BDTIC.com/maxim 9 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Block Diagram EN ENABLE CONTROL AND THERMAL SHUTDOWN VDD 5V LDO UVLO COMPARATOR 3.9V/3.75V BST BIAS GENERATOR VDD CURRENT-SENSE AMPLIFIER AND CURRENT LIMIT VOLTAGE REFERENCE IN LX LX CONTROL LOGIC MAX15066 MAX15166 VDD 1.6V CLAMP GND 5µA ZERO-CROSSING CURRENT LIMIT PWM COMPARATOR 0.606 SS FB ERROR AMPLIFIER C COMP OSCILLATOR 0.560V RISING, 0.545V FALLING 10 POWER-GOOD COMPARATOR PGOOD MAX15066 (500kHz) MAX15166 (350kHz) Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches INPUT 4.5V TO 16V IN BST EN LX 22µF 10nF VDD 1µF MAX15066 MAX15166 10kI 2.2µH COUT OUTPUT 270pF R1 FB COMP PGOOD RCOMP SS GND 10nF CCOMP 10kI COMPONENT MAX15066 MAX15166 COUT 1 x 47µF 4 x 47µF RCOMP 7.5kI 7.5kI CCOMP 2700pF 2700pF R1 20kI 5.1kI VOUT 1.8V 0.9V Figure 1. Reference Circuit Detailed Description The MAX15066/MAX15166 are high-efficiency, peak current-mode, step-down DC-DC converters with integrated high-side (40mI) and low-side (18.5mI) power switches. The output voltage is set from 0.606V to 0.9 x VIN by using an external resistive divider and can deliver up to 4A of load current. The input voltage range is 4.5V to 16V, making these devices ideal for distributed power systems, notebook computers, nonportable consumer applications, and preregulation applications. The devices feature a PWM, internally fixed switching frequency of 500kHz (MAX15066) and 350kHz (MAX15166) with a 90% maximum duty cycle. PWM current-mode control allows for an all-ceramic capacitor solution. The devices include a high gain transconductance error amplifier. The current-mode control architecture simplifies compensation design, and ensures a cycle-by-cycle current limit and fast reaction to line and load transients. The low RDS-ON, internal MOSFET switches ensure high efficiency at heavy loads and minimize critical inductances, reducing layout sensitivity. The devices feature thermal shutdown, overcurrent protection (high-side sourcing and hiccup protection), and an internal 5V (25mA) LDO with undervoltage lockout. An externally adjustable voltage soft-start gradually ramps up the output voltage and reduces inrush current. At light loads, as soon as a low-side MOSFET zero-crossing event is detected, the devices automatically switch to pulse-skipping mode to keep the quiescent supply current low and enhances the light load efficiency. An independent enable input controls and the power-good output allow for flexible power sequencing. The devices also provide the ability to start up into a prebiased output. Controller Function—PWM Logic and Skip Mode The devices employ PWM control with a constant switching frequency of 500kHz (MAX15066) or 350kHz (MAX15166) at medium and heavy loads, and skip mode at light loads. When EN is high, after a brief settling time, PWM operation starts when VSS exceeds the FB voltage, at the beginning of soft-start. The first operation is always a high-side turn-on at the beginning of the clock cycle. The high side is turned off when any of the following conditions occur: 1)COMP voltage exceeds the internal current-mode ramp waveform, which is the sum of the slope compensation ramp and the current-mode ramp derived from the inductor current waveform (through the current-sense block). 2) The high-side current limit is reached. 3) The maximum duty cycle of 90% is reached. The low side turns off when the clock period ends or when the zero-crossing current threshold is intercepted. The devices monitor the inductor current during every switch cycle and automatically enters discontinuous mode when the inductor current valley intercepts the zero-crossing threshold (under light loads); under very light load conditions, skip mode is activated/deactivated on a cycle-by-cycle basis. Maxim Integrated www.BDTIC.com/maxim 11 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches The devices enter discontinuous mode when load current (ILOAD) and inductor ripple current (DIL) are such that: ∆IL 1 V − VOUT VOUT = 0.21A (typ) ILOAD − = ILOAD − × IN × 2 2 L × fSW VIN During skip-mode operation, the devices skip switch cycles, switching only as needed to service the load. This reduces the switching frequency and associated losses in the internal switch, the synchronous rectifier, and the inductor. In skip mode, to avoid the occasional switch cycle “bursts” (and reduce power losses), a fixed on-time is forecasted using a skip current-limit flag (0.58A, typ). The on-time, even if controlled by COMP, cannot be lower than the time needed for the inductor current to reach 0.58A. Starting into a Prebiased Output The devices are capable of safely soft-starting into a prebiased output without discharging the output capacitor. Starting up into a prebiased condition, both low-side and high-side switches remain off to avoid discharging the prebiased output. PWM operation starts only when the SS voltage crosses the FB voltage. During soft-start, zero crossing is activated to avoid reverse current in the device. Enable Input and Power-Good Output The devices feature independent device enable control and power-good signals that allow for flexible power sequencing. The enable input (EN) accepts a digital input with a 1.9V (typ) threshold. Apply a voltage exceeding the threshold on EN to enable the regulator, or connect EN to IN for always-on operations. Powergood (PGOOD) is an open-drain output that deasserts (goes high impedance) when VFB is above 0.56V (typ), and asserts low if VFB is below 0.545V (typ). When the EN voltage is higher than 0.7V (typ) and lower than 1.9V (typ), most of the internal blocks are disabled; only an internal coarse preregulator, including the EN accurate comparator, is kept on. An external voltagedivider from IN to EN to GND can be used to set the device turn-on threshold. Programmable Soft-Start (SS) The devices utilize a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. Connect a capacitor from SS to GND to set the startup time (see the Setting the Soft-Start Time section for capacitor selection details). Internal LDO (VDD) The devices include an internal 5V (typ) LDO. VDD is externally compensated with a minimum 1FF, low-ESR 12 ceramic capacitor. VDD supplies the low-side switch driver, and the internal control logic. The VDD output current limit is 90mA (typ) and a UVLO circuit inhibits switching when VDD falls below 3.75V (typ). Error Amplifier A high gain-error amplifier provides accuracy for the voltage feedback loop regulation. Connect the necessary compensation network between COMP and GND (see the Compensation Design Guidelines for details). The error-amplifier transconductance is 1.6mS (typ). COMP clamp low is set to 0.68V (typ), just below the slope compensation ramp valley, helping COMP to rapidly return to correct set point during load and line transients. PWM Comparator The PWM comparator compares COMP voltage to the current-derived ramp waveform (LX current to COMP voltage transconductance value is 9A/V typ). To avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a slope compensation ramp is added to the current-derived ramp waveform. The compensation ramp (0.667V x 500kHz) for the MAX15066 and (0.667V x 350kHz) for the MAX15166 is equivalent to half of the inductor current down slope in the worst case (load 4A, current ripple 30% and maximum duty-cycle operation of 90%). Overcurrent Protection and Hiccup Mode When the converter output is shorted or the device is overloaded, the high-side MOSFET current-limit event (7.7A, typ) turns off the high-side MOSFET and turns on the low-side MOSFET. In addition, the device discharges the SS capacitor (CSS) for a fixed period of time (70ns, typ) through the internal SS low-side switch RDS-ON (RSS). If the overcurrent condition persists, the device continues discharging CSS until VSS drops below 0.606V and a hiccup event is triggered. The regulator softly resets by pulling COMP low, turning off the high-side and turning on the low-side, until the low-side zero-crossing current threshold is reached. The highside and low-side MOSFETs remain off and COMP is pulled low for a period equal to 21 times the nominal soft-start time (blanking time). This is obtained by charging SS from 0 to 0.606V with a 5FA (typ) current, and then slowly discharging it back to 0V with a 250nA (typ) current. After the blanking time has elapsed, the device attempts to restart. If the overcurrent fault has cleared, the device resumes normal operation. Otherwise, a new hiccup event is triggered (see the Output Short-Circuit Waveform in the Typical Operating Characteristics). Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Thermal-Shutdown Protection The devices contain an internal thermal sensor that limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +160NC (typ), the thermal sensor shuts down the device, turning off the DC-DC converter and the LDO regulator to allow the die to cool. The regulator softly resets by pulling COMP low, discharging soft-start, turning off the high-side and turning on the low-side, until the low-side zero-crossing current threshold is reached. After the die temperature falls by 20NC (typ), the device restarts, using the softstart sequence. Applications Information Setting the Output Voltage Connect a resistive divider (R1 and R2, see Figure 3) from OUT to FB to GND to set the DC-DC converter output voltage. Choose R1 and R2 so that the DC errors due to the FB input bias current do not affect the outputvoltage accuracy. With lower value resistors, the DC error is reduced, but the amount of power consumed in the resistive divider increases. A typical trade-off value for R2 is 10kI, but values between 5kI and 50kI are acceptable. Once R2 is chosen, calculate R1 using: V R1 = R2 × OUT − 1 VFB where the feedback threshold voltage VFB = 0.606V (typ). When regulating an output of 0.606V, short FB to OUT and keep R2 connected from FB to GND. Maximum/Minimum Voltage Conversion Ratio The maximum voltage conversion ratio is limited by the maximum duty cycle (DMAX): VOUT D × VDROP2 + (1 − D MAX ) × VDROP1 < D MAX + MAX VIN VIN where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances. VDROP2 is an absolute value and the sum of the resistances in the charging path, including the high-side switch, inductor, and PCB resistances. The minimum voltage conversion ratio is limited by the minimum duty cycle (DMIN): VOUT V V > D MIN + D MIN × DROP2 + (1 − D MIN) × DROP1 VIN VIN VIN where DMIN = fOSC x tON(min); fOSC is 500kHz/350kHz for the MAX15066/MAX15166, respectively, and tON(min) is typically 150ns. See the specifications in the Electrical Characteristics table. Inductor Selection A larger inductor value results in reduced inductor ripple current, leading to a reduced output ripple voltage. However, a larger inductor value results in either a larger physical size or a higher series resistance (DCR) and a lower saturation current rating. Typically, the inductor value is chosen to have current ripple equal to 30% of load current. Choose the inductor with the following formula: = L V VOUT × 1 − OUT fSW × ∆IL VIN where fSW is the internally fixed switching frequency of 500kHz (MAX15066) or 350kHz (MAX15166), and DIL is the estimated inductor ripple current (DIL = LIR x ILOAD, where LIR is the inductor current ratio). In addition, the peak inductor current, IL_PK, must always be below both the minimum high-side current-limit value (7.7A, typ), and the inductor saturation current rating, IL_SAT. Ensure that the following relationship is satisfied: IL_PK = ILOAD + 1 × ∆IL < min(IHSCL ,IL_SAT ) 2 Input Capacitor Selection For a step-down converter, input capacitor CIN helps reduce input ripple voltage, in spite of discontinuous input AC current. Low-ESR capacitors are preferred to minimize the voltage ripple due to ESR. For low-ESR input capacitors, size CIN using the following formula: = CIN ILOAD V × OUT fSW x ∆VIN_RIPPLE VIN For high-ESR input capacitors, the additional ripple contribution due to ESR (DVIN_RIPPLE_ESR) is calculated as follows: δVIN_RIPPLE = RESR_IN(ILOAD + δIL/2) where RESR_IN is the ESR of the input capacitor. The RMS input ripple current is given by: IRIPPLE = ILOAD × VOUT × (VIN − VOUT ) VIN Maxim Integrated www.BDTIC.com/maxim 13 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Output-Capacitor Selection The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL. Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL as follows: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: VRIPPLE(C) = ∆IP −P 8 × C OUT × fSW VRIPPLE(ESR) = ∆IP −P × ESR and VRIPPLE(ESL) can be approximated as an inductive divider from LX to GND: VRIPPLE (ESL) =VLX × ESL ESL =VIN × L L where VLX swings from VIN to GND. The peak-to-peak inductor current (DIP-P) is: VOUT VIN (VIN − VOUT ) × ∆IP −P = L × fSW When using ceramic capacitors, which generally have low-ESR, DVRIPPLE(C) dominates. When using electrolytic capacitors, DVRIPPLE(ESR) dominates. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. As a general rule, a smaller inductor ripple current results in less output ripple voltage. Since inductor ripple current depends on the inductor value and input voltage, the output ripple voltage decreases with larger inductance and increases with higher input voltages. However, the inductor ripple current also impacts transient-response performance, especially at low VIN to VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. 14 Load-transient response also depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ∆ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to the predetermined value. Use higher COUT values for applications that require light-load operation or transition between heavy load and light load, triggering skip mode, causing output undershooting or overshooting. When applying the load, limit the output undershooting by sizing COUT according to the following formula: ∆ILOAD C OUT = 3fCO × ∆VOUT where ∆ILOAD is the total load change, fCO is the unitygain bandwidth (or zero-crossing frequency), and ∆VOUT is the desired output undershooting. When removing the load and entering skip mode, the device cannot control output overshooting, since it has no sink current capability; see the Skip Mode Frequency and Output Ripple section to properly size COUT under this circumstance. A worst-case analysis in sizing the minimum output capacitance takes the total energy stored in the inductor into account, as well as the allowable sag/soar (undershoot/overshoot) voltage as follows: C OUT (MIN) = C OUT(MIN) = ( L × I 2 OUT(MAX) − I 2 OUT(MIN) (VFIN + VSOAR ) 2 2 − V INIT ( L × I 2 OUT(MAX) − I 2 OUT(MIN) 2 V INIT − (VFIN − VSAG ) 2 ) , voltage soar (overshoot) ) , voltage sag (undershoot) where IOUT(MAX) and IOUT(MIN) are the initial and final values of the load current during the worst-case load dump, VINIT is the initial voltage prior to the transient, VFIN is the steady-state voltage after the transient, VSOAR is the allowed voltage soar (overshoot) above VFIN, and VSAG is the allowable voltage sag below VFIN. The terms (VFIN + VSOAR) and (VFIN - VSAG) represent the maximum/minimum transient output voltage reached during the transient, respectively. Use these equations for initial output-capacitor selection. Determine final values by testing a prototype or an evaluation circuit under the worst-case conditions. Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches or approximately as: IL ISKIP-LIMIT ILOAD tON tOFF1 VOUT-RIPPLE tOFF2 = n x TCK VOUT 1 1 + t OFF2 = L × ISKIP −LIMIT × VIN − VOUT VOUT I × SKIP −LIMIT − ILOAD 2 ILOAD Finally, frequency in skip mode is: fSKIP = Figure 2. Skip Mode Waveform 1 t ON + t OFF1 + t OFF2 Output ripple in skip mode is: Skip Mode Frequency and Output Ripple In skip mode, the switching frequency (fSKIP) and output = VOUT −RIPPLE VCOUT −RIPPLE + VESR−RIPPLE ripple voltage (VOUT_RIPPLE) shown in Figure 2 are cal−I (I ) × t ON + culated as follows: = SKIP −LIMIT LOAD C OUT tON is the time needed for inductor current to reach SKIP R ESR,COUT × (I SKIP −LIMIT − ILOAD ) current limit (0.58A, typ): t ON = L × I SKIP −LIMIT VIN − VOUT [1] tOFF1 is the time needed for inductor current to reach the zero current limit (~0A): t OFF1 = L × I SKIP −LIMIT VOUT [2] During tON and tOFF1 the output capacitor stores a charge equal to (see Figure 2): 1 Q OUT I SKIP −LIMIT × (t ON + t OFF1) ∆ = 2 − ILOAD × (t ON + t OFF1) [3] Combining [1], [2] and [3], and solving for DQOUT: I L × I SKIP −LIMIT × SKIP −LIMIT − ILOAD 2 1 1 × + V V V − OUT OUT ∆Q OUT = IN 2 During tOFF2 (= n x tCK, number of clock cycles skipped), the output capacitor loses this charge or can approximate as: t OFF2 = To limit output ripple in skip mode, size COUT based on the above formula accordingly. All formulas above are valid for ILOAD < ISKIP-LIMIT. Compensation Design Guidelines The devices use a fixed-frequency, peak current-mode control scheme to provide easy compensation and fast transient response. The inductor peak current is monitored on a cycle-by-cycle basis and compared to the COMP voltage (output of the voltage error amplifier). The regulator’s duty cycle is modulated based on the inductor’s peak current value. This cycle-by-cycle control of the inductor current emulates a controlled current source. As a result, the inductor’s pole frequency is shifted beyond the gain bandwidth of the regulator. System stability is provided with the addition of a simple series capacitor-resistor from COMP to GND. This polezero combination serves to tailor the desired response of the closed-loop system. The basic regulator loop consists of a power modulator (comprising the regulator’s pulse-width modulator, slope compensation ramp, control circuitry, MOSFETs, and inductor), the capacitive output filter and load, an output feedback divider, and a voltage-loop error amplifier with its associated compensation circuitry (see Figure 3). ∆Q OUT ILOAD Maxim Integrated www.BDTIC.com/maxim 15 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches FEEDBACK DIVIDER POWER MODULATOR ERROR AMPLIFIER COMPENSATION RAMP VOUT R1 *CFF C FB OUTPUT FILTER AND LOAD VIN gMC COMP VFB QHS IL L CONTROL LOGIC VCOMP gMV R2 PWM COMPARATOR RC ROUT DCR QLS VOUT IOUT ESR RLOAD COUT CC VCOMP GMOD VOUT IL ROUT = REF 10 AVEA(dB)/20 gMV NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR, IL, INJECTED INTO THE OUTPUT LOAD, IOUT, e.g., IL = IOUT. SUCH CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER STAGE CIRCUITRY SHOWN WITHIN THE BOXED AREA. *CFF IS OPTIONAL, DESIGNED TO EXTEND THE REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS. Figure 3. Peak Current-Mode Regulator Transfer Model The average current through the inductor is expressed as: = IL G MOD × VCOMP where IL is the average inductor current and GMOD is the power modulator’s transconductance. For a buck converter: = VOUT R LOAD × IL where RLOAD is the equivalent load resistor value. Combining the above two relationships, the power modulator’s transfer function in terms of VOUT with respect to VCOMP is: VOUT R LOAD × IL = = R LOAD × G MOD IL VCOMP G MOD The peak current-mode controller’s modulator gain is attenuated by the equivalent divider ratio of the load resistance and the current-loop gain. GMOD becomes: 1 G MOD (DC = ) gMC × R LOAD × K S × (1 − D) − 0.5 1 + × f L SW where RLOAD = VOUT/IOUT(MAX), fSW is the switching frequency, L is the output inductance, D is the duty cycle (VOUT/VIN), and KS is the slope compensation factor calculated from the following equation: S V ×f × L × g MC KS = 1 + SLOPE = 1 + SLOPE SW SN (VIN − VOUT ) where: S= SLOPE VSLOPE = VSLOPE × fSW t SW SN = 16 (VIN − VOUT ) L × g MC Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches As previously mentioned, the power modulator’s dominate pole is a function of the parallel effects of the load resistance and the current-loop gain’s equivalent impedance: fPMOD = 1 −1 1 K S × (1 − D) − 0.5 2π × C OUT × ESR + + RLOAD fSW × L Knowing that the ESR is typically much smaller than the parallel combination of the load and the current loop, e.g.,: 1 K S × (1 − D) − 0.5 + ESR << R LOAD fSW × L fPMOD ≈ −1 1 1 K S × (1 − D) − 0.5 2π × C OUT × + RLOAD fSW × L −1 where the sampling effect quality factor, QC, is: QC = and the resonant frequency is: wSAMPLING(s) = π × fSW or: f fSAMPLING = SW 2 Having defined the power modulator’s transfer function, the total system transfer can be written as follows (Figure 3): Gain(s) = GFF(s) × GEA(s) × GMOD(DC) × GFILTER(s) × GSAMPLING(s) where: G = FF (s) This can be expressed as: fPMOD ≈ K S × (1 − D) − 0.5 + 2π × C OUT × R LOAD 2π × fSW × L × C OUT 1 1 π × K S × (1 − D) − 0.5 (sC FFR1 + 1) R2 × R1 + R2 sC FF (R1|| R2) + 1 Leaving CFF empty, GFF(s) becomes: G FF (s) = R2 R1 + R2 Note: Depending on the application’s specifics, the amplitude of the slope compensation ramp could have a Also: significant impact on the modulator’s dominate pole. For (sC CR C + 1) low duty-cycle applications, it provides additional damp-= GEA (s) 10 AVEA(dB)/20 × ing (phase lag) at/near the crossover frequency. See the 10 AVEA(dB)/20 sC C R C + + 1 Closing the Loop: Designing the Compensation Circuitry g MV section. There is no equivalent effect on the power modulator zero: AVEA(dB)/20 If RC << 10 , the equation simplifies to: 1 MV fZMOD = fZESR = 2π × C OUT × ESR The effect of the inner current loop at higher frequencies is modeled as a double-pole (complex conjugate) frequency term, GSAMPLING(s), as shown: G SAMPLING (s) = = G EA (s) 10 AVEA(dB)/20 × 1 s 2 (π × fSW ) 2 + s π × fSW × Q C +1 G FILTER = (s) RLOAD × (sC CR C + 1) 10 AVEA(dB)/20 sC C + 1 gMV (sC OUTESR + 1) −1 1 sC K S × (1 − D) − 0.5 + 1 + OUT 2π × R 2π × fSW × L LOAD Maxim Integrated www.BDTIC.com/maxim 17 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches 1ST ASYMPTOTE R2 x (R1 + R2)-1 x 10AVEA(dB)/20 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 2ND ASYMPTOTE R2 x (R1 + R2)-1 x gMV x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 GAIN 3RD ASYMPTOTE R2 x (R1 + R2)-1 x gMV x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 4TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 3RD POLE 2ND ZERO 0.5 x fSW (2GCOUTESR)-1 UNITY 1ST ZERO (2GCCRC)-1 1ST POLE [2GCC(10AVEA(dB)/20 x gMV-1)]-1 FREQUENCY fCO 2ND POLE fPMOD* 5TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x [(2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 x (0.5 x fSW)2 x (2Gf)-2 NOTE: ROUT = 10AVEA(dB)/20 x gMV-1 fPMOD = [2GCOUT x (ESR + {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)]-1 WHICH FOR ESR << {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1 6TH ASYMPTOTE R2 x (R1 + R2)-1 x gMV x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x ESR x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1 x (0.5·fSW)2 x (2Gf)-2 BECOMES fPMOD = [2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1]-1 fPMOD = (2GCOUT x RLOAD)-1 + [KS(1 – D) – 0.5] x (2GCOUT x L x fSW)-1 Figure 4. Asymptotic Loop Response of Peak Current-Mode Regulator The dominant poles and zeros of the transfer loop gain are shown below: fP1 << fP2 = g MV 2π × C C × 10 AVEA(dB) /20 1 1 K S × (1 − D) − 0.5 2π × C OUT + RLOAD fSW × L fSW fP3 = 2 1 1 fZ1 = fZ2 = 2π × C CR C 2π × C OUTESR The order of pole-zero occurrences is: fP1 < fP2 ≤ fZ1 < fCO < fP3 < fZ2 Note: Under heavy load, fP2 can approach fZ1. 18 −1 Figure 4 shows a graphical representation of the asymptotic system closed-loop response, including dominant pole and zero locations. The loop response’s fourth asymptote (in bold, Figure 4) is the one of interest in establishing the desired crossover frequency (and determining the compensation component values). A lower crossover frequency provides for stable closed-loop operation at the expense of a slower load and line transient response. Increasing the crossover frequency improves the transient response at the (potential) cost of system instability. A standard rule of thumb sets the crossover frequency P 1/5 to 1/10 of the switching frequency. First, select the passive power components that meet the application’s requirements. Then, choose the smallsignal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined in the Closing the Loop: Designing the Compensation Circuitry section. Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Closing the Loop: Designing the Compensation Circuitry 1) Select the desired crossover frequency. Choose fCO between 1/5 to 1/10 of fSW. 2) Select RC by setting the system transfer’s fourth asymptote gain equal to unity (assuming fCO > fZ1, fP2, and fP1). RC becomes: R LOADK S (1 − D) − 0.5 1 + L × fSW R1 + R2 × 2πf C RC = × CO OUT × R2 g MV × g MC × R LOAD 1 ESR + K 1 D 0.5 − − ( ) 1 S + R LOAD L × fSW and where the ESR is much smaller than the parallel combination of the equivalent load resistance and the current-loop impedance, e.g.,: ESR << 1 1 K S (1 − D) − 0.5 + R LOAD L × fSW RC becomes: = RC R1 + R2 2πfCO × C OUT × R2 g MV × g MC 3) Select CC. CC is determined by selecting the desired first system zero, fZ1, based on the desired phase margin. Typically, setting fZ1 below 1/5 of fCO provides sufficient phase margin. f 1 = fZ1 ≤ CO 2π × C CR C 5 therefore: CC ≥ 5 2π × fCO × R C Optional: For low duty-cycle applications, the addition of a phase-leading capacitor (CFF in Figure 3) helps mitigate the phase lag of the damped half-frequency double pole. Adding a second zero near to but below the desired crossover frequency increases both the closed-loop phase margin and the regulator’s unity-gain bandwidth (crossover frequency). Select the capacitor as follows: C FF = 1 2π × fCO × (R1|| R2) This guarantees the additional phase-leading zero occurs at a frequency lower than fCO from: fPHASE_LEAD = 1 2π × C FF × R1 Using CFF, the zero-pole order is adjusted as follows: fP1 < fP2 ≤ fZ1 < 1 1 < 2πC FFR1 2πC FF (R1|| R2) ≈ fCO < fP3 < fZ2 Confirm the desired operation of CFF empirically. The phase lead of CFF diminishes as the output voltage is a smaller multiple of the reference voltage, e.g., below about 1V. Do not use CFF when VOUT = VFB. Setting the Soft-Start Time The soft-start feature ramps up the output voltage slowly, reducing input inrush current during startup. Size the CSS capacitor to achieve the desired soft-start time (tSS) using: I ×t C SS = SS SS VFB ISS, the soft-start current, is 5FA (typ) and VFB, the output feedback voltage threshold, is 0.606V (typ). When using large COUT capacitance values, the high-side current limit can trigger during soft-start period. To ensure the correct soft-start time tSS, choose CSS large enough to satisfy: C SS >> C OUT × VOUT × I SS (IHSCL − IOUT ) × VFB IHSCL is the typical high-side switch current-limit value. Maxim Integrated www.BDTIC.com/maxim 19 MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Layout Procedure Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX15066/MAX15166 evaluation kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1) Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. Connect the signal ground plane to the power ground plane at a single point adjacent to the ground bump of the IC. 2) Place capacitors on VDD, IN, and SS as close as possible to the device and the corresponding pin using direct traces. Keep the power ground plane and signal ground plane separate. Connect all GND bumps at only one common point near the input bypass capacitor return terminal. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. 4) Connect IN, LX, and GND separately to large copper areas to help cool the device to further improve efficiency and long-term reliability. 5) For better thermal performance, maximize the copper trace widths for consecutive bumps (LX, IN, GND) using solder mask (SMD) lands. 6) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the device. 7) Route high-speed switching nodes (such as LX and BST) away from sensitive analog areas (such as SS, FB, and COMP). Ordering Information PIN-PACKAGE FREQUENCY MAX15066EWE+ PART -40°C to +85°C TEMP RANGE 16 WLP 500kHz MAX15166EWE+ -40°C to +85°C 16 WLP 350kHz +Denotes a lead(Pb)-free/RoHS-compliant package. Chip Information PROCESS: BiCMOS 20 Package Information For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 WLP W162B2+1 21-0200 — Maxim Integrated www.BDTIC.com/maxim MAX15066/MAX15166 High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches Revision History REVISION NUMBER REVISION DATE 0 4/10 Initial release 4/10 Revised the General Description, Absolute Maximum Ratings, Typical Operating Characteristics, and the PWM Comparator, Output-Capacitor Selection, Compensation Design Guidelines, and the Closing the Loop: Designing the Compensation Circuitry sections. Updated Figures 3 and 4. 2 5/10 Revised the Electrical Characteristics, PWM Comparator, Output Capacitor Selection, Skip Mode Frequency and Output Ripple, Compensation Design Guidelines, Closing the Loop: Designing the Compensation Circuitry, and the Layout Procedure sections and Figures 3 and 4. 3 9/10 Revised the Electrical Characteristics and PWM Comparator sections. 3, 11 4 5/13 Added MAX15166 1–20 1 DESCRIPTION PAGES CHANGED — 1, 2, 4, 10, 13, 15–18 3, 11, 13–19 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2013 Maxim Integrated Products, Inc. www.BDTIC.com/maxim 21 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.